CN1147146A

CN1147146A - Deprocessing method for analyzing failure in semiconductor device

Info

Publication number: CN1147146A
Application number: CN96111009A
Authority: CN
Inventors: 具政会; 金哲弘
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1995-06-30
Filing date: 1996-06-30
Publication date: 1997-04-09
Also published as: KR100216674B1; DE19626026A1; GB2302987A; GB9613789D0; TW318950B; JPH0922932A; GB2302987B; KR970003748A

Abstract

A deprocessing method for analyzing a polysilicon contact open failure and contact misalignment in a semiconductor device comprises the steps of: removing a passivation layer and double metal layer placed on a wafer including a memory cell thereon; selectively removing the upper portions of a polysilicon forming a capacitor and polysilicon forming a bit line through plasma dry etch; and carrying out wet etch using an etchant having HF to expose a field oxide layer, and at the same time, to leave the lower portions of the polysilicon layer forming the bit line, and a polysilicon layer forming a capacitor storage node on the wafer.

Description

Deprocessing method about the analyzing semiconductor component failure

The present invention relates to the Failure Analysis method that in the semiconductor device forming process, produces, particularly be used to expose the deprocessing method of semiconductor device polysilicon contact, so that reach confirmation produces the contact open failure at polysilicon contact place purpose.

Along with the increase of semiconductor device integrated level, the component structure that forms semiconductor device becomes three-dimensional labyrinth, so that obtain enough big capacity in the zone that limits.This requires to expose with senior stripping layer treatment technology the failure conditions of the laminated construction that results from the integrated semiconductor device of height.

Disconnect situation about losing efficacy for reaching analysis at the contact of semiconductor device polysilicon contact place generation, in common process, observe by making and dissect sample.But there is following problems in this anatomic observation method.That is, be difficult to find failure site.Because the polysilicon layer quilt is such as coverings such as metal and oxide passivation layers, it is very little analyzing the zone of losing efficacy.

Therefore, when carrying out the contact failure analysis, utilize deprocessing method,, remove each lamination successively, then can observe the failure site of each layer successively from its top layer.According to the method, the polysilicon layer that corrosion contacts with silicon substrate is observed the failure site that produces then in substrate, confirm thus whether contact disconnects.But whether this method can not observe directly contact and disconnect.And during the corrosion polysilicon layer, enlarged the contact position, make its contact, as shown in Figure 1 greater than reality.Therefore, be difficult to confirm the actual contact size and the contact position of aligning.And in the analysis of failure mechanism that can be produced by identical failure mode, routine analyzer can not correspondingly be finished.

The purpose of this invention is to provide a kind of deprocessing method that analyzing semiconductor device polysilicon contact disconnects failure conditions that is used for, whether this method can accurately detect polysilicon and disconnect, and points out the position of its aligning.

For realizing purpose of the present invention, a kind of deprocessing method is provided, be used for analyzing semiconductor device polysilicon contact and disconnect failure conditions, it comprises the following steps: to remove passivation layer and the double-metal layer that is positioned on the wafer that comprises memory cell; Utilize plasma dry corrosion (RIE is a reactive ion etching) method, remove polysilicon that forms capacitor and the top section that forms the polysilicon of bit line; And utilize the corrosive agent that comprises HF to carry out wet corrosion, so that expose field oxide, simultaneously, on wafer, stay polysilicon layer that forms bit line and the underclad portion that forms the polysilicon layer of capacitor storage node.

By understanding the distinctive novel feature of the present invention well to being described in detail of specific embodiment with reference to the accompanying drawings.In the accompanying drawing:

Fig. 1 is a microphoto, represents that the polysilicon contact disconnects the used sample that lost efficacy in the technical Analysis semiconductor device routinely;

Fig. 2 A and Fig. 2 B are cutaway views, the method that expression is handled according to embodiment of the invention stripping layer;

Fig. 3 is a microphoto, and expression is shelled the plane graph that layer is handled sample according to the present invention.

Below with reference to the accompanying drawing narration preferred embodiment of the invention.

Fig. 2 A and Fig. 2 B are cutaway views, the stripping layer treatment process of expression analyzing semiconductor device capacitor contact and bit line contact.Fig. 2 A represents to be the manufacturing failure analytic sample according to the structure of the method formation of making DRAM, utilizes conventional deprocessing method, removes its passivation layer (pass-ivation layer) and metal level.In Fig. 2 A, label 21 expression silicon substrates, 22 expression field oxides, 23 expression gate oxides, 24 expressions form the polysilicon layer of electrode, 25 expression dielectric isolation layers, 26 expression source and drain regions, 27 expressions, first interlayer insulating film, 28 expressions form the polysilicon layer of bit line, 29 expressions, second interlayer insulating film, and 30 expressions form the polysilicon layer of capacitor storage node, the dielectric layer of 31 expression electric capacity, 32 expressions form the polysilicon layer of capacitor plate electrode.Shown in Fig. 2 A, polysilicon layer 28 forms with the drain region with the source region of silicon substrate 21 with polysilicon layer 30 and contacts.

Shown in Fig. 2 B, utilize CF ₄And O ₂, in RIE (reactive ion etching equipment), carry out the plasma dry corrosion, selectively corrosion forms the polysilicon layer top of capacitor fin (a) (shown in Fig. 2 A) and the top of bit line polysilicon layer 28.Then, utilize the corrosive agent that contains about 49%HF, suitably carry out wet corrosion,, on silicon base, stay the bottom of bit line polysilicon layer 28 and storage node polysilicon layer 30 so that expose field oxide.Like this, on substrate contact region, stay the residual fraction of polysilicon.

By observing the structure shown in Fig. 2 B, the present invention can prove conclusively the inefficacy of polysilicon contact.That is, stay the residual polycrystalline silicon part of contact zone, can analyze the quality of contact lamination easily and confirm whether contact disconnects by observation.And, can analyze the failure mechanism that in substrate, produces.Fig. 3 is a microphoto, and expression as shown in Figure 3, can accurately be determined the contact position and measure its size according to the sample that the present invention exposes the storage node contacts district.

Therefore, should understand, the invention is not restricted to above-mentioned disclosed as the specific embodiment of realizing best way of the present invention.The specific embodiments that the present invention is not limited in the specification to be narrated except that appended claim of the present invention limits.

Claims

1, a kind of analyzing semiconductor device polysilicon contact disconnects the deprocessing method that lost efficacy, and it comprises the following steps:

Remove passivation layer and double-metal layer on the wafer, comprise a memory cell on the said wafer;

Utilize the plasma dry etching method, selectively remove polysilicon that forms capacitor and the top section that forms the polysilicon of bit line; And

The corrosive agent that utilization contains HF carries out wet corrosion, so that expose field oxide, simultaneously, stays the bottom of described polysilicon layer with the polysilicon layer that forms capacitor storage node of the described bit line of formation that is positioned on the described wafer.

2, the deprocessing method of analyzing semiconductor component failure, wherein, described plasma dry corrosion utilization comprises CF at least ₄And O ₂Gas as source gas.

3, the deprocessing method of analyzing semiconductor component failure, wherein, the content of the described HF of described corrosive agent is about 49%.