JPS60148147A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a hole structure with a less occupied area in a semiconductor device by a method wherein the hole structure is made to have a contact hole, which exists in an active region having a reverse conductive type to that of the semiconductor substrate and has a depth deep enough to reach the substrate, and a metal wiring layer formed in such a way as to cover the upper part and side surface of the hole. CONSTITUTION:A contact hole 17 is shaped like a hole bored in a substrate 1 in a depth of about 1mum at this part, where the hole 17 itself is existing, for taking the potential of conductive regions 4' forming a source and the potential of the semiconductor substrate 1. An aluminum wiring layer is formed on the sidewall of the hole 17 and the regions 4' and the substrate 1 are mutually connected. However, at this time, as there is a possibility that a metal wiring 9 may be brought into a state of Schottky contact with the substrate 1 in some cases by the concentration of the P type substrate 1, it is better that a high-concentration region of P type impurities as indicated by A in the diagram has been previously formed by an ion-implantation technique, etc. As a result, the wiring 9 can be done with enough area to cover at least the hole 17 and any restriction due to the intervals between the wiring 9 and the neighboring wirings can be completely eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a contact hole for connecting active regions formed on a semiconductor substrate.

Recently, the integration of semiconductor devices has been remarkable, but on the other hand, there are several barriers to this integration. There is a structure.

The object of the present invention is to provide a contact hole structure that occupies a sufficiently small area.

This will be explained below using the drawings. FIG. 1 shows a cross section of a semiconductor device with a conventional structure. For the sake of simplicity, we will explain here the case where an N-type active region is formed on a silicon substrate having a P-type conductivity type. Conventionally, the active region is formed in the Pffli board 1 using 3T-polycrystalline silicon, which will become the gate part of the transistor. After forming the N-type portion 4 which will become the drain region by doping it with an N-group impurity such as phosphorus or AS, an oxide film which will become the interlayer film 5 is formed on the entire surface of the cable by CVD, and then drained. , drain region and wiring 8. A contact hole 6.7 is opened to take the potential between the contact hole 6.7 and the contact hole 6.7.

The conventional method for opening this hole was to soak it in hydrofluoric acid! '
Dry etching is performed using a plasma gas such as h CF 4 deep, but with recent integration, the latter dry etching is becoming mainstream. contact hole 6
．． 7 After the holes are completely opened, aluminum wiring lines 8 and 9 for applying potential to the source and drain are formed. Now, as a drawback of this similar conventional method, since two metal lines 8 and 9 are required for each valley transistor to give potential to the source and drain, the distance between the adjacent wires is smaller than the distance between the metal wires. , which prevents the multiplication of the index.

Next, the invention will be explained according to examples. The main point of the invention is that, in view of the drawbacks of the conventional method as described above, the potential of the source is taken from the substrate in order to reduce the occupied area 1fjtk of the metal arrangement. FIG. 2 shows a cross section of a semiconductor device according to the invention. In order to obtain a potential between a conductive region 4' formed in a first contact with the substrate 1, a contact hole 17 is formed at a depth of ~1 μm in the substrate at this portion. It is shaped like a moat. An aluminum wiring layer is formed on the side wall of the contact hole 17 to connect the source region 4' and the substrate 1.
Depending on the concentration of the type substrate, there is a risk of Schottky contact between the metal wiring 17 and the substrate 1, so a region with a high concentration of P-type impurity as shown in the figure may be formed using ion implantation technology. It's better.

Figures 3(a), (b), and (C) are 4' due to non-invention.
g is a sectional view according to a process flow for easily realizing metal manufacturing. As shown in the figure (a), after the thick oxide film 12 for separator isolation is completely formed in the P-type silicon substrate 11, the gate part 13 of the transistor is formed with the first polycrystalline silicon layer having tetraelectricity. After that, source and drain regions 14' and 14 are formed on the self-line by ion implantation of N-type impurities respectively.Next, after a CVD oxide film 15 is formed on the entire surface of the conductor, a first contact' is formed. 16e, a hole is opened by dry etching, and the entire second polycrystalline silicon layer 17 having tetraelectricity is formed on the entire surface of the core by CVD method, and the second polycrystalline silicon layer 17 is formed only on the drain region 14. The resist film 18 is formed in order to leave the resist film 18.
As shown in FIG. 7), polycrystalline layer 17 is etched by dry etching using InI3 as a mask. In this case, source region 14' and silicon substrate 11 are etched by ~1 μm.
It will be set up so that it will be etched. After forming the deep contact hole 20 on the source side, as described above, the high '1# degree region A is formed by doping all of the P type impurities so that the aluminum wiring and the substrate become ohmic. Then the same figure (
A thick interlayer insulation layer 19 is formed as shown in C), and contact holes are formed in 19 again to form aluminum wiring layers 21 and 22.

As mentioned above, according to the uninvented structure, the potential of one side of the transistor is supplied from the substrate, so the aluminum wiring 22
The area of the contact hole 20 is sufficient to cover at least the contact hole 20, and there can be no restriction caused by the distance between adjacent wiring lines.

The example used in the explanation above is limited to the case where an N-type transistor is formed on a P-type substrate, but there are other cases as well. -N in the well
Needless to say, the present invention can be similarly applied to type transistors, P type transistors in N type substrates, complementary type transistors, etc.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device with a conventional structure. 1...Silicon substrate, 2...Field tR conversion tm, 3...Gate electrode, 4...Source/drain region, 5...Interlayer insulation, 6. 7...
Contact hole, 8°9...Metal contact layer. FIG. 2 is a sectional view of a semiconductor device according to an embodiment V of the invention. 4'...source region, 17...contact hole, A...high concentration impurity region. FIG. 3(a), [b), and (C) are examples e of the present invention.
(j, cross-sectional view of + process. 11...silicon substrate, 12...field oxide film, 13...ge)! Pole, 14...Drain region, 14'...Source region, 15...Interlayer encapsulation film, 16, . 20...Contact hole, 17...
... Polycrystalline silicon layer, 19 ... Interlayer insulation 1
Exchange, 21, 22...metal wiring layer.

Claims (2)

[Claims] (1) - shape on a silicon semiconductor substrate having a conductivity type,
' In the manufactured semiconductor device, a contact hole exists in an active region having a conductivity type opposite to that of the substrate and has a depth reaching the substrate, and a contact hole is formed to cover the top and side surfaces of the contact hole. 1. A semiconductor device comprising a metal wiring layer. (2) The semiconductor device according to claim 1, further comprising an impurity region in the substrate surrounding the contact hole that has the same conductivity type as the substrate and has a higher concentration than the substrate.