KR100216674B1 - Deprocessing method of defect analysis of polysilicon contact - Google Patents
Deprocessing method of defect analysis of polysilicon contact Download PDFInfo
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- KR100216674B1 KR100216674B1 KR1019950019151A KR19950019151A KR100216674B1 KR 100216674 B1 KR100216674 B1 KR 100216674B1 KR 1019950019151 A KR1019950019151 A KR 1019950019151A KR 19950019151 A KR19950019151 A KR 19950019151A KR 100216674 B1 KR100216674 B1 KR 100216674B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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Abstract
본 발명은 기판에 디파인되어 있는 폴리실리콘을 통해 콘택의 크기 및 위치 등의 불량 발생 여부를 직접적으로 정확히 확인할 수 있는 개선된 디프로세싱 방법을 제공하고자 하는 것으로, 이를 위해 본 발명은 절연막을 일부 식각하여 콘택된 폴리실리콘 기둥의 상단부를 노출시키는 제1단계; 상기 노출된 폴리실리콘 기둥의 상단부를 플라즈마 식각하는 제2단계; 잔류 절연막을 습식식각하되, 후속 린스 및 건조 단계에서 잔류 폴리실리콘 기둥을 물리적으로 제거 가능하도록 장시간 동안 습식식각을 행하는 제3단계; 및 린스 및 건조를 행하므로써 순수 유입과 질소 가스 압력에 의해 상기 잔류 폴리실리콘 기둥을 제거하고 그 기둥의 저부인 얇은 폴리실리콘을 기판상의 콘택 부위에 잔류시키는 제4단계를 포함하여 이루어진다.The present invention is to provide an improved deprocessing method that can directly and accurately determine whether a defect such as the size and position of the contact through the polysilicon is finely deposited on the substrate, the present invention to partially etch the insulating film Exposing a top end of the contacted polysilicon column; Plasma etching the upper end of the exposed polysilicon pillar; A third step of wet etching the residual insulating film, and performing wet etching for a long time so as to physically remove the residual polysilicon pillar in a subsequent rinsing and drying step; And a fourth step of removing the residual polysilicon pillar by pure inflow and nitrogen gas pressure by rinsing and drying, and leaving thin polysilicon, which is the bottom of the pillar, at the contact site on the substrate.
Description
제1도는 종래방법에 따른 불량분석 상태를 나타내는 평면도.1 is a plan view showing a state of failure analysis according to the conventional method.
제2(a)도 내지 제2(d)도는 본 발명의 일실시예에 다른 불량분석을 위한 디프로세싱 과정을 나타내는 단면도.2 (a) to 2 (d) is a cross-sectional view showing a deprocessing process for failure analysis according to an embodiment of the present invention.
제3도는 본 발명에 따른 불량분석 상태를 나타내는 평면도.3 is a plan view showing a failure analysis state according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘기판 22 : 필드산화막21 silicon substrate 22 field oxide film
23 : 게이트산화막 24 : 제1폴리실리콘막23 gate oxide film 24 first polysilicon film
25 : 게이트스페이서산화막 26 : 소스/드레인접합영역25 gate oxide film 26 source / drain junction region
27 : 제1층간산화막 28 : 제2폴리실리콘막27: first interlayer oxide film 28: second polysilicon film
29 : 제2층간산화막 31 : 제3폴리실리콘막29: second interlayer oxide film 31: third polysilicon film
32 : 캐패시터의 유전막 33 : 제4폴리실리콘막32: dielectric film of capacitor 33: fourth polysilicon film
본 발명은 반도체소자 제조시 발생되는 불량을 분석하는 방법에 관한 것으로, 특히 폴리실리콘 콘택에서 발생하는 불량원인을 확인하기 위하여 이를 드러내는 디프로세싱(deprocessing) 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for analyzing defects generated during semiconductor device manufacturing, and more particularly, to a deprocessing method for revealing defects occurring in polysilicon contacts.
반도체소자의 집적도가 크게 증가하면서 제한된 면적에서 충분한 충전용량을 확보하기 위하여 각층 구조는 3차원적인 복잡한 구조로 변모되어 있다. 따라서 고집적화된 층구조에서 발생되는 불량들을 드러내기 위한 디프로세싱 기술의 고도화가 요구된다.As the degree of integration of semiconductor devices is greatly increased, each layer structure is transformed into a three-dimensional complex structure to secure sufficient charge capacity in a limited area. Thus, there is a need for advanced deprocessing techniques to reveal defects that occur in highly integrated layer structures.
종래에는 폴리실리콘 콘택의 불량발생 여부를 분석하기 위해서, 시편을 단면 제작하여 관찰하였다. 그러나 단면 관찰 방법은 시편제작 과정상 불량부위(failure site)에 정확하게 접근하기가 어렵고 분석할 수 있는 영역이 매우 국소적이라는 단점이 있다.Conventionally, in order to analyze the occurrence of defects of the polysilicon contact, the specimen was made by cross-sectional observation. However, the cross-sectional observation method has a disadvantage in that it is difficult to accurately access a failure site during the fabrication process and the area to be analyzed is very local.
또한, 층별 디프로세싱 방법이 제안되고 있는데, 이 방법은 폴리실리콘막을 제거한 후 실리콘기판에 남겨진 식각된 자국(pits)을 관찰함으로써 오픈불량 여부를 확인하는 것으로, 오픈 여부의 직접적인 관찰이 불가능하고 제1도에서 보는 바와 같이 식각과정에서 콘택 자국이 실제보다 확대되어 나타난다. 따라서 실제 콘택크기와 정렬된 위치는 확인이 어렵고 같은 불량모드에서 발생 가능한 불량메커니즘을 분석하는데 있어서도 분석과정을 연관시켜 진행시킬 수 없는 단점이 있다.In addition, a method of layered deprocessing has been proposed. This method checks open defects by removing etched pits left on the silicon substrate after removing the polysilicon film. As shown in the figure, the contact marks appear larger than they are in the etching process. Therefore, the position aligned with the actual contact size is difficult to identify and there is a disadvantage in that it is impossible to proceed with the analysis process in analyzing the failure mechanism that may occur in the same failure mode.
상기와 같이 종래기술의 문제점을 해결하기 위하여 안출된 본 발명은 기판에 디파인(define)되어 있는 폴리실리콘를 통해 콘택의 크기 및 위치 등의 불량 발생 여부를 직접적으로 정확히 확인할 수 있는 개선된 디프로세싱 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the problems of the prior art as described above is an improved deprocessing method that can directly and accurately determine whether a defect such as the size and position of the contact through the polysilicon (fine) is defined on the substrate The purpose is to provide.
상기 목적을 달성하기 위하여 본 발명은 반도체소자의 폴리실리콘 콘택에서 발생한 불량을 분석하기 위한 디프로세싱 방법에 있어서, 절연닥을 일부 식각하여 콘택된 폴리실리콘 기둥의 상단부를 노출시키는 제1단계; 상기 노출된 폴리실리콘 기둥의 상단부를 플라즈마 식각하는 제2단계, 잔류 절연막을 습식식각하되, 후속 린스 및 건조 단계에서 잔류 폴리실리콘 기둥을 물리적으로 제거 가능하도록 장시간 동안 습식식각을 행하는 제3단계; 및 린스 및 건조를 행하므로써 순수 유입과 질소 가스 압력에 의해 상기 잔류 폴리실리콘 기둥을 제거하고 그 기둥의 저부인 얇은 폴리실리콘을 기판상의 콘택 부위에 잔류시키는 제4단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a deprocessing method for analyzing a defect occurring in a polysilicon contact of a semiconductor device, the method comprising: a first step of exposing an upper end portion of a contacted polysilicon column by etching a portion of an insulating chip; Plasma etching the upper end of the exposed polysilicon pillar, wet etching the residual insulating film, and performing wet etching for a long time to physically remove the residual polysilicon pillar in a subsequent rinsing and drying step; And a fourth step of removing the residual polysilicon pillar by rinsing and drying and purging the residual polysilicon pillar by the inflow of nitrogen gas and leaving the thin polysilicon, which is the bottom of the pillar, in the contact portion on the substrate. .
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명차기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
제2(a)도 내지 제2(d)도는 본 발명의 일실시예에 따른 폴리실리콘 콘택 불량분석을 위한 디프로세싱 방범을 나타내는 공정 단면도이다.2 (a) to 2 (d) is a cross-sectional view showing the deprocessing security for the polysilicon contact failure analysis according to an embodiment of the present invention.
DRAM 셀의 폴리실리콘 콘택에서 발생한 불량부위를 드러내기 위해, 보호막과 이 중금속배선을 종래와 같은 디프로세싱 방법에 의해 제거하여, 먼저 제2(a)도에 도시된 바와 같은 단면을 형성한다. 제2(a)도에서 도면부호 21은 실리콘기판, 22는 필드 산화막, 23은 게이트산화막, 24는 게이트전극용 제1폴리실리콘막, 25는 게이트스페이서산화막, 26은 소스/드레인접합영역, 27은 제1층간산화막, 26은 비트라인용 제2 폴리실리콘막, 29는 제2층간산화막, 31은 캐패시터의 전하저장전극용 제3폴리실리콘막, 32는 캐패시터의 유전막, 33은 캐패시터의 플레이트전극용 제4폴리실리콘막을 각각 나타낸다.In order to reveal the defective portion generated in the polysilicon contact of the DRAM cell, the protective film and the heavy metal wiring are removed by a conventional deprocessing method, and first, a cross section as shown in FIG. 2 (a) is formed. In FIG. 2A, reference numeral 21 denotes a silicon substrate, 22 a field oxide film, 23 a gate oxide film, 24 a first polysilicon film for a gate electrode, 25 a gate spacer oxide film, 26 a source / drain junction region, 27 Is the first interlayer oxide film, 26 is the second polysilicon film for the bit line, 29 is the second interlayer oxide film, 31 is the third polysilicon film for the charge storage electrode of the capacitor, 32 is the dielectric film of the capacitor, 33 is the plate electrode of the capacitor The 4th polysilicon film for each is shown.
계속해서, 제2(b)도에 도시된 바와 같이 캐패시터의 윙(wing) 부분을 제거하고 제2층간산화막(29)을 식각하여 기판에 콘택된 제2 및 제3폴리실리콘막(28, 31)의 기둥 상단부가 노출되도록 한다.Subsequently, as shown in FIG. 2 (b), the second and third polysilicon films 28 and 31 contacted to the substrate by removing the wing portion of the capacitor and etching the second interlayer oxide film 29. To expose the top of the column.
다음으로, 제2(c)도에 도시된 바와 같이, 플라즈마 식각(RF 전력: 200w, CF4:40m1/sec와 조금의 O2혼합)으로 드러난 기둥 상단부의 폴리실리콘막들(28,31,33)을 식각한다.Next, as shown in FIG. 2 (c), the polysilicon films 28 and 31 at the upper end of the pillar exposed by plasma etching (RF power: 200w, CF 4 : 40m1 / sec and some O 2 mixture) are shown. Etch 33).
이후, 제2(d)도는 본 발명의 특징적 구성을 나타내는 부분으로서, 도면에 도시된 바와 같이, HF 용액을 사용하여 잔존해 있는 층간산화막들을 모두 제거하는데. 이때 층간산화막들을 장시간동안 충분하게 식각하면 린스 및 건조 과정에서 순수(DI water) 유입과 질소(N2)가스 압력에 의해 물리적으로 잔류하는 폴리실리콘막의 기둥은 제거되게 된다. 한편, 폴리실리콘 콘택을 형성하는 공정에서 폴리실리콘막이 기판 바닥에 파고들면서 증착되므로 층간산화막 식각과정에서 기판에는 폴리실리콘 기둥의 저부가 충격을 받지 않고 얇게 잔류하게 된다. 따라서 이러한 상태로 폴리실리콘 콘택의 실제 크기를 확인할 수 있다.2 (d) shows a characteristic configuration of the present invention, as shown in the figure, to remove all remaining interlayer oxide films using HF solution. At this time, if the interlayer oxide films are sufficiently etched for a long time, the pillars of the polysilicon film physically remaining by the inflow of pure water (DI water) and the nitrogen (N 2 ) gas pressure during rinsing and drying are removed. Meanwhile, in the process of forming the polysilicon contact, the polysilicon layer is deposited while digging into the bottom of the substrate, so that the bottom of the polysilicon pillar remains thin in the substrate during the interlayer oxide etching process without being impacted. In this state, therefore, the actual size of the polysilicon contact can be confirmed.
제3도는 앞서 설명한 공정으로 제작된 시편을 SEM으로 촬영한 상태의 평면도로서, 본 발명은 디프로세싱에 의해 콘택된 폴리실리콘을 제거하여 그 콘택 자국으로 콘택의 위치 및 크기를 측정하는 것이 아니고, 린스 과정에서 콘택된 폴리실리콘의 골격을 제거하고 콘택부위에 아주 얇은 폴리실리콘막을 잔류시켜, 그 디파인된 잔류 폴리실리콘막에 의해 콘택 크기 및 콘택 위치 등의 불량 여부를 분석하는 것이다. 즉, 본 발명은 제3도에 나타나듯이 종래의 제1도와 같은 문제(콘택 크기가 실제보다 확대되어 나타나는 문제)를 방지할 수 있다.3 is a plan view of a specimen produced by the above-described process in a SEM state, the present invention is not to remove the polysilicon contacted by deprocessing and to measure the position and size of the contact with the contact marks, rinse In the process, the backbone of the contacted polysilicon is removed, and a very thin polysilicon film is left in the contact portion, and the defect size and contact position are analyzed by the fine residual polysilicon film. That is, the present invention can prevent the problem as shown in FIG. 3 (the problem in which the contact size is enlarged than it is).
상기와 같이 본 발명은 기판에 디파인(define) 되어있는 폴리실리콘으로 오픈성 여부의 상태를 확인할 수 있으므로 불량분석의 정확도가 뛰어나고, 폴리실리콘 콘택의 위치 및 크기를 정확히 확인할 수 있을 뿐만 아니라 기판에서 발생하는 불량 메커니즘들의 분석도 가능한 잇점이 있다.As described above, the present invention can check the state of openness with polysilicon that is defined on the substrate, so that the accuracy of defect analysis is excellent, and the position and size of the polysilicon contact can be accurately identified as well as occurring on the substrate. Analysis of bad mechanisms is also possible.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
Claims (3)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019151A KR100216674B1 (en) | 1995-06-30 | 1995-06-30 | Deprocessing method of defect analysis of polysilicon contact |
| DE19626026A DE19626026A1 (en) | 1995-06-30 | 1996-06-28 | Reworking method for analyzing malfunction in a semiconductor device |
| TW085107886A TW318950B (en) | 1995-06-30 | 1996-06-29 | |
| CN96111009A CN1147146A (en) | 1995-06-30 | 1996-06-30 | Deprocessing method for analyzing failure in semiconductor device |
| GB9613789A GB2302987B (en) | 1995-06-30 | 1996-07-01 | Method for analyzing failure in semiconductor device |
| JP8191396A JPH0922932A (en) | 1995-06-30 | 1996-07-01 | Deprocessing method for analysis of defect of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950019151A KR100216674B1 (en) | 1995-06-30 | 1995-06-30 | Deprocessing method of defect analysis of polysilicon contact |
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| Publication Number | Publication Date |
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| KR970003748A KR970003748A (en) | 1997-01-28 |
| KR100216674B1 true KR100216674B1 (en) | 1999-09-01 |
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| KR1019950019151A KR100216674B1 (en) | 1995-06-30 | 1995-06-30 | Deprocessing method of defect analysis of polysilicon contact |
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| JP (1) | JPH0922932A (en) |
| KR (1) | KR100216674B1 (en) |
| CN (1) | CN1147146A (en) |
| DE (1) | DE19626026A1 (en) |
| GB (1) | GB2302987B (en) |
| TW (1) | TW318950B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100533387B1 (en) * | 1998-06-10 | 2006-01-27 | 매그나칩 반도체 유한회사 | Reverse process method of semiconductor device |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6033994A (en) * | 1997-05-16 | 2000-03-07 | Sony Corporation | Apparatus and method for deprocessing a multi-layer semiconductor device |
| AT409429B (en) | 1999-07-15 | 2002-08-26 | Sez Semiconduct Equip Zubehoer | METHOD FOR ETCH TREATING SEMICONDUCTOR SUBSTRATES FOR THE EXPLOSION OF A METAL LAYER |
| CN100340851C (en) * | 2003-02-18 | 2007-10-03 | 华为技术有限公司 | Miniature device and component dissection method |
| CN101769876B (en) * | 2008-12-29 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Carry out the method for failure analysis in the semiconductor device |
| CN102253325B (en) * | 2010-05-21 | 2013-07-31 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN102254844B (en) * | 2010-05-21 | 2013-06-19 | 武汉新芯集成电路制造有限公司 | Memory chip bit line failure analysis method |
| CN102565680B (en) * | 2010-12-27 | 2016-09-14 | 无锡华润上华半导体有限公司 | The failure analysis method of semiconductor device |
| CN103776668B (en) * | 2012-10-26 | 2016-03-09 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices active region failure analysis sample |
| CN105092620B (en) * | 2015-06-02 | 2018-06-26 | 武汉新芯集成电路制造有限公司 | A kind of semiconductor device failure analysis method |
| CN106876296A (en) * | 2017-01-03 | 2017-06-20 | 航天科工防御技术研究试验中心 | A kind of semiconductor device failure localization method |
| CN108037431B (en) * | 2017-11-16 | 2020-02-14 | 长江存储科技有限责任公司 | Method for calibrating bit line short-circuit defects of 3D NAND product |
| TWI738568B (en) * | 2020-11-18 | 2021-09-01 | 汎銓科技股份有限公司 | A method of preparing a semiconductor specimen for failure analysis |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4836883A (en) * | 1988-06-07 | 1989-06-06 | Advanced Micro Devices, Inc. | Method of performing electrical reject selection |
| US5214283A (en) * | 1991-07-23 | 1993-05-25 | Sgs-Thomson Microelectronics, Inc. | Method of determining the cause of open-via failures in an integrated circuit |
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1995
- 1995-06-30 KR KR1019950019151A patent/KR100216674B1/en not_active IP Right Cessation
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1996
- 1996-06-28 DE DE19626026A patent/DE19626026A1/en not_active Ceased
- 1996-06-29 TW TW085107886A patent/TW318950B/zh active
- 1996-06-30 CN CN96111009A patent/CN1147146A/en active Pending
- 1996-07-01 JP JP8191396A patent/JPH0922932A/en active Pending
- 1996-07-01 GB GB9613789A patent/GB2302987B/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100533387B1 (en) * | 1998-06-10 | 2006-01-27 | 매그나칩 반도체 유한회사 | Reverse process method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW318950B (en) | 1997-11-01 |
| GB2302987A (en) | 1997-02-05 |
| CN1147146A (en) | 1997-04-09 |
| KR970003748A (en) | 1997-01-28 |
| DE19626026A1 (en) | 1997-01-23 |
| GB9613789D0 (en) | 1996-09-04 |
| GB2302987B (en) | 1999-09-15 |
| JPH0922932A (en) | 1997-01-21 |
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