JPH01286432A - Detecting method for defects of insulating film - Google Patents

Abstract

PURPOSE:To enable exactly detecting the position of electrostatic breakdown in a plasma process and the like by applying a desired DC voltage between two electrodes, and depositing copper on an insulating film having defects. CONSTITUTION:In the sectional structure of an MOS structure applying a molybudenum layer 14 to a gate electrode, treatment is performed under an etching condition of an assumed gate electrode processing, and then a photo resist 24 is eliminated. The molybdenum layer 14 is selectively eliminated by using mixed solution of phosphoric acid, nitric acid and water. Since said mixed solution does not etch an silicon oxide film, a gate oxide film 3 is not affected by eliminating the molybdenum layer 14. Next, two electrodes 10, 12 are dipped in methyl alcohol 11 containing copper ion; a wafer 13 is set between the two electrodes 10, 12; a desired electric potential is applied between the two electrodes 10, 12. In the case where insulation of the gate oxide film 3 is lost, copper is deposited thereon. On the contrary, when insulation of the gate oxide film 3 is maintained, copper is not deposited. The copper which is deposited can be easily observed with an optical microscope.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is a method for accurately locating electrostatic damage in gate oxide films, etc., which occurs in various plasma processes, ion implantation processes, etc. used in the manufacturing process of semiconductor integrated circuits. The present invention relates to a method for detecting defects in an insulating film that can be easily and easily investigated.

(Prior Art) In the manufacture of semiconductor integrated circuits, the importance of various plasma processes such as dry etching and ion implantation processes is increasing year by year. These technologies have advantages such as a small amount of undercut (side etching) and excellent controllability of the amount of impurity introduced, so they are useful for miniaturizing semiconductor integrated circuits.

It has become a central technology driving high integration. However, since these technologies use ions, a bias voltage is applied to the insulating film in the semiconductor integrated circuit during the process, which may lead to electrostatic breakdown of the gate insulating film in some cases. be. Electrostatic breakdown of the gate insulating film causes the semiconductor integrated circuit to lose its functionality, so it is necessary to find stable manufacturing conditions that do not cause electrostatic breakdown. To this end, we need to understand the distribution of electrostatic damage within the eight planes, the dimensions and shape of gate electrodes that are likely to cause electrostatic damage, the gate electrode density, and the relationship between electrostatic damage and the arrangement of other surrounding buttons. Detailed data needs to be collected.

FIG. 6 is a cross-sectional view of a MOS transistor.

1 is a p-type silicon substrate, 2 is a thick selective oxide film (silicon oxide film) provided for isolation between elements, 3 is a gate oxide film (silicon oxide film), 4 is a polycrystalline silicon layer that acts as a gate electrode, 5 is n that acts as source and drain
“The diffusion layer, 6 is an interlayer insulating film, and 7 is a contact hole.

To specifically enumerate several examples of steps that may cause electrostatic damage to the gate electrode, they are as follows: 1) Processing of the gate electrode (dry etching of the polycrystalline silicon layer 4) 2) Formation of the n" diffusion layer 5 3) Formation of contact hole 7 in interlayer insulating film 6 (contact to polycrystalline silicon layer 4) 4) Formation of aluminum layer (electrification to gate electrode) 5) Machining of aluminum wiring (same as above), etc. In all cases, the gate insulating film 3 is covered with the polycrystalline silicon layer 4, so conventional methods for detecting defects in the insulating film are M by using the crystalline silicon layer 4 as it is
A method has been used to measure the leakage electrode between the polycrystalline silicon layer 4 and the semiconductor substrate for the OS capacitor.

(Problem to be Solved by the Invention) However, this MOS capacitor method requires a pad electrode (usually 80 μm or more) with which the probe needle comes into contact, so if there are a large number of fine bumps, the insulating film It had the disadvantage that it was not possible to evaluate the defect position.In particular, it was difficult to evaluate the defect position in RAM (Random Access Memory
) and ROM (Read Only Memory), the MOS capacitor method could hardly accurately detect the location where electrostatic damage occurred.

As a result, it is possible to understand electrostatic breakdown phenomena appropriately and quickly.
This has been a major hindrance to the process development of semiconductor integrated circuits.

The purpose of this invention is to solve the above-mentioned drawbacks.
An object of the present invention is to provide a method that can accurately detect the position of electrostatic breakdown (defects) caused by plasma processes and the like. That is, the present invention provides a method for detecting defects in an insulating film that is suitable for investigating the influence of plasma processes and the like in the actual manufacturing process of semiconductor integrated circuits.

[Means to solve the problem]

The method for detecting defects in an insulating film according to the present invention includes a step of selectively forming a metal film on an insulating film, a step of removing the metal film without damaging the insulating film, and a step of removing the metal film in a solvent containing copper ions. This semiconductor integrated circuit is held between two electrodes of
This process consists of depositing copper on a defective insulating film by applying a desired DC voltage between two electrodes.

[Effect]

In this invention, if there is a defect in the insulating film, copper is precipitated in the defective portion, so even if there are many defects, it can be reliably detected.

(Example) (Example 1) (When investigating electrostatic damage during gate electrode processing) Here, we will detect the position of electrostatic damage (of the gate oxide film) that may occur during the dry etching process for gate electrode processing. The method will be described.

First, a semiconductor integrated circuit shown in FIG. 1(a) is manufactured.

This is a cross-sectional structural diagram of a MOS structure in which the molybdenum layer 14 is used as a gate electrode. 1 is a p-type silicon substrate, 2 is a thick selective oxide film, 3 is a gate oxide film, 14 is a molybdenum layer functioning as a gate electrode, and 24 is a photoresist. The thickness of gate oxide film 3 is assumed to be 10 nm. Next, etching is performed under the assumed etching conditions for gate electrode processing, and then the photoresist 24 is removed to obtain the structure shown in FIG. 1(b). During this etching,
There is a possibility that the gate oxide film 3 directly under the molybdenum layer 14 may suffer from electrostatic breakdown, and the purpose here is to examine its insulation properties. The gate electrode material used in actual semiconductor integrated circuits is often polycrystalline silicon, but here we chose molybdenum as the gate electrode material. The electrostatic breakdown phenomenon during gate processing is not affected by this change in gate electrode material.

Next, the molybdenum layer 14 is selectively removed using a mixed solution of phosphoric acid, nitric acid, and water to obtain the structure shown in FIG. 1(C). Since this mixed solution does not etch the silicon oxide film, the gate oxide film 3 is not affected by the removal of the molybdenum layer 14 (that is, the gate oxide film defects will not increase or decrease due to the removal of the molybdenum layer 14). do not have).

Next, gate oxide film defects are evaluated using a copper deposition method. FIG. 2 is a cross-sectional structural diagram of an apparatus used for the copper deposition method. 8 is a bead made of fluororesin, 9 is a stage made of fluororesin, 10 is a lower electrode plated with gold, 11 is methyl alcohol, 12 is an upper electrode made of pure copper, 13 is a sample wafer, and 15 is a DC power supply. , 16 are wirings covered with a covering material made of fluororesin.

Two electrodes 1.0.12 are immersed in methyl alcohol 11 containing copper ions, a wafer 13 is set between these two electrodes 10.12, and a desired potential is applied between the two electrodes 10.12. . If the insulation of the gate oxide film 3 is lost, copper will be deposited in that area. Conversely, if the insulation properties of the oxide film 3 are maintained, copper will not precipitate. The deposited copper can be easily observed with an optical microscope. The detection accuracy of the position of the gate oxide film defect is 1 to 27 zm.

Even if there are many copper deposits on the wafer as shown in FIG. You can check whether this has occurred. From this observation result, it is possible to know the dimensions of the batten and the batten arrangement, which are less susceptible to electrostatic damage.

Although molybdenum was used here as the gate electrode material, it goes without saying that other materials may be used. However, when removing the gate electrode, the minimum requirement is that the gate oxide film 3 is not etched, and the ratio of the etching rate of the gate electrode to the etching rate of the gate oxide film (silicon oxide) 3 is at least 300 or more. It is necessary to be able to specifically apply the etching method. Etching speed of warped oxide and gate oxide film (silicon oxide)
Etching solutions with an etching rate ratio of at least 300 include the above-mentioned mixture of phosphoric acid, nitric acid, water, and hydrogen peroxide. ) The molybdenum layer 14 can be removed. It is for this reason that molybdenum was selected as the gate electrode in this embodiment. There is also an etching solution for aluminum that satisfies the above conditions. Polycrystalline silicon is unsuitable because there is no etching method that satisfies the above conditions.

(Example 2) (When investigating electrostatic damage during ion implantation) Here, in which region of the gate oxide film 3 is affected by electrostatic damage during the ion implantation process (formation of n+ diffusion layer 5; for source and drain) I will explain how to find out whether you are likely to receive it.

First, a semiconductor integrated circuit shown in FIG. 3(a) is manufactured.

This is a cross-sectional structural diagram of a MOS transistor using a molybdenum layer 14 as a gate electrode. 21 is an n-type silicon substrate. The thickness of the gate oxide film 3 is assumed to be fOnm. Using this molybdenum layer 14 as a mask, arsenic ions for the source and drain are implanted, and then heated to 900-1000°C.
When heat treatment is carried out, the structure shown in FIG. 3(b) is obtained. During ion implantation, there is a possibility that electrostatic breakdown may occur in the gate dielectric film 3 directly under the molybdenum layer 14, and the purpose here is to investigate its insulation properties. In actual semiconductor integrated circuits, polycrystalline silicon is often used as the material for the gate electrode, but even if molybdenum is used as the gate electrode,
There is no problem in investigating electrostatic damage during ion implantation. Next, when the molybdenum layer 14 is selectively removed using a mixed solution of phosphoric acid and nitric acid, the result shown in FIG. 3(C) is obtained. Then,
As in the previous example, gate oxide film defects are evaluated using the copper deposition method.

Even if there are many copper deposits on the wafer as shown in FIG. 3(b), it is possible to detect which part of the gate oxide film 3 is susceptible to dielectric breakdown by detecting in which part copper precipitation has occurred. You can check whether it has occurred.

[Embodiment 3] (Inspection of electrostatic breakdown during contact hole formation) Here, a method for investigating in which region dielectric breakdown has occurred in the gate oxide film 3 during the dry etching process for contact hole formation will be described.

First, the structure shown in FIG. 4(a) is manufactured. This is a cross-sectional view of the MOS structure when the glabellar insulating film 6 is formed on the molybdenum layer (gate electrode) 14. The thickness of gate oxide film 3 is 10 nm. Next, a contact hole 7 is formed in the interlayer insulating film 6 to make electrical contact with the gate electrode 14, resulting in the structure shown in FIG. 4(b). When forming the contact hole 7, there is a possibility that the gate oxide film 3 directly under the gate electrode 14 may suffer from electrostatic breakdown, and the purpose here is to examine its insulation properties. Then,
When the molybdenum layer 14 is removed using this contact hole 7, the structure shown in FIG. 4(C) is obtained. Next, as in the previous example, gate oxide film defects are evaluated using the copper deposition method.

Even if there are a large number of gates on a wafer as shown in FIG. It is possible to check whether dielectric breakdown has occurred in the oxide film 3.

(Example 4) (Investigating electrostatic breakdown during processing of aluminum wiring) Here, we will describe a method for investigating which part of the gate oxide film 3 has dielectric breakdown caused by dry etching for processing aluminum wiring. .

First, the structure shown in FIG. 5(a) is manufactured. This is a cross-sectional view after the aluminum wiring layer 18 is formed on the interlayer insulating film 6. The material of the gate electrode 14 is molybdenum, and the thickness of the gate oxide film 3 is 10 nm. Then,
When the aluminum wiring layer 18 is etched under predetermined etching conditions, the structure shown in FIG. 5(b) is obtained. During etching of the aluminum wiring layer 18, there is a possibility that the gate oxide film 3 directly under the gate electrode 14 may suffer from electrostatic breakdown, so the purpose here is to examine its insulation properties.

First, the aluminum wiring layer 18 is removed, and then the molybdenum layer 14 is removed to obtain the structure shown in FIG. 5(C). Next, as in the previous example, gate oxide film defects are evaluated using the copper deposition method.

Even if there are many bumps on the wafer as shown in FIG. It is possible to check whether dielectric breakdown has occurred in the oxide film 3.

〔Effect of the invention〕

As explained above, this invention includes a process of selectively forming a metal film on an insulating film, a process of removing this metal film without damaging the insulating film, and a process of forming two electrodes in a solvent containing copper ions. This process consists of holding this semiconductor integrated circuit between the two electrodes and depositing copper on the defective insulating film by applying a desired DC voltage between these two electrodes, so it is difficult to use any plasma process or ion implantation process. You can easily check whether a process is causing electrostatic damage to the gate oxide film, and you can also use an unprecedentedly detailed map of electrostatic damage (within the eight faces of the sea urchin).
It has the advantage of being obtained. As a result, the development speed of semiconductor integrated circuits becomes faster, and unnecessary investments in terms of time and materials can be avoided.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention assuming electrostatic damage to the gate oxide film during gate electrode processing, Fig. 2 is a block diagram of an apparatus for carrying out the copper deposition method, and Fig. 3 is an ion FIG. 4 is a process diagram showing an embodiment of the present invention assuming electrostatic breakdown of the gate oxide film during implantation, and FIG. A process diagram showing an example, FIG. 5 is a process diagram showing an embodiment of the present invention assuming electrostatic breakdown of the gate oxide film during processing of aluminum wiring, and FIG. 6 is a cross-sectional diagram showing the configuration of an MO3 transistor. It is. In the figure, 1 is a P-type silicon substrate, 2 is a thick selective oxide film (silicon oxide film) provided for isolation between elements, 3 is a gate oxide film (silicon oxide film), and 4 is polycrystalline silicon that acts as a gate electrode. 5 is an N9 diffusion layer that acts as a source and drain, 6 is an interlayer insulating film, 7 is a contact hole, 8 is a bead made of fluororesin, 9 is a stage made of fluororesin, and 1o is a gold-plated lower part. Electrode, 11 is methyl alcohol, 12 is an upper electrode made of pure copper, 13 is a sample wafer, 14 is a molybdenum layer (gate electrode), 15 is a DC power supply, 16 is a wiring, 18 is an aluminum wiring layer, 21 is n-type silicon The substrate 24 is a photoresist. Section 2 - 10QV Fig. 3/-1 N type silicon fallout Fig. 4 Fig. 1 Nintakutohonomu Fig. 5 18 Aluminum distribution band J- 1 only Fig. 6 Fig. 4, multi-layer silicon 1

Claims (1)

[Claims] In a method for detecting defects in an insulating film of a semiconductor integrated circuit,
A step of selectively forming a metal film on the insulating film, a step of removing the metal film without damaging the insulating film, and a step of placing the semiconductor integrated circuit between two electrodes in a solvent containing copper ions. A method for detecting defects in an insulating film, comprising the step of depositing copper on the defective insulating film by holding the insulating film and applying a desired DC voltage between the two electrodes.