JP2000164490A - Electron beam drawing device and manufacture of semiconductor device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electron beam drawing device for drastically reducing the setting error of the amount of dosage of electron beams and for improving the setting accuracy of electron beams, and a method for manufacturing a semiconductor device. SOLUTION: In an electron beam-drawing device, a first forming aperture AP1 where an electron beam 2 emitted from an electron beam source 1 is applied is installed at the lower portion of the electron beam source 1, a forming polarizer 3 is installed at the lower portion of the first forming aperture AP1, and a second forming aperture AP2 is installed at the lower portion of the forming polarizer 3. In the electron beam drawing device, a plurality of cell patterns are formed at the second forming aperture AP2, one side of the cell patterns is smaller than one side of cell pattern of the first forming aperture AP1, and the opening of the cell pattern of the second forming aperture AP2 cannot be changed by the first forming aperture AP1 and the forming polarizer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron beam lithography apparatus and a method for manufacturing a semiconductor device using the same, and more particularly, it is possible to drastically reduce the setting error of the dose of an electron beam and improve the setting accuracy of the electron beam. The present invention relates to an electron beam writing apparatus and a method for manufacturing a semiconductor device using the same.

[0002]

2. Description of the Related Art The present inventors have studied an electron beam writing apparatus used in a method of manufacturing a semiconductor device. The following is a technique studied by the present inventors, and the outline is as follows.

That is, in an exposure method of an electron beam lithography apparatus used in a method of manufacturing a semiconductor device, a resist film applied on a wafer is subjected to an LSI (Large Scale Integrated Circuit) using an electron beam lithography apparatus.
The step of exposing the pattern as in t) is used.

In this case, in order to draw a pattern on an LSI or the like with good reproducibility by using an electron beam drawing apparatus on a resist film applied on a wafer, an electron beam calibrated by accurate beam current measurement is used. It is necessary to use a dose.

[0005] The beam current measurement is performed by using two shaping apertures (a first shaping aperture AP1 and a second shaping aperture AP) provided in the electron beam writing apparatus.
An operation of automatically cutting 2) by a shaping deflector to form a variable shaping beam is performed.

Further, in the prior art, the first shaping aperture AP1 is a shaping aperture which can move the opening of the cell pattern of the first shaping aperture AP1 under the second shaping aperture AP2. The opening of the cell pattern of the second shaping aperture AP2 can be made variable using the first shaping aperture AP1 and the shaping deflector. When performing beam current measurement, the second shaping aperture AP2 is used. The opening of the cell pattern is made variable so that the variable shaped cell pattern is 2.5 μm × 2.5 μm
Square cell pattern.

A document describing an electron beam writing apparatus is, for example, December 13, 1988.
There are those described in “Electronic Materials, December 1988, Separate Volume”, p.

[0008]

However, according to the embodiment in which the opening of the cell pattern of the second shaping aperture AP2 can be varied by using the above-described first shaping aperture AP1, the beam current is measured. It has been clarified that there is a potential problem that a dimensional error easily occurs in a variable shaped beam due to contamination of a standard mark used for calibration of the beam size itself, or contamination of a shaping deflector for controlling cutting.

As a result, at present, the beam current value is affected because the cutting dimension of the forming aperture is delicately changed by the standard mark or the contamination of the forming deflector. Therefore, when the beam current value fluctuates by about ± 1%, the setting error of the dose amount of the electron beam increases, and the setting accuracy of the electron beam is extremely reduced. .

An object of the present invention is to provide an electron beam drawing apparatus capable of drastically reducing the setting error of the electron beam dose and improving the setting accuracy of the electron beam, and a method of manufacturing a semiconductor device using the same. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, (1). In the electron beam writing apparatus according to the present invention, the first shaping aperture to be irradiated with the electron beam emitted from the electron beam source is provided below the electron beam source, and the shaping deflection is formed below the first shaping aperture. An electron beam lithography apparatus in which a device is installed, and a second shaping aperture is installed below the shaping deflector, wherein a plurality of cell patterns are formed in the second shaping aperture. One side of the cell pattern is the first
The distance is smaller than one side of the cell pattern of the shaping aperture, and the opening of the cell pattern of the second shaping aperture is not changed by the first shaping aperture and the shaping deflector.

(2). The exposure method of the electron beam writing apparatus according to the present invention includes a step of exposing a resist film applied on the surface of a wafer using the electron beam writing apparatus according to the above (1).

(3). The method of manufacturing a semiconductor device according to the present invention includes a step of forming a pattern of the semiconductor device by using a lithography technique using the exposure method of the electron beam writing apparatus described in (2).

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) FIG. 1 is a schematic configuration diagram showing an electron beam writing apparatus according to Embodiment 1 of the present invention. FIG. 2 is a schematic plan view showing, on an enlarged scale, a first shaping aperture provided in the electron beam writing apparatus shown in FIG. FIG. 3 is a schematic plan view showing, on an enlarged scale, a second shaping aperture provided in the electron beam writing apparatus shown in FIG.

As shown in FIGS. 1 to 3, the electron beam writing apparatus according to the present embodiment has a first electron beam (irradiation beam) 2 irradiated from an electron beam source (electron gun) 1. Is formed below the electron beam source 1, a shaping deflector 3 is installed below the first shaping aperture AP1, and a second shaping aperture AP2 is formed below the shaping deflector 3. is set up.

The first shaping aperture AP1 is a shaping aperture having a cell pattern (opening) AP1A. In this case, the cell pattern AP1A is a square, and is a square (150 μm × 150 μm) cell pattern in which one side of the square is 150 μm.

The second shaping aperture AP2 is mounted on an aperture stage 4 capable of moving the X shaping, Y-direction or rotation with respect to the second shaping aperture AP2.

A plurality of cell patterns AP2A to AP2F are formed in the second shaping aperture AP2, and one side of the cell patterns AP2A to AP2F is smaller than one side of the cell pattern AP1A of the first shaping aperture AP1. The distance is such that the openings of the cell patterns AP2A to AP2F of the second shaping aperture AP2 are not transformed by the first shaping aperture AP1 and the shaping deflector 3. Further, the plurality of cell patterns AP2A to AP2F in the second shaping aperture AP2 are collective cell patterns, and are formed of fixed shape patterns, so that the first shaping aperture A
The cell patterns AP2A to AP2F do not require the cutting operation of the two forming apertures composed of P1 and the second forming aperture AP2. in this case,
The second shaping aperture AP2 is a feature of the electron beam writing apparatus of the present embodiment.

As a result of the study by the present inventor, one side of each of the cell patterns AP2A to AP2F in the second shaping aperture AP2 has a distance of 10% or less of one side of the cell pattern AP1A of the first shaping aperture AP1. Have been.

The plurality of cell patterns AP2A to AP2F in the second shaping aperture AP2 include a square cell pattern AP2A and a rectangular cell pattern AP2B as rectangular (quadrangle) cell patterns. In this case, the square cell pattern A
One side of P2A is 125 μm, and one side of the cell pattern AP1A of the first shaping aperture AP1 is 150 μm.
, The first forming aperture AP1
From one side (150 μm) of the cell pattern AP1A of FIG.
% Is defined as one side of the distance.

Further, the second shaping aperture AP2 is provided with a cell pattern AP2C, a cell pattern AP2D, a cell pattern AP2E, and a cell pattern AP2F according to the design specification.

Furthermore, the second forming aperture AP2
Can apply a second shaping aperture AP2 provided with a rhombic, trapezoidal or round cell pattern depending on the design specifications. In this case, since the second shaping aperture AP2 of the present embodiment can have any shape as the collective cell pattern, if the current density can be calculated according to the design specifications, a diamond, trapezoid, or circle It has been clarified as a result of the study of the present inventor that a cell pattern having a shape can be provided.

The electron beam writing apparatus according to the present embodiment has an objective lens 5 below the second shaping aperture AP2.
And an electron optical system including a deflector 6 and the like. A wafer stage (sample stage) 7 is provided below the electron optical system.

The wafer stage 7 is a stage on which a wafer 8 as a sample (a wafer 8 such as a mode in which a resist film 8a is coated on the surface of the wafer 8) is set.
However, the wafer stage 7 of the present embodiment is provided with a Faraday cup 9 having a function of measuring the beam current of the electron beam 2 on the surface of the wafer stage 7. Further, a power supply 9a is electrically connected to the Faraday cup 9, and a measuring instrument 10 having a function of measuring a beam current or the like is electrically connected to the Faraday cup 9.

In the electron beam lithography apparatus according to the present embodiment, the structural elements and structures of the electron beam lithography apparatus other than the second shaping aperture AP2 are not limited to those described above. Components and structures can be applied.

The exposure method of the electron beam lithography system of the present embodiment uses the above-described electron beam lithography system having the second shaping aperture AP2 to remove the resist film 8a applied to the surface of the wafer 8 using the electron beam lithography system. It has an exposure step.

The method of manufacturing a semiconductor device according to the present embodiment includes a step of forming a pattern of the semiconductor device by using a lithography technique using an exposure method of an electron beam drawing apparatus.

According to the above-described electron beam writing apparatus of the present embodiment, the first shaping aperture AP1 is installed below the electron beam source 1, and the first shaping aperture A
A shaping deflector 3 is installed below P1, and a second shaping aperture AP2 is installed below the shaping deflector 3. The second shaping aperture AP2 includes a plurality of cell patterns AP2A. To AP2F, and one side of each of the cell patterns AP2A to AP2F is smaller than one side of the cell pattern AP1A of the first shaping aperture AP1 (in particular, the second shaping aperture AP).
2, one side of each of the cell patterns AP2A to AP2F is the first formed aperture A
P1 is a distance of 10% or less of one side of the cell pattern AP1A), and the openings of the cell patterns AP2A to AP2F of the second shaping aperture AP2 are transformed by the first shaping aperture AP1 and the shaping deflector 3. That is not done.

Further, the plurality of cell patterns AP2A to AP2F in the second shaping aperture AP2 are collective cell patterns, and are formed of fixed shape patterns, so that the first shaping aperture AP2 is formed.
The cell patterns AP2A to AP2F do not require a cutting operation of two forming apertures including the first and second forming apertures AP2. In this case, the second shaping aperture AP2 is a feature of the electron beam writing apparatus of the present embodiment.

Therefore, according to the electron beam lithography apparatus of the present embodiment, the cell pattern in a mode that does not require the cutting operation of the two shaping apertures consisting of the first shaping aperture AP1 and the second shaping aperture AP2. AP
By setting 2A to AP2F, the switching error between the two shaping apertures can be eliminated, and the fluctuation of the measured beam current value can be made extremely small, so that the beam current can be secured according to the design specifications.

As a result, according to the electron beam writing apparatus of the present embodiment, the setting error of the dose amount of the electron beam 2 can be drastically reduced, and the setting accuracy of the electron beam 2 can be improved. it can.

According to the exposure method of the electron beam lithography system of the present embodiment, the resist film applied to the surface of the wafer 8 by using the electron beam lithography system having the above-mentioned second shaping aperture AP2. By having the step of exposing 8a, the setting error of the dose can be drastically reduced, and the controllability of the dimensional accuracy within the wafer 8 and between the wafers 8 can be improved.

According to the method of manufacturing a semiconductor device of the present embodiment, the method includes a step of forming a pattern of a semiconductor device by using a lithography technique using the above-described exposure method of an electron beam writing apparatus. As a result, the dose setting accuracy can be improved, and the beam current fluctuation rate can be reduced as the pattern becomes finer, so that a high-performance and highly reliable pattern can be formed even when the pattern of the semiconductor device is fine. it can.

Therefore, according to the method of manufacturing a semiconductor device of the present embodiment, the present invention can be applied to a method of manufacturing a semiconductor integrated circuit device having a fine pattern of a semiconductor device and having a pattern requiring fine processing. And fine processing can be performed, and the production yield can be increased.

(Embodiment 2) FIGS. 4 and 6 to 12
FIG. 7 is a schematic sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention; FIG. 5 is a schematic plan view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention. In this case, FIG. 6 is a schematic cross-sectional view showing a cross section taken along line AA of FIG. The method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG.

The method of manufacturing a semiconductor device according to the present embodiment
MOSFET (Metal Oxide Semiconductor Field Effe
ct transistor).

First, for example, a CVD (Chemic)
After a thin silicon oxide film 12 is formed by using an Al Vapor Deposition method or a thermal oxidation method, a silicon nitride film 13 is formed on the silicon oxide film 12 by using a CVD method. Next, a resist film 14 is applied on the semiconductor substrate 11 (FIG. 4).

Thereafter, an exposed portion 14a is formed in the resist film 14 by using the lithography technique using the exposure method of the electron beam writing apparatus according to the first embodiment (FIG. 5).
And FIG. 6).

Accordingly, by applying the above-described exposure method of the electron beam lithography apparatus of the first embodiment to the lithography technique, the dose setting accuracy at the time of writing becomes high, and the pattern formation accuracy can be made extremely high. Therefore, the production yield can be increased, and the processing capability can be improved.

Next, the resist film in the region of the exposed portion 14a of the resist film 14 is removed using a lithography technique, and an opening is formed in the region (FIG. 7).

Thereafter, using the resist film 14 as an etching mask, the silicon nitride film 13 below the opening formed in the resist film 14 is removed by etching, and then the silicon oxide film 12 thereunder is removed. Work to remove by etching (FIG. 8).

Next, after the unnecessary resist film 14 is removed, the semiconductor substrate 11 below the opening is etched using the silicon nitride film 13 as an etching mask to form an element isolation insulating film. A groove (trench groove) 15 is formed as a region to be formed (FIG. 9).

After that, a silicon oxide film 16 is formed on the semiconductor substrate 11 by using the CVD method, and the trench 15 is filled with the silicon oxide film 16.
Using a polishing technique such as an emical mechanical polishing (chemical mechanical polishing) method, the silicon oxide film 16
The underlying silicon nitride film 13 and the underlying silicon oxide film 12 are removed, and the surfaces of the silicon oxide film (element isolation insulating film) 16 and the semiconductor substrate 11 buried in the trench 15 are planarized ( (FIG. 10).

According to this manufacturing process, an element isolation insulating film made of the silicon oxide film 16 embedded in the trench 15 can be formed in a selective region of the semiconductor substrate 11, and the planarized semiconductor substrate 11 can be formed. A silicon oxide film 16 as an isolation insulating film having the same plane as the surface of the semiconductor substrate 11 can be formed in the region.

In addition to the element isolation insulating film consisting of the silicon oxide film 16 buried in the trench 15, the above-described manufacturing process of the silicon oxide film 16 is used to form a cross-sectional shape on the semiconductor substrate 11. After forming a rectangular shallow groove, a silicon oxide film 16 is buried in the groove, and a silicon oxide film as a device isolation insulating film in various modes composed of a silicon oxide film or the like projecting more than the surface of the semiconductor substrate 11. A film 16 can be formed.

Next, in the element formation region of the semiconductor substrate 11,
For example, a MOSFET is formed (FIG. 11). in this case,
After a gate insulating film 17 made of, for example, a silicon oxide film is formed on a semiconductor substrate 11, a gate electrode 1 is formed thereon.
After forming a polycrystalline silicon film containing, for example, phosphorus as an impurity, and forming an insulating film 19 made of, for example, a silicon oxide film thereon, the gate electrode is formed by using a lithography technique and a selective etching technique. And the like.

Next, after a silicon oxide film is formed on the semiconductor substrate 11 by using the CVD method, the gate electrode 1 is formed by using the lithography technique and the selective etching technique.
Sidewall spacers (sidewall insulating films) 20 on the side walls 8
To form Next, using a gate region including the gate electrode 18 and the like as a mask, an ion implantation method is used to ion-implant an n-type impurity such as phosphorus into the semiconductor substrate 11 and then perform a thermal diffusion process to perform source and drain Is formed.

After that, a silicon oxide film 22 is formed on the semiconductor substrate 11 by using the CVD method, and then, if necessary, the surface of the silicon oxide film is formed by using a polishing technique such as a CMP method. The film 22 is removed, and a flattened silicon oxide film 22 is formed.

Next, after a through hole (connection hole) is formed in the silicon oxide film 22, for example, tungsten or the like is buried in the through hole by using a selective CVD method to form a plug 23. After a wiring layer made of aluminum or the like is formed using a sputtering method or the like, a patterned wiring layer 24 is formed using a lithography technique and a selective etching technique (FIG. 11). In this case, as another embodiment, the plug 23 is a plug 23 made of the same material as the wiring layer 24, and the plug 23 and the wiring layer 24 are formed by the same manufacturing process as the wiring layer 24. It can be taken as an embodiment.

Thereafter, a silicon oxide film 25 as an interlayer insulating film is formed on the semiconductor substrate 11 by using a CVD method, and if necessary, a surface layer is formed by using a polishing technique such as a CMP method. The silicon oxide film 25 in the portion is removed, and a flattened silicon oxide film 25 is formed.

Then, after a through hole is formed in the silicon oxide film 25, a wiring layer made of, for example, aluminum is formed by using a sputtering method or the like, and then patterned by using a lithography technique and a selective etching technique. The formed wiring layer 26 is formed (FIG. 12).

Next, if necessary, after forming a multilayer wiring layer, a passivation film is formed, thereby completing the semiconductor device manufacturing process.

When forming an etching mask made of a resist film in a lithography technique for forming a pattern of the above-described wiring layer 26 and the like, the electron beam lithography of the first embodiment described above is performed in accordance with design specifications. The exposure method of the apparatus can be applied.

According to the method of manufacturing a semiconductor device of the present embodiment, the lithography technique using the exposure method of the electron beam lithography apparatus of the first embodiment is used.
By forming the exposed portions 14a in the resist film 14, the dose setting accuracy at the time of writing becomes high, and the pattern forming accuracy can be made extremely high, so that the manufacturing yield can be increased and the processing capability can be improved. Can be.

According to the method of manufacturing a semiconductor device of the present embodiment, the lithography technique using the exposure method of the electron beam lithography apparatus of the first embodiment is used.
Since the pattern of the semiconductor device is formed, the dose setting accuracy can be improved, and the beam current fluctuation rate can be reduced as the pattern becomes finer. In addition, since the semiconductor device can be formed as a highly reliable pattern, a high performance and highly reliable semiconductor device such as a semiconductor integrated circuit device can be manufactured with a high manufacturing yield.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, the method of manufacturing a semiconductor device according to the present invention employs a lithography technique for exposing a resist film using the above-described exposure method of the electron beam lithography apparatus of the first embodiment. A variety of patterns can be formed by using a selective etching technique in which a resist film is formed and the resist film is used as an etching mask.

The method of manufacturing a semiconductor device according to the present invention
A semiconductor substrate on which a semiconductor element is formed is formed using SOI (Silicon on
Insulator) Substrates such as substrates can be used, and a method for manufacturing a semiconductor device such as a semiconductor integrated circuit device in which various semiconductor elements such as MOSFETs, CMOSFETs, and bipolar transistors are combined on those substrates. it can.

Further, the method of manufacturing a semiconductor device according to the present invention comprises a MOSFET, a CMOSFET, a BiCMOSFE.
DRAM (Dynamic Random Acc.)
ess Memory), SRAM (Static Random Access Memor)
The present invention can be applied to a method of manufacturing a semiconductor device such as various semiconductor integrated circuit devices having a memory system such as y) or a logic system.

[0063]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the electron beam writing apparatus of the present invention, the cell pattern in the second shaping aperture is
Since the cell pattern is formed in a mode that does not require the cutting operation of the two forming apertures including the first forming aperture and the second forming aperture, the cutting error of the two forming apertures can be eliminated, and the beam Since the fluctuation of the measured current value can be made extremely small, it is possible to secure the beam current according to the design specifications.

As a result, according to the electron beam writing apparatus of the present invention, the setting error of the dose of the electron beam can be drastically reduced, and the electron beam writing apparatus can improve the setting accuracy of the electron beam.

(2). According to the exposure method of the electron beam lithography apparatus of the present invention, there is provided a step of exposing a resist film applied to a surface of a wafer using the electron beam lithography apparatus having the above-described second shaping aperture. Thus, the setting error of the dose can be drastically reduced, and the controllability of the dimensional accuracy within the wafer and between the wafers can be improved.

(3). According to the method of manufacturing a semiconductor device of the present invention, the method includes a step of forming a pattern of a semiconductor device by using a lithography technique using the above-described exposure method of an electron beam lithography apparatus. Since the setting accuracy can be improved and the beam current fluctuation rate can be reduced as the pattern becomes finer, a high-performance and highly reliable pattern can be formed even if the pattern of the semiconductor device is fine.

Therefore, according to the method of manufacturing a semiconductor device of the present invention, the method can be applied to a method of manufacturing a semiconductor integrated circuit device having a fine pattern of a semiconductor device and having a pattern requiring fine processing. In addition, fine processing can be performed, and the production yield can be increased.

(4). According to the method of manufacturing a semiconductor device of the present invention, the lithography technique using the above-described exposure method of the electron beam lithography apparatus of the present invention is used to form an exposed portion in the resist film. Since the dose setting accuracy is increased and the pattern formation accuracy can be extremely increased, the manufacturing yield can be increased, and the processing capability can be improved.

(5). According to the method for manufacturing a semiconductor device of the present invention, the pattern of the semiconductor device is formed by using the lithography technique using the above-described exposure method of the electron beam drawing apparatus of the present invention. Since the precision can be improved and the beam current fluctuation rate can be reduced as the fine processing pattern becomes smaller, the pattern of the semiconductor integrated circuit device requiring the fine processing can be formed as a high-performance and high-reliability pattern. A semiconductor device including a highly reliable semiconductor integrated circuit device or the like can be manufactured with a high manufacturing yield.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating an electron beam writing apparatus according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing, on an enlarged scale, a first shaping aperture provided in the electron beam writing apparatus shown in FIG.

FIG. 3 is an enlarged schematic plan view showing a second shaping aperture provided in the electron beam writing apparatus shown in FIG. 1;

FIG. 4 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 5 is a schematic plan view illustrating a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 6 is a schematic sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 7 is a schematic sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 8 is a schematic sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 9 is a schematic sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 10 is a schematic sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 11 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 12 is a schematic sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

DESCRIPTION OF SYMBOLS 1 Electron beam source 2 Electron beam 3 Shaping deflector 4 Aperture stage 5 Objective lens 6 Deflector 7 Wafer stage 8 Wafer 8a Resist film 9 Faraday cup 9a Power supply 10 Measuring device 11 Semiconductor substrate (wafer) 12 Silicon oxide film 13 Silicon nitride film 14 Resist film 14a Exposure portion 15 Groove 16 Silicon oxide film (insulating film for element isolation) 17 Gate insulating film 18 Gate electrode 19 Insulating film 20 Side wall spacer 21 Semiconductor region 22 Silicon oxide film (insulating film) ) 23 plug 24 wiring layer 25 silicon oxide film (interlayer insulating film) 26 wiring layer AP1 first forming aperture AP1A cell pattern in first forming aperture AP1 second forming aperture AP2A to AP2F to second forming aperture AP2 Kicking the cell pattern

Claims (9)

[Claims] 1. A first shaping aperture to be irradiated with an electron beam emitted from an electron beam source is provided below the electron beam source, and a shaping deflector is provided below the first shaping aperture. An electron beam writing apparatus, wherein a second shaping aperture is installed below the shaping deflector, wherein a plurality of cell patterns are formed in the second shaping aperture. One side of the cell pattern is a distance smaller than one side of the cell pattern of the first shaping aperture, and the opening of the cell pattern of the second shaping aperture is transformed by the first shaping aperture and the shaping deflector. An electron beam writing apparatus characterized by not being performed. 2. The electron beam writing apparatus according to claim 1, wherein one side of the cell pattern in the second shaping aperture is a distance of 10% or less of one side of the cell pattern of the first shaping aperture. An electron beam lithography apparatus, comprising: 3. The electron beam writing apparatus according to claim 1, wherein a rectangular cell pattern is provided in the plurality of cell patterns in the second shaping aperture. apparatus. 4. The electron beam lithography apparatus according to claim 3, wherein the rectangular cell pattern is provided with a square cell pattern. 5. The electron beam writing apparatus according to claim 4, wherein one side of said square cell pattern is 125 μm.
Wherein the one side of the cell pattern of the first shaping aperture is 150 μm. 6. The electron beam writing apparatus according to claim 1, wherein the plurality of cell patterns in the second shaping aperture include a diamond-shaped, trapezoidal, or round cell pattern. Electron beam drawing equipment. 7. An electron beam writing apparatus characterized in that an electron beam current is measured using a collective cell beam without using a variable shaped beam. 8. The electron beam writing apparatus according to claim 7, wherein a dose amount at the time of exposure is determined based on an electron beam current measurement. 9. A method for manufacturing a semiconductor device, comprising the step of forming a pattern of a semiconductor device using the electron beam writing apparatus according to claim 1.