JPH1197326A - Electron beam exposure method and manufacture of semiconductor device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electron beam exposure method by which high-accuracy exposure can be performed and a method for manufacturing a semiconductor device using the method. SOLUTION: When exposure is performed correspondingly to the positions and shapes of chips C1 -Cn on a wafer 2 by detecting the positions of alignment marks M1a -M1d arranged at the corners of a plurality of arbitrary chips Cm1 -Cml on the wafer 2, a function containing such a term of second degree as the XX, XY, or YY of the X-Y coordinate system of the chips on the wafer 2 is used as the function used for the alignment of the chips on the wafer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method for an electron beam exposure (drawing) apparatus and a method for manufacturing a semiconductor device using the same, and more particularly, to an electron beam exposure method capable of performing high-precision exposure. And a method of manufacturing a semiconductor integrated circuit device using the same.

[0002]

2. Description of the Related Art The present inventors have studied an electron beam (electron beam) exposure apparatus used in a method of manufacturing a semiconductor integrated circuit device. The following is a technique studied by the present inventors, and the outline is as follows.

That is, LSI (Large Scale Integrat)
In a manufacturing process of a semiconductor integrated circuit device such as an ed circuit, a lithography technique using an electron beam exposure method and a selective etching technique are used to form a wafer made of a semiconductor substrate or the like (a wafer on which a plurality of chips are arranged). ) Are formed with patterns such as through holes.

In this case, when performing exposure using an electron beam exposure apparatus, the shape of a chip as a semiconductor element formation region is measured, and exposure is performed in accordance with the position and shape. By detecting the positions of the alignment marks provided at the four corners of a plurality of chips selected as necessary on the wafer, the coefficients of the gain, rotation, shift, etc. for the chips can be calculated for all the chips. Global adjustment is performed by calculating the same coefficient as a function of the position coordinates of each chip.

An electron beam exposure apparatus (electron beam drawing apparatus)
Are described in, for example, 1988
December 13, 1998, "Electronic Materials 1988"
December 2004, separate volumes, p.84-p89.

[0006]

However, the electron beam is
When an electric field exists near the wafer surface,
There is a problem that the irradiation trajectory is bent and an error occurs in the detection position of the alignment mark.

In this case, especially when the wafer itself is charged, the following problems occur.

Since the electron beam is incident on the wafer almost perpendicularly, even if the wafer has an electric field, the electric field is uniform inside the wafer so that the irradiation trajectory of the electron beam cannot be bent. Since the periphery is surrounded by grounded metal, the outer edge of the wafer has a problem that the irradiation trajectory is bent due to a change in the electric field.

As a result, at the outer edge of the wafer, a chip is erroneously detected as being large or small. As a result of the study by the present inventors, it has been found that this error occurs two-dimensionally from the center of the wafer to the outside. Therefore, according to the above-described alignment method, since an error that changes two-dimensionally from the center of the wafer toward the outside is not taken into account, the error affects each chip, and the alignment accuracy is degraded. Problem has occurred.

An object of the present invention is to provide an electron beam exposure method capable of performing highly accurate exposure and a method of manufacturing a semiconductor device using the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the electron beam exposure method according to the present invention, alignment marks are arranged at the corners of a plurality of chips on a wafer, and the positions of the alignment marks are detected to correspond to the positions and shapes of the chips on the wafer. When performing the exposure, the X-coordinate of the coordinate system of the chip on the wafer is used as a function used for alignment of the chip on the wafer.
And XX of XY or XY or YY
A function containing the following term is used.

Further, a method of manufacturing a semiconductor device according to the present invention
A manufacturing process for forming a pattern of a semiconductor device such as a semiconductor integrated circuit device by using a lithography technique and a selective etching technique using the electron beam exposure method.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) FIG. 1 is a schematic configuration diagram showing an electron beam exposure apparatus used in an electron beam exposure method according to Embodiment 1 of the present invention.

FIG. 2 is a schematic plan view showing a wafer used in the electron beam exposure method according to the first embodiment of the present invention.

In the electron beam exposure apparatus used in the electron beam exposure method according to the first embodiment,
A wafer 2 for manufacturing a semiconductor integrated circuit device is set. In this case, the sample table 1 has a function such as an XY table function movable in a horizontal plane, and a resist film is applied on the surface of the wafer 2.

The wafer 2 includes a plurality of chips C ₁ , C ₂ ,
C ₃ ,..., C _n are arranged, and alignment marks are provided at the four corners of an arbitrary plurality of chips.

A plurality of chips C ₁ , C ₂ , C ₃ ,.
Among the C _n , a plurality of chips (arbitrarily selected chips) to be measured when performing the overlay exposure operation are represented by C
_{m1, C m2, C m3,} ···, shown as C _ml. In this case, the alignment marks provided at the four corners of the chip C _m1 are shown as M _1a , M _1b , M _1c , and M _1d . Also shows the alignment marks are provided at four corners of the chip _{C m2 M 2a, M 2b,} M 2c, as M _2d. Also,
The alignment marks provided at the four corners of the chip C _ml are shown as M _la , M _lb , M _lc , and M _ld . As another embodiment, the alignment marks provided at the four corners of the chip include a plurality of chips C ₁ , C ₂ , C ₃ ,.
Among the _n , only the plurality of chips C _m1 , C _m2 , C _m3 ,..., C _ml to be measured at the time of performing the superposing exposure operation are provided only in C _ml. A mode in which chips in various regions of the chips are selected and set can be applied.

On the other hand, an electron beam source 3 is provided above the sample stage 1, and the wafer 2 set on the sample stage 1
Is configured to radiate an electron beam 4 to the electron beam.

Between the electron beam source 3 and the sample table 1, there is provided an electron optical system comprising a molding unit 5, an objective lens 6, a deflector 7, and the like. In this case, the electron beam source 3
After the photoelectron surface is shaped into a predetermined shape by the shaping device 5, the electron beam 4 emitted from the wafer 2 is focused on the surface of the wafer 2 by the objective lens 6, and deflected by the deflector 7. Is irradiated to the position.

The molding device 5 is electrically connected to a calculation unit 10 via a molding device control unit 8 and a molding signal generation unit 9. Further, the objective lens 6 is electrically connected to the calculation unit 10 via the lens control unit 11 and the position signal generation unit 12. The deflector 7 is electrically connected to the calculation unit 10 via the deflector control unit 13 and the position signal generation unit 12.

The arithmetic unit 10 is electrically connected to the control computer 15 via a buffer memory 14 capable of high-speed acceleration, and is also directly electrically connected to the control computer.

The control computer 15 is electrically connected to an exposure data storage section 16 composed of, for example, a large-capacity magnetic disk and storing a plurality of graphic data to be exposed on the wafer 2. In this case, the control computer 15 can transfer predetermined exposure data appropriately selected to the buffer memory 14 as needed.

The control computer 15 is electrically connected to a mark position detector 17 disposed near the wafer 2 set on the sample table 1. The sample stage 1 is electrically connected to the control computer 15 via a sample stage controller 18. Therefore, it is possible to control the positioning of an arbitrary exposure area of the wafer 2 below the electron optical system.

Next, an electron beam exposure method according to this embodiment will be described.

[0028] First, prior to exposure using an electron beam exposure apparatus, the control computer 15, each of the chips C ₁ of the wafer _{2, C 2, C 3,} ···, graphic data to be exposed to each of the C _n And alignment marks M _1a , M _1b , M _1c , M _1d , M
_2a , M _2b , M _2c , M _2d , ..., M _la , M _lb , M _lc , M
Scan data for scanning the electron beam 4 on the _ld is read from the exposure data storage unit 16 and stored in the buffer memory 14.

Next, the control computer 15 determines a correction coefficient for superimposition on each of the chips C ₁ , C ₂ , C ₃ ,..., C _n on the wafer 2. The operation is performed as described below.

The control computer 15 moves the sample stage 1 via the sample stage controller 18 and sequentially aligns the alignment marks M _1a , M _1a ,
M _1b , M _1c , M _1d , M _2a , M _2b , M _2c , M _2d , ...,
Position M _la , M _lb , M _lc , and M _ld below the electron optics. Also, the alignment mark M in the buffer memory 14
_1a , M _1b , M _1c , M _1d , M _2a , M _2b , M _2c , M _2d ,.
_.. , M _la , M _lb , M _lc , and M _ld , using the scanning data for scanning the electron beam 4, the deflector 7 via the calculation unit 10, the position signal generation unit 12, and the deflector control unit 13. To control the electron beam 4 to align the alignment marks M _1a , M _1b , M _1c ,
M _1d , M _2a , M _2b , M _2c , M _2d , ..., M _la , M _lb ,
The backscattered electrons 19 obtained by scanning over each of M _lc and M _ld
Are received by the mark position detecting section 17, and the alignment marks _M1a , _M1b , _M1c , _M1d , _M2a , _M2b , _M2c , _M2d,.
... obtain _{M la, M lb, M lc} , the detected coordinates of each M _ld.

In this case, the detected coordinates of the alignment mark M _1a are (X _m1a , Y _m1a ), and X _{m1a with} respect to the origin coordinates where the coordinates of the center of the chip C _m1 are (0, 0) is X direction. Y _m1a is a coordinate in the Y direction, and indicates a coordinate in the chip. The detected coordinates of the following alignment marks M _1b and the like are also displayed in the same manner as the detected coordinates (X _m1a , Y _m1a ) of the alignment marks M _1a .
That is, the detected coordinates of the alignment mark M _1b are (X _m1b , Y _m1b ), the detected coordinates of the alignment mark M _1c are (X _m1c , Y _m1c ), and the detected coordinates of the alignment mark M _1d are (X _m1d , Y _M1D), the detected coordinates of the alignment mark M _2a is (X _m2a, Y _m2a), the detected coordinates of the alignment mark M _2b is (X _m2b, Y _m2b), the detected coordinates of the alignment mark M _2c is (X _{m @ 2 c} , Y _m2c ), alignment mark M _2d
The detected coordinates of _{(X m2d, Y m2d),} ···, detected coordinates of the alignment mark M _la is (X _mla, Y _mla), the detected coordinates of the alignment mark M _lb is (X _mlb, Y _mlb), detected coordinates of the alignment mark M _lc is _{(X ml c, Y mlc)} , the detected coordinates of the alignment mark M _ld have done labeled (X _mld, Y _mld).

The control computer 15 calculates the alignment marks M _1a , M _1b , M _1c , M _1d , M _2a , M _2b , M _2c , M _2d,.
.., M _la , M _lb , M _lc , M _ld detected coordinates (X
_{m1a, Y m1 a), (} X m1b, Y m1b), (X m1c, Y
_{m1c), (X m1d, Y} m1d), (X m2 a, Y m2a),
(X _m2b , Y _m2b ), (X _m2c , Y _m2c ), (X _m2d ,
Y _m2d ), ..., (X _mla , Y _mla ), (X _mlb , Y
_mlb ), (X _mlc , Y _mlc ) and (X _mld , Y _mld ) are expressed as (X _e , Y _e ), and the alignment marks M _1a ,
M _1b , M _1c , M _1d , M _2a , M _2b , M _2c , M _2d , ...,
Design coordinates of each of M _la , M _lb , M _lc , and M _ld (X _md1a , Y
_md1a ), ( _Xm1db , _Ymd1b ), ( _Xmd1c , _Ymd1c ),
(X _md1d , Y _md1d ), (X _md2a , Y _md2a ), (X _m2db ,
Y _md2b ), (X _md2 c, Y _md2c ), (X _md2d , Y _md2d ),
..., (X _mdla , Y _mdla ), (X _mdlb , Y _{md lb} ),
(X _mdlc , Y _mdlc ) and (X _mdld , Y _mdld )
_d , Y _d ), the correction coefficients A, B, C, D, E, F, G, and H satisfying the following equation 1 are calculated using a least square method or the like, and the correction coefficients are calculated. A, B,
C, D, E, F, G, H are defined, and are defined
Give to.

X _e = (1 + A) X _d + BY _d + CX _d · Y _d + D Y _e = EX _d + (1 + F) Y _d + GX _d · Y _d + H (1) _{1, C 2, C 3,} ···,
Gain terms representing the distortion in each of C _n by A and F, B and E
The correction coefficient is obtained by classifying into a rotation term represented by, a trapezoidal term represented by C and G, and a shift term represented by D and H.

Next, the control computer 15, via the sample stage controller 18 controls the sample stage 1, chip C _1, C _2, C ₃ in the wafer 2, ..., and any region of the C _n Position it below the electron optics. The arithmetic unit 10 decomposes the individual pattern data of the graphic data to be exposed in the arbitrary area in the buffer memory 14 into a plurality of shot data, and sequentially determines the shape of the photoelectric surface of the electron beam 4 based on the individual shot data. The data and the irradiation position data of the electron beam 4 on the wafer 2 are calculated and given to the shaping signal generator 9 and the position signal generator 12, respectively. In this case, the calculation unit 10 calculates the correction coefficient A, with respect to the designed irradiation position data of each shot, that is, the designed irradiation position coordinates (X _sd , Y _sd ).
The correction expressed by Equation 2 is performed using B, C, D, E, F, G, and H, and the irradiation position data on the wafer 2, that is, the irradiation position coordinates (X _se , Y _se ) in execution are obtained. It is provided to the position signal generator 12.

X _se = (1 + A) X _sd + BY _sd + CX _sd .Y _sd + _{DY se} = EX _sd + (1 + F) Y _sd + GX _sd .Y _sd + H (Formula 2) The molding signal generator 9 is a molding machine. Forming device 5 via control unit 8
, And the shape of the photocathode of the electron beam 4 is adjusted to an arbitrary shape. The position signal generating unit 12 supplies a focus signal to the objective lens 6 via the lens control unit 11 to focus the electron beam 4 on the surface of the wafer 2, and to control the objective lens 6 via the deflector control unit 13. To irradiate the electron beam 4 to an arbitrary position on the surface of the wafer 2. When the exposure operation for an arbitrary area of the chips C ₁ , C ₂ , C ₃ ,..., C _{n on} the wafer 2 is completed, the control computer 15 controls the sample stage 1 via the sample stage controller 18. And wafer 2
, Another arbitrary area of the chips C ₁ , C ₂ , C ₃ ,..., C _n is positioned below the electron optical system, and the same exposure operation as described above is performed. Chip C ₁ these exposure operation on the wafer _{2, C 2, C 3,} ···, by performing all of the C _n,
The exposure operation for the wafer 2 is completed.

Next, features such as the effects of the electron beam exposure method of this embodiment will be described in comparison with the conventional electron beam exposure method.

In the conventional electron beam exposure method, the necessity of obtaining the designed irradiation position coordinates (X _sd , Y _sd ) of each shot is caused by the distortion of the electron beam exposure apparatus and each electron beam. The correction coefficients A, B, C, D, E, F,
Regarding G and H, the chips C ₁ , C ₂ , C ₃ ,
..., or use the same value in each of the C _n, chip C _1, C _2, C ₃ in the wafer 2, ..., are represented by a linear equation by the position of the wafer 2 in each of the C _n Or
Only values not considering the second-order terms were used.

However, the silicon oxide film formed on the surface of the wafer 2 is charged, or the leakage current from the electrostatic chuck for holding the wafer 2 on the sample stage 1 causes the state in which the wafer 2 has a potential. Has become. Therefore,
As shown in FIG. 3, the equipotential surface 20 is perpendicular to the electron beam 4 inside the wafer 2, but has an inclination with respect to the electron beam 4 at the outer edge of the wafer 2. Then, the electron beam 4 is bent.

Therefore, as shown in FIG.
Each of the chips C ₁ , C ₂ , C ₃ ,..., C _n changes its shape depending on the two-dimensional position of the wafer 2. FIG.
The wafer 2 shown in FIG. 2 is negatively charged and bent outward of the electron beam 4. There is a shift in the vertical gain component above and below the wafer 2, and a shift in the horizontal gain component between the left and right sides of the wafer 2. In these diagonal directions, there is shown a state where there is a rotation of a diamond or a combination of rotation and a trapezoid in a rhombus.

In the conventional electron beam exposure method, the irradiation position coordinates (X _sd , Y _sd ) in the design of each shot described above are corrected to correct the irradiation position coordinates (execution position) of each shot on the wafer 2. X _se , Y _se ) need not be determined because the distortion of the electron beam exposure apparatus and the distance between the electron beam exposure apparatuses were not taken into account. There is a problem that only an average correction is performed for the shift of the gain component and the shift of the rhombus in which the rotation and the trapezoid are combined in the diagonal directions, and the alignment accuracy is deteriorated.

More specifically, when the wafer 2 is charged by several volts, the electron beam 4 is bent by about 0.1 μm at the outer edge of the wafer 4, but is corrected on average. As a result, an alignment error of about 0.05 μm occurs. I do. These are the chips C ₁ , C ₂ , C ₃ ,.
When the two-dimensional position of each of C _n on the wafer 2 is (X _i , Y _i ), the gain component above and below the wafer 2 depends on Y _i · Y _i , and the gain on the left and right The component is X _i
Depending on the X _i, the rotational and trapezoidal components is because not considered to be dependent on X _i · Y _i.

In the electron beam exposure method of the present embodiment, the above-mentioned problems can be solved because the alignment exposure described below is performed.

[0043] That is, first, the control computer 15 as described above, any of a plurality of chips C _m1, used in the exposure operation superposition _{C m2, ···, C mj,} ···, in each of the C _ml Alignment M _1a , M _1b , M _1c , M _1d ,
M _2a , M _2b , M _2c , M _2d , ..., M _la , M _lb , M _lc ,
Each M _ld of detected coordinates _{(X m1a, Y m1a),} (X m1b,
_Ym1b ), ( _Xm1c , _Ym1c ), ( _Xm1d , _Ym1d ),
(X _m2a , Y _m2a ), (X _m2b , Y _m2b ), (X _m2c ,
Y _m2c ), (X _m2d , Y _m2d ), ..., (X _mla , Y
_mla ), (X _mlb , Y _mlb ), (X _mlc , Y _mlc ),
(X _mld , Y _mld ) Any set of detection coordinates (X _mld , Y _mld )
_mja , Y _mja ), (X _mjb , Y _mjb ), (X _mjc , Y
_mjc), (X _MJD, respectively (X _ej of _Y mjd), Y _ej) and then, the design coordinates _{(X mdja, Y mdja),} (X mdjb, Y
_mdjb ), (X _mdjc , Y _mdjc ), and (X _mdjd , Y _{md jd} ) are each represented by (X _dj , Y _dj ), and the correction coefficient in an arbitrary superimposed chip C _mj is A _j , B _j , C _j , D _j ,
E _j , F _j , G _j , and H _j are obtained by the following Expression 3.

[0044] _{X ej = (1 + A j} ) X dj + B j Y dj + C j X dj · Y dj + D j Y ej = E j X dj + (1 + F j) Y dj + G j X dj · Y dj + H j ·· Equation 3 Next, the control computer 15 selects a plurality of arbitrary chips C _m1 , C _m2 ,
_.. , C _mj ,..., C _ml , the individual correction coefficients A _j , B _j , C _j , D _j , E _j , F _j , G _j , H _j Chips C _m1 , C _m2 , ..., C _mj , ...
Using a two-dimensional coordinate (X _j , Y _j ) on the wafer 2 of C _ml, a quadratic equation generally expressed by the following equation 4 is solved by a least square method or the like, and a correction coefficient is obtained. a ₀ , a ₁ , a ₂ , a ₃ , a ₄ ,
_{a 5, b 0, b 1} , b 2, b 3, b 4, b 5, ···, h 0, h 1, h 2, h
₃ , h ₄ and h ₅ are determined.

A _j = a ₀ + a ₁ X _j + a ₂ X _j · X _j + a ₃ X _j · Y _j + a ₄ Y _j · Y _j + a ₅ Y _j B _j = b ₀ + b ₁ X _j + b ₂ X _{j · X j + b 3 X j} · Y j + b 4 Y j · Y j + b 5 Y j C j = c 0 + c 1 X j + c 2 X j · X j + c 3 X j · Y j + c 4 Y j · Y _{j + c 5 Y j D j} = d 0 + d 1 X j + d 2 X j · X j + d 3 X j · Y j + d 4 Y j · Y j + d 5 Y j E j = e 0 + e 1 X j + e 2 _{X j · X j + e 3} X j · Y j + e 4 Y j · Y j + e 5 Y j F j = f 0 + f 1 X j + f 2 X j · X j + f 3 X j · Y j + f 4 Y j _{· Y j + f 5 Y j} G j = g 0 + g 1 X j + g 2 X j · X j + g 3 X j · Y j + g 4 Y j · Y j + g 5 Y j H j = h 0 + h 1 X j the wafer 2 by _{+ h 2 X j · X j} + h 3 X j · Y j + h 4 Y j · Y j + h 5 Y j ··· equation 4 the control computer 15 Chips C ₁ , C ₂ ,
, C _i ,..., C _n , upon exposure of an arbitrary chip C _i , the correction coefficients a ₀ , a ₁ , a ₂ , a ₃ , a
_{4, a 5, b 0,} b 1, b 2, b 3, b 4, b 5, ···, h 0, h 1, h 2,
From h ₃ , h ₄ , h ₅ and the two-dimensional position (X _i , Y _i ) of the arbitrary chip C _{i on} the wafer 2, the correction coefficients A _i , B for the arbitrary chip C _i are obtained by the following equation (5). _i , C _i , D _i ,
By obtaining E _i , F _i , G _i , and H _i , and providing them to the arithmetic unit 10, it is possible to perform accurate exposure.

A _i = a ₀ + a ₁ X _i + a ₂ X _i · X _i + a ₃ X _i · Y _i + a ₄ Y _i · Y _i + a ₅ Y _i B _i = b ₀ + b ₁ X _i + b ₂ X _{i · X i + b 3 X i} · Y i + b 4 Y i · Y i + b 5 Y i C i = c 0 + c 1 X i + c 2 X i · X i + c 3 X i · Y i + c 4 Y i · Y _{i + c 5 Y i D i} = d 0 + d 1 X i + d 2 X i · X i + d 3 X i · Y i + d 4 Y i · Y i + d 5 Y i E i = e 0 + e 1 X i + e _{2 X i · X i + e} 3 X i · Y i + e 4 Y i · Y i + e 5 Y i F i = f 0 + f 1 X i + f 2 X i · X i + f 3 X i · Y i + f 4 Y _{i · Y i + f 5 Y} i G i = g 0 + g 1 X i + g 2 X i · X i + g 3 X i · Y i + g 4 Y i · Y i + g 5 Y i H i = h 0 + h 1 X _{i + h 2 X i · X} i + h 3 X i · Y i + h 4 Y i · Y i + h 5 Y i ··· equation 5 further, in the charged state of the wafer 2, By correcting the shift of the gain component in the vertical and horizontal directions of Eha 2 and the shift of the rhombus in the diagonal direction thereof, the quadratic term in Equation 5 is reduced as in Equation 6 below. be able to.

A _j = a ₀ + a ₁ X _j + a ₂ X _j · X _j + a ₅ Y _j B _j = b ₀ + b ₁ X _j + b ₂ X _j · X _j + b ₅ Y _j C _j = c ₀ + c ₁ X _j + c ₂ X _j · X _j + c ₅ Y _j D _j = d ₀ + d ₁ X _j + d ₂ X _j · X _j + d ₅ Y _j E _j = e ₀ + e ₁ X _j + e ₂ X _j · X _j + e ₅ Y _j F _j = f ₀ + f ₁ X _j + f ₂ X _j · X _j + f ₅ Y _j G _j = g ₀ + g ₁ X _j + g ₂ X _j · X _j + g ₅ Y _j H _j = h ₀ + h _{1 X j + h 2 X j ·} X j + h 5 Y j ··· equation 6 the correction coefficient at an arbitrary chip C _i a _i,
B _i , C _i , D _i , E _i , F _i , G _i , and H _i can be obtained by the following equation (7).

A _i = a ₀ + a ₁ X _i + a ₂ X _i · X _i + a ₅ Y _i B _i = b ₀ + b ₁ X _i + b ₂ X _i · X _i + b ₅ Y _i C _i = c ₀ + c _{1 X i + c 2 X i ·} X i + c 5 Y i D i = d 0 + d 1 X i + d 2 X i · X i + d 5 Y i E i = e 0 + e 1 X i + e 2 X i · X i + e _{5 Y i F i = f 0} + f 1 X i + f 2 X i · X i + f 5 Y i G i = g 0 + g 1 X i + g 2 X i · X i + g 5 Y i H i = h 0 + h 1 X _i + h ₂ X _i · X _i + h ₅ Y _i Equation 7 According to the electron beam exposure method of the present embodiment described above, an arbitrary plurality of chips (chips having alignment marks) C on the wafer 2 _m1 -C _ml alignment marks M _1a ~M _1d in the corner is disposed such corners, to detect the position of the alignment mark M _1a ~M _1d, all chips C ₁ -C _n in the wafer 2 Position and shape When performing corresponding exposure, the chips C _{1 to} C _n are used as a function used for positioning any chip C _i on the wafer 2.
X or X of X and Y of the coordinate system on the wafer 2
Since a function including a quadratic term of Y or Y · Y is used, high-precision overlay exposure can be performed, and therefore, high-precision overlay exposure can be performed.

Further, according to the electron beam exposure method of the present embodiment, it is possible to perform high-precision exposure by performing high-precision overlay exposure, and to perform high-precision exposure by performing high-precision overlay exposure. When a pattern of a semiconductor device is formed by using a lithography technique and a selective etching technique using an electron beam exposure method, the precision of the pattern can be improved. A semiconductor device such as a semiconductor integrated circuit device can be manufactured with a high manufacturing yield.

Further, according to the electron beam exposure method of the present embodiment, it is possible to perform a high-accuracy overlay exposure, and to perform a high-accuracy overlay exposure, thereby achieving lithography using the electron beam exposure method of the present embodiment. Achieving lithography technology that enables microfabrication to be facilitated by the technology, it can be applied to various types and various manufacturing processes of semiconductor devices, such as semiconductor integrated circuit devices, which are microfabricated bodies, and microfabrication can be performed with high precision and easily. Can be done.

(Embodiment 2) FIGS. 5 to 10 are schematic sectional views showing manufacturing steps of a semiconductor integrated circuit device according to Embodiment 2 of the present invention. The method of manufacturing a semiconductor integrated circuit device according to the present embodiment uses the electron beam exposure method of the first embodiment. The method for manufacturing the semiconductor integrated circuit device according to the present embodiment will be specifically described with reference to FIG.

First, as shown in FIG. 5, a silicon oxide film is formed on a device isolation region, which is a selective region on the surface of a semiconductor substrate (wafer) 21 made of, for example, p-type silicon single crystal by using thermal oxidation. Is formed.

Next, a gate insulating film 23 made of, for example, a silicon oxide film is formed on the semiconductor substrate 21, and a CVD (Chemical Vapor Depos) is formed on the gate insulating film 23.
After a conductive polycrystalline silicon film serving as the gate electrode 24 is deposited using the ition method, an insulating film 25 made of, for example, a silicon oxide film is formed thereon.

Thereafter, the resist film 2 is formed on the insulating film 25.
6 is applied, a patterned resist film 26 is formed by using the lithography technique using the electron beam exposure method of Embodiment 1 described above, and then, using the resist film 26 as an etching mask, Using a selective etching technique such as dry etching, a patterned gate electrode 24 is formed and a patterned gate insulating film 23 is formed.

In this case, according to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, the pattern of the resist film 26 is formed by using the lithography technique using the electron beam exposure method of the first embodiment. By doing so, the pattern of the resist film 26 can be made highly accurate by performing high-precision exposure, so that the gate electrode 2 having higher performance and higher reliability can be obtained.
The semiconductor integrated circuit device can be manufactured by using the lithography technique capable of easily performing the fine processing of No. 4.

Next, after removing the unnecessary resist film 26, a sidewall spacer 27 made of, for example, a silicon oxide film is formed on the side wall of the gate electrode 24.
An n-type impurity such as phosphorus is ion-implanted into the semiconductor substrate 21 to form an n-type semiconductor region 28 serving as a source and a drain (FIG. 6).

In the manufacturing process of the above-described semiconductor integrated circuit device, an n-channel MO
In this embodiment, an SFET is formed, but n
P-channel MOSFET other than channel MOSFET,
An embodiment in which various semiconductor elements such as a CMOSFET, a bipolar transistor, and a capacitor are formed can be employed.

Next, after an insulating film 29 made of, for example, a silicon oxide film is formed on the semiconductor substrate 21, the insulating film 2 is formed.
9, a resist film 30 is applied, a patterned resist film 30 is formed by using the lithography technique using the electron beam exposure method of the first embodiment, and then the resist film 30 is removed. A through-hole (connection hole) 31 is formed as a contact hole by using a selective etching technique such as dry etching using the mask as an etching mask (FIG. 7).

In this case, the surface of the insulating film 29 is formed, for example, by depositing a silicon oxide film using a CVD method and then using an etch-back method or a CMP (Chemical Mechanical Polishing) method. The insulating film 29 having a flat surface is formed by a flattening process.

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the pattern of the resist film 30 is formed by using the lithography technique using the electron beam exposure method of the first embodiment. With this, the pattern of the resist film 30 can be made highly accurate by performing high-precision exposure.
A semiconductor integrated circuit device can be manufactured by using a lithography technique capable of easily performing fine processing.

Next, after removing the unnecessary resist film 30, a wiring layer 32 made of, for example, an aluminum layer is deposited on the semiconductor substrate 21, and a resist film 33 is applied on the wiring layer 32. After that, a patterned resist film 33 is formed by using the lithography technique using the electron beam exposure method of Embodiment 1 described above, and then the resist film 33 is used as an etching mask by dry etching or the like. The wiring layer 32 is formed by using the selective etching technique described above (FIG. 8).

In this case, the wiring layer 32 is formed, for example, by depositing an aluminum layer using a sputtering method or a CVD method and then using an etch-back method or a CMP method.
Wiring layer 3 having a flat surface by flattening its surface
It is 2. Before depositing the wiring layer 32, a conductive film such as a tungsten film may be buried in the through hole 31 to form a plug buried in the through hole 31.

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the pattern of the resist film 33 is formed by using the lithography technique using the electron beam exposure method of the first embodiment. With this, the pattern of the resist film 33 can be made highly accurate by performing high-precision exposure, so that the lithography technology that can easily perform fine processing of the wiring layer 32 with high performance and high reliability is used. An integrated circuit device can be manufactured.

Next, after removing the unnecessary resist film 33, an insulating film 34 made of, for example, a silicon oxide film is formed on the semiconductor substrate 21, and a resist film 35 is formed on the insulating film 34. After application, a patterned resist film 35 is formed by using the lithography technique using the electron beam exposure method of the first embodiment, and then dry etching is performed by using the resist film 35 as an etching mask. Through holes 36 are formed by using a selective etching technique such as (FIG. 9).

In this case, the insulating film 35 has a flat surface by, for example, depositing a silicon oxide film by using a CVD method and then flattening the surface by using an etch-back method or a CMP method. The insulating film 35 is used.

Further, according to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, the pattern of the resist film 35 is formed by using the lithography technique using the electron beam exposure method of the first embodiment. Since the patterning of the resist film 35 can be performed with high precision by performing high-precision exposure, the performance and reliability of the through hole 36 can be improved.
A semiconductor integrated circuit device can be manufactured by using a lithography technique capable of easily performing fine processing.

Next, after removing the unnecessary resist film 35, a wiring layer 37 made of, for example, an aluminum layer is deposited on the semiconductor substrate 21, and a resist film 38 is applied on the wiring layer 37. After that, a patterned resist film 38 is formed by using the lithography technique using the electron beam exposure method of Embodiment 1 described above, and then the resist film 38 is used as an etching mask to perform dry etching or the like. The wiring layer 38 is formed by using the selective etching technique described above (FIG. 10).

In this case, the wiring layer 37 is formed, for example, by depositing an aluminum layer using a sputtering method or a CVD method and then using an etch-back method or a CMP method.
Wiring layer 3 having a flat surface by flattening its surface
7 is assumed. Before depositing the wiring layer 37, a conductive film such as a tungsten film may be embedded in the through-hole 36 to form a plug embedded in the through-hole 36.

Further, according to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, the pattern of the resist film 38 is formed by using the lithography technique using the electron beam exposure method of the first embodiment. With this, the pattern of the resist film 38 can be made highly accurate by performing high-precision exposure, so that the lithography technology that can easily perform fine processing of the wiring layer 37 with high performance and high reliability is used. An integrated circuit device can be manufactured.

Thereafter, according to the design specifications, the above-described manufacturing steps (wiring layer 32 as a first wiring layer, insulating film 34 as an interlayer insulating film, through hole 36, wiring as a second wiring layer) By repeating the manufacturing process of the layer 37)
By forming the multilayer wiring layer, the manufacturing process of the semiconductor integrated circuit device according to the present embodiment ends.

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the resist films 26, 30, 33, and 35 are formed by using the lithography technique using the electron beam exposure method of the first embodiment. , 38, the resist film 2 is exposed with high precision.
6, 30, 33, 35, and 38 patterns can be made more precise, so that the performance and reliability of the gate electrode 2 can be improved.
4, through hole 31, wiring layer 32, through hole 3
6. A semiconductor integrated circuit device can be manufactured by using a lithography technique capable of easily performing fine processing of the wiring layer 37.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the lithography technique using the above-described electron beam exposure method of the first embodiment is used, so that highly accurate exposure can be performed. It can be used to form high-performance and highly reliable wiring layers and through-hole patterns and to facilitate microfabrication, so it can be applied to various types of microfabricated semiconductor integrated circuit devices and various manufacturing processes. Thus, the fine processing can be performed with high accuracy and easily.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, according to the present invention, a semiconductor substrate (wafer) on which a semiconductor element is formed is formed by SOI (Silicon on Insul).
ator) The substrate can be changed to various substrates such as a substrate. As a semiconductor element formed on a substrate (wafer) such as a semiconductor substrate, in addition to MOSFET, various semiconductor elements such as a CMOSFET and a bipolar transistor are combined. A semiconductor element can be applied.

The present invention relates to a MOSFET, a CMOS,
Logic or DRA with FET etc. as components
M (Dynamic Random Access Memory), SRAM (Stat
The present invention can be applied to a method of manufacturing various semiconductor integrated circuit devices having a memory system such as an IC (Random Access Memory).

[0076]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the electron beam exposure method of the present invention, alignment marks are arranged at corners such as four corners of a plurality of arbitrary chips (chips having alignment marks) on a wafer, and the positions of the alignment marks are detected. When performing exposure corresponding to the position and shape of a chip on a wafer, XX or X of X and Y of the coordinate system of the chip on the wafer is used as a function used for alignment of the chip on the wafer.・ Y or Y ・ Y
By using a function that includes the quadratic term
Since accurate alignment exposure can be performed, highly accurate overlay exposure can be performed.

(2). According to the electron beam exposure method of the present invention, high-precision exposure can be performed by performing high-precision overlay exposure, and high-precision overlay exposure can be performed. In addition, when the pattern of the semiconductor device is formed by using the selective etching technology, the precision of the pattern can be improved, so that a semiconductor device such as a semiconductor integrated circuit device that can be finely processed and has high performance and high reliability can be manufactured. It can be manufactured with a high manufacturing yield.

(3). According to the electron beam exposure method of the present invention, it is possible to perform high-precision overlay exposure, and to perform high-precision overlay exposure, thereby facilitating fine processing by the lithography technique using the electron beam exposure method of the present invention. Since the technology can be achieved, the fine processing can be performed with high accuracy and easily by applying to various kinds and various manufacturing processes of semiconductor devices such as a semiconductor integrated circuit device which is a fine processed body.

(4). According to the method of manufacturing a semiconductor device such as the semiconductor integrated circuit device of the present invention, since the pattern of the resist film is formed by using the lithography technique using the electron beam exposure method of the present invention, highly accurate exposure can be achieved. To improve the accuracy of the resist film pattern, so that the gate electrode, through hole,
A semiconductor device such as a semiconductor integrated circuit device can be manufactured by using a lithography technique capable of easily performing fine processing of a wiring layer and the like.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an electron beam exposure apparatus used in an electron beam exposure method according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing a wafer used in the electron beam exposure method according to the first embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a wafer used in the electron beam exposure method according to the first embodiment of the present invention.

FIG. 4 is a schematic plan view showing a wafer and chips on the wafer used in the electron beam exposure method according to the first embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 6 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 7 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 8 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 9 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 10 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Sample stand 2 Wafer 3 Electron beam source 4 Electron beam 5 Shaping device 6 Objective lens 7 Deflector 8 Shaping device control part 9 Shaping signal generation part 10 Operation part 11 Lens control part 12 Position signal generation part 13 Deflector control part 14 Buffer Memory 15 Control computer 16 Exposure data storage unit 17 Mark position detector 18 Sample stage control unit 19 Backscattered electron 20 Equipotential surface 21 Semiconductor substrate (wafer) 22 Field insulating film 23 Gate insulating film 24 Gate electrode 25 Insulating film 26 Resist film 27 Sidewall spacer 28 Semiconductor region 29 Insulating film 30 Resist film 31 Through hole 32 Wiring layer 33 Resist film 34 Insulating film 35 Resist film 36 Through hole 37 Wiring layer 38 Resist film C ₁ , C ₂ , C ₃ , C _n chip C _m1 , C _m2 , C _m3 , C _ml Chips having alignment marks M _1a , M _{1 b,} M _1c, M _1d alignment mark _{M 2a, M 2b, M 2c} , M 2d alignment mark _{M la, M lb, M lc} , M ld alignment mark

Continued on the front page (72) Inventor Hideki Sekine 3-3-2 Fujibashi, Ome-shi, Tokyo 2 Hitachi Tokyo Electronics Co., Ltd.

Claims (8)

[Claims] An alignment mark is arranged at a corner of a plurality of arbitrary chips on a wafer, and the position of the alignment mark is detected, and exposure is performed in accordance with the position and shape of the chip on the wafer. X and Y of the coordinate system of the chips on the wafer as functions used for the alignment of the chips on the wafer.
An electron beam exposure method, wherein a function including a quadratic term of XX or XY or YY is used. 2. The electron beam exposure method according to claim 1, wherein alignment marks of a plurality of chips on the wafer are arranged at four corners of the chip, and the function includes a gain of the chip. An electron beam exposure method, wherein at least one of correction terms such as correction, rotation, and shift is included. 3. The electron beam exposure method according to claim 2, wherein alignment marks are arranged at four corners of a plurality of chips on the wafer, and the position of the alignment mark is detected, so that the wafer is exposed. An electron beam exposure method comprising performing correction such as gain, rotation, shift, and the like on a chip inside the device, and performing overlay exposure. 4. The electron beam exposure method according to claim 3, wherein the gain term in the X direction of the coordinate system on the wafer in the gain term has an X · X term, and the gain term is on the wafer. Wherein the gain term in the Y direction of the coordinate system has a Y · Y term, and the rotation term has an XY term. 5. A manufacturing process for forming a pattern of a semiconductor device using a lithography technique and a selective etching technique using the electron beam exposure method according to claim 1. Manufacturing method of a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the pattern of the semiconductor device is a pattern of a semiconductor integrated circuit device. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the pattern is a pattern of a through hole formed in an insulating film. 8. The method for manufacturing a semiconductor device according to claim 5, wherein said pattern is a pattern of a wiring layer.