JPH1126342A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor integrated circuit device wherein a lithographic technology in which matching precision is high, while fine working is easy to be made. SOLUTION: Using a lithography technology which uses a light-exposure device, a pattern for forming a gate electrode 24 on a resist film coated on the surface of a semiconductor substrate (wafer) 21 is formed. Then, after a unwanted resist film has been removed, a pattern for forming a through-hole 31 on a resist film coated on the surface of the semiconductor substrate 21 is formed, using a lithography technology which uses an electron beam exposure device. Then, after a unwanted resist film has been removed, using a lithography technology which uses a different light exposure device from the light exposure device, a pattern for forming an interconnection layer 32 on a resist film 33 coated on the surface of the semiconductor substrate 21 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of manufacturing a semiconductor integrated circuit device using a lithography technique using an electron beam exposure apparatus, which can achieve high alignment accuracy and facilitate fine processing. The present invention relates to a method for manufacturing a semiconductor integrated circuit device used.

[0002]

2. Description of the Related Art The present inventors have studied a method of manufacturing a semiconductor integrated circuit device. The following is a technique studied by the present inventors, and the outline is as follows.

That is, in a manufacturing process of a semiconductor integrated circuit device, a manufacturing process of manufacturing a plurality of semiconductor elements on a wafer-like semiconductor substrate and an insulating film such as an interlayer insulating film having a wiring layer and a through hole are formed on the semiconductor substrate. A lithography technique using a light exposure apparatus is used in a manufacturing process for manufacturing.

[0004] The light exposure apparatus selects an exposure apparatus or changes an exposure illumination system according to necessity.

[0005] References describing the light exposure apparatus include, for example, “Electronic Materials November 1987 Special Edition”, p.
To p83.

[0006]

However, a lithography technique using a light exposure apparatus is used to make a MOSFET.
(Metal Oxide Semiconductor Field Effect Transisto
r) After the pattern of the gate electrode is formed, the lithography technique using another light exposure apparatus is used to form the pattern of the through-hole in the insulating film on the gate electrode. There is a problem that the alignment accuracy between the pattern and the through-hole pattern is 0.1 μm or more, and the alignment accuracy is reduced (deteriorated).

Therefore, after a pattern of a gate electrode is formed using a lithography technique using a light exposure apparatus, the insulating film on the gate electrode is formed using a lithography technique using another light exposure apparatus. The formation of the through-hole pattern deteriorates the alignment accuracy between the gate electrode pattern and the through-hole pattern, so that fine processing is difficult.

It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device using a lithography technique capable of achieving high alignment accuracy and facilitating fine processing.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, a pattern is formed on a first resist film applied on a surface of a wafer by using a lithography technique using a light exposure apparatus, and The first semiconductor film is processed using the resist film as a mask, and then, after removing the unnecessary first resist film, a second semiconductor film is deposited, and a second semiconductor film is formed on the surface thereof. A resist film is applied, a pattern is formed on the second resist film applied to the surface of the wafer by using a lithography technique using an electron beam exposure apparatus, and a second is formed using the second resist film as a mask. After processing the semiconductor forming film, and after removing the unnecessary second resist film, a third semiconductor forming film is applied, and a third resist film is applied to the surface thereof, Lithography technology using Use, the forming a pattern on the third resist film applied on the surface of the wafer, in which processing the third semiconductor forming film using the third resist film as a mask.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) FIG. 1 is a schematic configuration diagram showing an electron beam (electron beam) exposure apparatus used in a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.

In the electron beam exposure apparatus used in the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, for example, a semiconductor integrated circuit device such as a semiconductor integrated circuit device is mounted on a sample stage 1. The wafer 2 is set. In this case, the sample table 1 has a function such as an XY table function movable in a horizontal plane, and a resist film is applied on the surface of the wafer 2. Further, a plurality of chips are arranged on the wafer 2, and alignment marks are provided at four corners of an arbitrary chip.

On the other hand, an electron beam source 3 is provided above the sample stage 1, and the wafer 2 set on the sample stage 1
Is configured to radiate an electron beam 4 to the electron beam.

Between the electron beam source 3 and the sample table 1, there is provided an electron optical system including a molding unit 5, an objective lens 6, a deflector 7, and the like. In this case, the electron beam source 3
After the photoelectron surface is shaped into a predetermined shape by the shaping device 5, the electron beam 4 emitted from the wafer 2 is focused on the surface of the wafer 2 by the objective lens 6, and deflected by the deflector 7. Is irradiated to the position.

The molding device 5 is electrically connected to a calculation unit 10 via a molding device control unit 8 and a molding signal generation unit 9. Further, the objective lens 6 is electrically connected to the calculation unit 10 via the lens control unit 11 and the position signal generation unit 12. The deflector 7 is electrically connected to the calculation unit 10 via the deflector control unit 13 and the position signal generation unit 12.

The operation unit 10 is electrically connected to the control computer 15 via a buffer memory 14 which can be accessed at high speed, and is also directly electrically connected to the control computer 15.

The control computer 15 is composed of, for example, a large-capacity magnetic disk, and is electrically connected to an exposure data storage 16 for storing a plurality of graphic data to be exposed on the wafer 2. In this case, the control computer 15 can transfer predetermined exposure data appropriately selected to the buffer memory 14 as needed.

The control computer 15 is electrically connected to a mark position detector 17 disposed near the wafer 2 set on the sample table 1. Therefore, the control computer 15 can move the sample stage 1 via the sample stage control unit 18 and sequentially position the alignment marks below the electron optical system. In addition, the deflector 7 is controlled via the calculation unit 10, the position signal generation unit 12, and the deflector control unit 13 using scan data for scanning the electron beam 4 on the alignment mark in the buffer memory 14. The reflected electron 19 obtained by scanning the electron beam 4 over each of the alignment marks is received by the mark position detection unit 17, and the detected coordinates of each of the alignment marks can be obtained. Further, the control computer 15 has a sample stage 1 via a sample stage controller 18.
Are electrically connected. Therefore, it is possible to control the positioning of an arbitrary exposure area of the wafer 2 below the electron optical system.

Therefore, when various patterns are formed on a resist film on a wafer by using a lithography technique using an electron beam exposure apparatus, a predetermined pattern is formed by controlling an electron beam lithography system. It can be formed with high precision.

In the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, a lithography technique using a light exposure apparatus is used, and a gate of a MOSFET is formed by using a resist film applied to the surface of a wafer made of a semiconductor substrate. After forming the electrode pattern, a through-hole pattern is formed in the insulating film above the gate electrode by using a lithography technique using an electron beam exposure apparatus. Thereafter, using a lithography technique using a light exposure device different from the light exposure device,
A wiring layer pattern is formed on the insulating film.

In this case, since a lithography technique using a light exposure apparatus is used to form a gate electrode pattern, as shown in FIG. There will be a pattern S ₁ that has occurred is formed.

Further, since a lithography technique using a light exposure apparatus different from the above-mentioned light exposure apparatus is used to form a pattern of the wiring layer, as shown in FIG. so that the pattern S ₂ where distortion occurs is formed for. Results of study of the present inventors, the alignment accuracy between the pattern S ₁ and the pattern S ₂ is a 0.1μm or more, in the present embodiment has a 0.14 .mu.m.

Therefore, the pattern S ₁ and the pattern S ₂
The alignment accuracy of 0.14 μm is obtained by using a lithography technique using an electron beam exposure apparatus, which uses an alignment correction coefficient that provides an alignment accuracy of 0.07 μm, which is almost half the value. A pattern of a through hole is formed in the insulating film on the electrode. In this case, as shown in FIG. 2, so that the pattern E in which the pattern S ₁ and the pattern S ₂ intermediate distortion occurs with respect to the pattern A design specification is formed.

As a result, in the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, after a pattern of a gate electrode is formed by using a lithography technique using a light exposure apparatus, a pattern S ₁ and a pattern S ₂ are formed. Alignment accuracy (0.14μm
Using a lithography technique with an electron beam exposure apparatus, a through-hole pattern is formed in the insulating film above the gate electrode, using a correction coefficient to obtain an alignment accuracy of half the value (0.07 μm) After that, by using a lithography technique using a light exposure device different from the light exposure device, by forming a pattern of the wiring layer on the insulating film, the light exposure device The alignment accuracy (0.14μ) when a pattern is formed using the lithography technology used
m) with an alignment accuracy of half the value (0.07 μm)
The matching accuracy of each pattern can be obtained.

Therefore, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, a value which is half the alignment accuracy (0.14 μm) when a pattern is formed by using a lithography technique using a light exposure apparatus. Manufacturing of a semiconductor integrated circuit device by using a lithography technique capable of achieving high alignment accuracy and facilitating fine processing by being able to achieve alignment accuracy of each pattern with an alignment accuracy of (0.07 μm). Can be.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, a lithography technique capable of achieving high alignment accuracy and facilitating fine processing can be achieved. The present invention can be applied to various kinds and various manufacturing processes to perform fine processing with high accuracy and easily.

(Embodiment 2) FIGS. 3 to 8 are schematic sectional views showing manufacturing steps of a semiconductor integrated circuit device according to Embodiment 2 of the present invention. The method for manufacturing the semiconductor integrated circuit device according to the present embodiment will be specifically described with reference to FIG.

First, as shown in FIG. 3, a silicon oxide film is formed on a device isolation region, which is a selective region on the surface of a semiconductor substrate (wafer) 21 made of, for example, p-type silicon single crystal by using thermal oxidation. Is formed.

Next, a gate insulating film 23 made of, for example, a silicon oxide film is formed on the semiconductor substrate 21, and a CVD (Chemical Vapor Depos) is formed on the gate insulating film 23.
After a conductive polycrystalline silicon film serving as the gate electrode 24 is deposited using the ition method, an insulating film 25 made of, for example, a silicon oxide film is formed thereon.

After that, the resist film 2 is formed on the insulating film 25.
6 is applied, a patterned resist film 26 is formed by using a lithography technique using a light exposure apparatus, and a selective etching technique such as dry etching is performed by using the resist film 26 as an etching mask. Used to form a patterned gate electrode 24 and a patterned gate insulating film 23.

Next, after removing the unnecessary resist film 26, a sidewall spacer 27 made of, for example, a silicon oxide film is formed on the side wall of the gate electrode 24.
An n-type impurity such as phosphorus is ion-implanted into the semiconductor substrate 21 to form an n-type semiconductor region 28 serving as a source and a drain (FIG. 4).

In the manufacturing process of the semiconductor integrated circuit device described above, an n-channel
In this embodiment, an SFET is formed, but n
P-channel MOSFET other than channel MOSFET,
An embodiment in which various semiconductor elements such as a CMOSFET, a bipolar transistor, and a capacitor are formed can be employed.

Next, after an insulating film 29 made of, for example, a silicon oxide film is formed on the semiconductor substrate 21, the insulating film 2 is formed.
9, a resist film 30 is applied, a patterned resist film 30 is formed using a lithography technique using an electron beam exposure apparatus, and then the resist film 30 is used as an etching mask. A through hole (connection hole) 31 as a contact hole is formed by using a selective etching technique such as dry etching (FIG. 5).

In this case, the surface of the insulating film 29 is formed, for example, by depositing a silicon oxide film using a CVD method and then using an etch-back method or a CMP (Chemical Mechanical Polishing) method. The insulating film 29 having a flat surface is formed by a flattening process.

Further, a pattern of the wiring layer 32 is formed on the insulating film 29 by using a lithography technique using a light exposure device different from the light exposure device by a manufacturing process described later. Therefore, since the alignment accuracy between the pattern of the gate electrode 24 and the wiring layer 32 is 0.14 μm, a lithography technique using an electron beam exposure apparatus that obtains a half value of 0.07 μm is used. Thus, a pattern of a through hole 31 is formed in the insulating film 29.

As a result, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, half the alignment accuracy (0.14 μm) in the case of forming a pattern by using a lithography technique using a light exposure apparatus. A semiconductor integrated circuit device can be manufactured by using a lithography technique capable of achieving high alignment accuracy and facilitating fine processing because the alignment accuracy of each pattern can be adjusted with the alignment accuracy of the value (0.07 μm). be able to.

Next, after removing the unnecessary resist film 30, a wiring layer 32 made of, for example, an aluminum layer is deposited on the semiconductor substrate 21, and a resist film 33 is applied on the wiring layer 32. After that, using a lithography technique using a different light exposure device from the light exposure device,
After forming the patterned resist film 33, the wiring layer 32 is formed by using the resist film 33 as an etching mask and using a selective etching technique such as dry etching (FIG. 6).

In this case, the wiring layer 32 is formed, for example, by depositing an aluminum layer using a sputtering method or a CVD method and then using an etch-back method or a CMP method.
Wiring layer 3 having a flat surface by flattening its surface
It is 2. Before depositing the wiring layer 32, a conductive film such as a tungsten film may be buried in the through hole 31 to form a plug buried in the through hole 31.

Next, after removing the unnecessary resist film 33, an insulating film 34 made of, for example, a silicon oxide film is formed on the semiconductor substrate 21, and a resist film 35 is formed on the insulating film 34. After the application, a patterned resist film 35 is formed by using a lithography technique using an electron beam exposure apparatus, and then a selective etching technique such as dry etching is used by using the resist film 35 as an etching mask. Thus, a through hole 36 is formed (FIG. 7).

In this case, the insulating film 35 has a flat surface by, for example, depositing a silicon oxide film by using a CVD method and then flattening the surface by using an etch-back method or a CMP method. The insulating film 35 is used.

Further, a pattern of the wiring layer 37 is formed on the insulating film 34 by a lithography technique using a light exposure device different from the light exposure device in a manufacturing process described later. Therefore, the alignment accuracy between the pattern of the first wiring layer 32 and the second wiring layer 37 is 0.14 μm.
Accordingly, the pattern of the through-hole 36 is formed in the insulating film 34 by using a lithography technique using an electron beam exposure apparatus that can obtain an alignment accuracy of 0.07 μm, which is half the value.

As a result, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, half the alignment accuracy (0.14 μm) when a pattern is formed by using a lithography technique using a light exposure apparatus. A semiconductor integrated circuit device can be manufactured by using a lithography technique capable of achieving high alignment accuracy and facilitating fine processing because the alignment accuracy of each pattern can be adjusted with the alignment accuracy of the value (0.07 μm). be able to.

Next, after removing the unnecessary resist film 35, a wiring layer 37 made of, for example, an aluminum layer is deposited on the semiconductor substrate 21, and a resist film 38 is applied on the wiring layer 37. After that, using a lithography technique using a different light exposure device from the light exposure device,
After forming the patterned resist film 38, the wiring layer 38 is formed by using the resist film 38 as an etching mask and by using a selective etching technique such as dry etching (FIG. 8).

In this case, the wiring layer 37 is formed, for example, by depositing an aluminum layer using a sputtering method or a CVD method and then using an etch-back method or a CMP method.
Wiring layer 3 having a flat surface by flattening its surface
7 is assumed. Before depositing the wiring layer 37, a conductive film such as a tungsten film may be embedded in the through-hole 36 to form a plug embedded in the through-hole 36.

Thereafter, according to the design specifications, the above-described manufacturing steps (wiring layer 32 as a first wiring layer, insulating film 34 as an interlayer insulating film, through hole 36, wiring as a second wiring layer) By repeating the manufacturing process of the layer 37)
By forming the multilayer wiring layer, the manufacturing process of the semiconductor integrated circuit device according to the present embodiment ends.

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment described above, a pattern such as the gate electrode 24 and the first wiring layer 32 is formed by lithography using an optical exposure apparatus. , The value (0.07 μm) that is half of the alignment accuracy (0.14 μm) of those patterns
m) A pattern (for example, a through hole formed in the insulating film 29) between patterns formed using a lithography technique using an optical exposure apparatus, 31), the alignment accuracy of a half value (0.07 μm) of the alignment accuracy (0.14 μm) when a pattern is formed using a lithography technique using a light exposure apparatus. , Matching accuracy of each pattern.

Therefore, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the value which is half the alignment accuracy (0.14 μm) when a pattern is formed by using a lithography technique using a light exposure apparatus. Manufacturing of a semiconductor integrated circuit device by using a lithography technique capable of achieving high alignment accuracy and facilitating fine processing by being able to achieve alignment accuracy of each pattern with an alignment accuracy of (0.07 μm). Can be.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, a lithography technique capable of achieving high alignment accuracy and facilitating fine processing can be achieved. The present invention can be applied to various kinds and various manufacturing processes to perform fine processing with high accuracy and easily.

In the above description, an example in which different light exposure apparatuses are used has been described. However, even if the same light exposure apparatus is used, if different illumination systems are used, the phenomenon of different distortions is the same. The effect used is the same.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, according to the present invention, a semiconductor substrate (wafer) on which a semiconductor element is formed is formed on an SOI (Silicon on Insul
ator) The substrate can be changed to various substrates such as a substrate. As a semiconductor element formed on a substrate such as a semiconductor substrate, M
In addition to the OSFET, a semiconductor element in which various semiconductor elements such as a CMOSFET and a bipolar transistor are combined can be applied.

The present invention also relates to a MOSFET, a CMOS,
Logic or DRA with FET etc. as components
M (Dynamic Random Access Memory), SRAM (Stat
The present invention can be applied to a method of manufacturing various semiconductor integrated circuit devices having a memory system such as an IC (Random Access Memory).

[0055]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a half value (for example, 0.07 μm) of the alignment accuracy (for example, 0.14 μm) when a pattern is formed by using a lithography technique using a light exposure apparatus. Since the alignment accuracy of each pattern can be adjusted to the alignment accuracy of the respective patterns, a semiconductor integrated circuit device can be manufactured using a lithography technique capable of achieving high alignment accuracy and facilitating fine processing.

(2). ADVANTAGE OF THE INVENTION According to the manufacturing method of the semiconductor integrated circuit device of this invention, since the lithography technique which is high in alignment accuracy and which can easily perform fine processing can be achieved, various kinds and various manufacturing of the semiconductor integrated circuit device which is a finely processed body are achieved. By applying the present invention to a process, fine processing can be performed with high precision and easily.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an electron beam exposure apparatus used in a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a pattern for describing a method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 4 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 5 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 6 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 7 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 8 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Sample stand 2 Wafer 3 Electron beam source 4 Electron beam 5 Shaping device 6 Objective lens 7 Deflector 8 Shaping device control part 9 Shaping signal generation part 10 Operation part 11 Lens control part 12 Position signal generation part 13 Deflector control part 14 Buffer Memory 15 Control computer 16 Exposure data storage unit 17 Mark position detector 18 Sample stage control unit 19 Backscattered electrons 21 Semiconductor substrate (wafer) 22 Field insulating film 23 Gate insulating film 24 Gate electrode 25 Insulating film 26 Resist film 27 Side wall spacer 28 Semiconductor region 29 Insulating film 30 Resist film 31 Through hole 32 Wiring layer 33 Resist film 34 Insulating film 35 Resist film 36 Through hole 37 Wiring layer 38 Resist film A pattern E pattern S ₁ pattern S ₂ pattern

Claims (5)

[Claims] 1. A pattern is formed on a first resist film applied to a surface of a wafer by using a lithography technique using a light exposure apparatus, and a first semiconductor forming film is formed using the first resist film as a mask. Then, after removing the unnecessary first resist film, a second semiconductor forming film is applied, a second resist film is applied on the surface thereof, and an electron beam exposure apparatus is used. Using a lithography technique, a pattern is formed on the second resist film applied to the surface of the wafer, and the second semiconductor film is processed using the second resist film as a mask. After removing the second resist film, a third semiconductor forming film is applied, a third resist film is applied to the surface thereof, and the lithography technique using a light exposure apparatus is used. The second coating applied to the surface of the wafer A method for manufacturing a semiconductor integrated circuit device, comprising: forming a pattern on a third resist film; and processing the third semiconductor formation film using the third resist film as a mask. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second resist film applied to the surface of the wafer is formed by using a lithography technique using the electron beam exposure apparatus. When forming a pattern, using a lithography technique using the light exposure apparatus, to form a pattern on the first or third resist film applied to the surface of the wafer, those patterns A method for manufacturing a semiconductor integrated circuit device, wherein a matching coefficient between the matching coefficients is used. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the light exposure apparatus forms a pattern on the first resist film, and a pattern is formed on the third resist film. A method for manufacturing a semiconductor integrated circuit device, wherein the method is different from the light exposure apparatus. 4. A pattern of a gate electrode of a MOSFET is formed on a first resist film applied to a surface of a wafer by using a lithography technique using a light exposure apparatus. After removing the resist film, using a lithography technique using an electron beam exposure apparatus, to form a pattern of through holes in the insulating film on the wafer in the second resist film applied to the surface of the wafer, Then, after removing the unnecessary second resist film, the wiring on the insulating film is applied to the third resist film applied on the surface of the wafer by using a lithography technique using a light exposure apparatus. A method for manufacturing a semiconductor integrated circuit device, comprising forming a layer pattern. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said wafer is a substrate such as a semiconductor substrate or an SOI substrate for manufacturing a semiconductor integrated circuit device. A method for manufacturing an integrated circuit device.