JPH07235477A - Fabrication of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance the plotting accuracy while shortening the exposing time by employing a positive or negative electron beam resist selectively depending on the area of an integrated circuit and coating the surface of a chemical amplification system electron beam resist with a conductive polymer. CONSTITUTION:Positive and negative electron beam resists are employed selectively for the contact hole making process and the wiring forming process. When a contact hole is made, an insulating film 20 is deposited at first on the main plane of a semiconductor wafer 2 and a chemical amplification system positive electron beam resist 21 is applied thereon. A positive polymer 22 is further applied thereon and then the surface of the semiconductor wafer 2 is irradiated with an electron beam. Subsequently, the positive electron beam resist 21 is baked. The semiconductor wafer 2 is washed with water to remove the conductive polymer 22 on the surface and then the positive electron beam resist 21 is developed using an organic solvent. Thereafter, the insulating film 20 is etched to make a contact hole 23 and then the positive electron beam resist 21 is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to fine processing of an integrated circuit pattern using an electron beam resist.

[0002]

2. Description of the Related Art Of the manufacturing process of a semiconductor integrated circuit device,
In the exposure step of transferring a desired integrated circuit pattern onto a semiconductor wafer, in recent years, an electron beam exposure technique has been used instead of the exposure technique using ultraviolet light. Among them, the electron beam direct writing method, in which a semiconductor wafer coated with an electron beam resist is irradiated with an electron beam to directly write an integrated circuit pattern, is a conventional light beam that transfers the integrated circuit pattern formed on the photomask onto the semiconductor wafer. It is particularly noted because it can form a finer integrated circuit pattern than the exposure method.

However, the above electron beam direct writing method is
Unlike the optical exposure method in which the integrated circuit pattern on the photomask is collectively transferred to the semiconductor wafer, the integrated circuit pattern is drawn on the semiconductor wafer by the electron beam focused into a predetermined shape, so how to reduce this drawing throughput. Is a particularly important issue.

The first factor that determines the drawing throughput is the irradiation time required to expose the resist.
Therefore, the development of electron beam resists with higher sensitivity is currently underway in various fields. As an example of this, an acid is liberated in the resist by electron beam irradiation, and this acid is used as a catalyst by heat treatment after exposure. So-called chemically amplified resists have been proposed which are designed to accelerate the exposure reaction.

Regarding the above chemically amplified resist, for example, “Journal of Photopolymer Science.
And Technology (Journal of Photopolymer Scien
ce and Technology), Volume 2, No.1 (1989) '' P115〜
There is a description on P122 etc.

[0006]

However, a chemically amplified electron beam resist which promotes an exposure reaction by using an acid generated from the resist upon irradiation of an electron beam as a catalyst, is
While high sensitivity and resolution can be obtained, the change over time is large,
Since its handling is complicated, there is a problem that it is not practical.

An object of the present invention is to provide a technique capable of realizing high-throughput electron beam direct writing.

Another object of the present invention is to provide a technique capable of realizing highly accurate electron beam direct writing using a chemically amplified electron beam resist.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1). A method for manufacturing a semiconductor integrated circuit device according to the present invention comprises irradiating a chemically amplified electron beam resist deposited on a semiconductor wafer with an electron beam, and applying a resist to a developing solution in an irradiated portion and an unirradiated portion. Equipped with a plurality of electron beam exposure step of forming a resist pattern by utilizing the difference in dissolution rate, a positive type electron beam resist is used in some steps of the plurality of electron beam exposure steps, and in some other steps. A negative type electron beam resist is used.

(2). In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the manufacturing method according to (1) above, a conductive polymer is formed on the surface of the chemically amplified electron beam resist prior to the irradiation with the electron beam. To be attached.

(3). The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing the semiconductor integrated circuit device according to the above (1), wherein the electron beam is generated based on electron beam drawing pattern data corresponding to the inside of the actual pattern of the integrated circuit. It is to irradiate.

(4). A method of manufacturing a semiconductor integrated circuit device according to the present invention applies the manufacturing method of (1) to a semiconductor integrated circuit device for a specific purpose.

(5). The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing the semiconductor integrated circuit device according to (2) above, wherein when the chemically amplified electron beam resist is irradiated with an electron beam, the conductive polymer is grounded. To bring the surface potential of the conductive polymer to the ground potential.

(6) The method for manufacturing a semiconductor integrated circuit device according to the present invention comprises a plurality of exposure steps of exposing a resist deposited on a semiconductor wafer to form a resist pattern. In some steps, a chemically amplified electron beam resist is irradiated with an electron beam to form a resist pattern, and in some other steps, the resist pattern is formed by a light projection exposure method using a photomask.

(7). The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a semiconductor integrated circuit device according to the above (6), wherein in the step of forming the integrated circuit element, a resist pattern is formed by at least one step by the light projection exposure method. And forming a wiring on the integrated circuit element, a resist pattern is formed by an electron beam exposure method using the chemically amplified electron beam resist.

(8). In the method for manufacturing a semiconductor integrated circuit device of the present invention, in the manufacturing method according to (6) above, a chemically amplified positive type electron beam resist is used in a part of the step of forming an integrated circuit element, Another part uses a chemically amplified negative type electron beam resist.

(9). The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a semiconductor integrated circuit device according to the above (6), wherein the chemically amplified electron beam resist is irradiated with an electron beam to form a resist pattern. A plurality of steps are provided, and a positive electron beam resist is used in a part of the plurality of electron beam exposure steps, and a negative electron beam resist is used in another part of the steps.

(10). The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a semiconductor integrated circuit device according to the above (6), wherein the minimum dimension of a resist pattern formed by irradiating the chemically amplified electron beam resist with an electron beam. Is less than or equal to the wavelength of the exposure light used in the light projection exposure method.

(11). In the method for manufacturing a semiconductor integrated circuit device of the present invention, a chemical amplification type positive electron beam is used in a part of the step of forming wiring on the integrated circuit element in the manufacturing method according to the above (7). A resist is used, and a chemically amplified negative type electron beam resist is used in another part.

(12). In the method for manufacturing a semiconductor integrated circuit device of the present invention, in the manufacturing method according to (8) above, a gate electrode of a MISFET is formed by using the chemical amplification type negative electron beam resist, and the chemical amplification is performed. A system positive type electron beam resist is used to form a through hole for connecting the MISFET and a wiring formed on the MISFET.

(13). In the method for manufacturing a semiconductor integrated circuit device of the present invention, wiring is performed by using a resist pattern obtained by irradiating a chemically amplified electron beam resist deposited on a semiconductor wafer with an electron beam as a mask. When forming a contact hole for connection, the following steps (a) to (e) are provided.

(A) An insulating film is deposited on a semiconductor wafer on which an integrated circuit element is formed, a chemical amplification type positive electron beam resist is coated on the insulating film, and further, a chemical amplification type positive electron beam resist is applied. And (b) irradiating the chemically amplified positive type electron beam resist with an electron beam based on electron beam writing pattern data corresponding to the inside of the actual pattern of the contact hole, (c) ) Baking the chemically amplified positive electron beam resist to accelerate the resist dissolution reaction using the acid generated by the irradiation of the electron beam as a catalyst, (d) the chemically amplified positive electron beam resist, A step of forming a resist pattern by developing and removing the irradiated portion, (e) the insulating film using the resist pattern as a mask By etching,
Step of forming contact holes for wiring connection.

(14). In the method for manufacturing a semiconductor integrated circuit device of the present invention, wiring is performed by using a resist pattern obtained by irradiating a chemically amplified electron beam resist deposited on a semiconductor wafer with an electron beam as a mask. The following steps when forming
It has (a) to (e).

(A) A conductive film is deposited on a semiconductor wafer on which an integrated circuit element is formed, a chemically amplified negative electron beam resist is applied to the conductive film, and the chemically amplified negative electron beam resist is further coated. Depositing a conductive polymer, (b) irradiating an electron beam to the chemically amplified negative type electron beam resist based on electron beam writing pattern data corresponding to the inside of the actual pattern of the wiring, (c) By baking the chemically amplified negative electron beam resist, accelerating the resist crosslinking reaction using the acid generated by the irradiation of the electron beam as a catalyst, (d) developing the chemically amplified negative electron beam resist. A step of forming a resist pattern by removing the non-irradiated portion by (e) etching the conductive film using the resist pattern as a mask It makes the process of forming the wiring.

(15). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the electron beam resist deposited on the semiconductor wafer is irradiated with an electron beam, and the resist dissolution rate of the developer in the irradiated portion and the non-irradiated portion is adjusted. A plurality of electron beam exposure processes for forming a resist pattern by utilizing the difference are provided, a positive type electron beam resist is used in a part of the plurality of electron beam exposure processes, and a negative type electron beam resist is used in another part of the processes. A beam resist is used.

(16). In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the manufacturing method according to (15) above, a conductive polymer is deposited on the surface of the electron beam resist prior to the irradiation with the electron beam. To do.

(17). In the method of manufacturing a semiconductor integrated circuit device of the present invention, in the manufacturing method of (15), the electron beam resist is irradiated with an electron beam formed into a rectangular or graphic shape.

[0030]

According to the above-mentioned means, the writing time can be shortened by selectively using the positive type electron beam resist and the negative type electron beam resist according to the size of the area inside the actual pattern of the integrated circuit.

According to the above-mentioned means, by depositing the conductive polymer on the surface of the chemically amplified electron beam resist, it is possible to prevent the resist from being charged up at the time of writing the electron beam, and at the same time, the chemically amplified electron beam resist. The resist can be stabilized.

According to the above-mentioned means, the light projection exposure method using the photomask is used in at least one step of the integrated circuit element forming step, and the electron beam exposure method is used in the subsequent wiring forming step, so that the exposure time is increased. It is possible to achieve both shortening of time and improvement of drawing accuracy.

[0033]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a flow chart showing a part of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

First, an insulating film 20 such as a silicon oxide film is formed on the main surface of the semiconductor wafer 2 on which a predetermined integrated circuit is formed.
Is deposited, and a chemically amplified positive type electron beam resist 21 is applied on the insulating film 20. This positive type electron beam resist 21 includes, for example, a cresol novolac resin as a base resin, a tetrahydropyranylated polyvinylphenol as a dissolution inhibitor (a portion corresponding to a hydroxyl group is protected with a pyranyl group to improve alkali resistance), an acid. It is composed of a generator, tri (methanesulfonyloxy) benzene, a sensitizer, and methyl cellosolve acetate (solvent). The positive electron beam resist 21
In order to improve the adhesion with the insulating film 20, a baking process (pre-baking or post-baking) is performed before and after the exposure.

Next, the positive type electron beam resist 21 is formed.
The conductive polymer 22 is applied on the top surface of the substrate. This conductive polymer 22 is, for example, "Espacer 100" manufactured by Showa Denko.
And so on.

The conductive polymer 22 is applied for the purpose of preventing charge-up of the semiconductor wafer 2 at the time of exposure and reducing and stabilizing the change with time of the positive type electron beam resist 21 after exposure. If the positive electron beam resist 21 is left after exposure without using the conductive polymer 22,
It is recognized that the acid generated by the electron beam irradiation is gradually deactivated, and the dimensional accuracy of the resist pattern deteriorates accordingly.

Next, the semiconductor wafer 2 is positioned on the XY stage of the electron beam drawing apparatus.

FIG. 2 is an overall configuration diagram of an electron beam drawing apparatus used in this embodiment, FIG. 3 is a diagram showing an example of a method for holding a semiconductor wafer by an electrostatic chuck of this electron beam drawing apparatus, and FIG. FIG. 3 is an explanatory diagram showing an example of a configuration of a position variation measuring mechanism of this electron beam drawing apparatus.

The electron beam drawing apparatus 1 combines the movement of the semiconductor wafer 2 which is the sample, the deflection scanning of the electron beam 7 which is the charged and focused beam, and the turning on and off of the electron beam 7, and the XY stage 15 is continuously connected. Is a device for drawing a predetermined integrated circuit pattern on an electron beam resist on a semiconductor wafer 2 while moving the device, and is roughly divided into a data storage unit 3, a drawing control unit 4, a control I / O unit 5, and an EB drawing unit 6. To be done.

An electron beam source 8 is provided above the XY stage 15. An electron beam optical system 6a including a first deflector 11, a second deflector 14, an electron lens 13 and the like is provided between the electron beam source 8 and the XY stage 15, and the electron beam 7 is directed toward the semiconductor wafer 2. Is irradiated.

The XY stage 15 is a position for measuring the positional fluctuation of the electrostatic chuck (see FIG. 3) which is a means for holding the semiconductor wafer 2 and the reference mark 43 (see FIG. 4) formed on the semiconductor wafer 2. A fluctuation measuring mechanism (see FIG. 4) is provided. The position of the reference mark 43 formed on the semiconductor wafer 2 is detected by the laser measurement for detecting the position of the XY stage 15 and the mark detection system 41 for detecting the reflection signal of the light or the electron beam 7 with which the reference mark 43 is irradiated. With the long portion 16 (see FIG. 2).

The data storage unit 3 is a component unit for storing drawing data, and includes a data storage unit 3a and a data transfer unit 3b. The data storage unit 3a is composed of, for example, a magnetic disk, and has therein control data for controlling drawing processing and an integrated circuit pattern (corresponding to a pattern corresponding to the inside of the actual pattern of the connection hole and an inside of the actual pattern of the wiring). Data such as a pattern) is stored.

The drawing control unit 4 is a component for controlling the overall operation of the electron beam drawing apparatus 1, and for example, a high speed control computer is used.

The control I / O unit 5 is a component for inputting / outputting the control signal transmitted from the drawing control unit 4 or the like to the EB drawing unit 6, and includes a buffer memory 5a, a computing unit 5b, and a control signal generating unit. 5c, blanking electrode controller 5d, first deflection controller 5e, movement controller 5f, second deflection controller 5g,
The detector 5h, the signal processor 5i, the stage controller 5j, the loader controller 5k, and the vacuum controller 5l are provided.

The position coordinates of the reference mark 43 on the semiconductor wafer 2 are detected by scanning the surface of the semiconductor wafer 2 with the electron beam 7 or light prior to writing, and the XY stage 15 is moved.
Information is obtained by performing laser length measurement of the position of 1 by the laser length measuring unit 16, and the coordinates are converted into, for example, the reference coordinate system of the electron beam drawing apparatus 1 and stored in the second buffer memory of the calculation unit 5b. Then, in correspondence with the drawing of individual graphic information, the second
The deflection controller 5g is controlled. Further, the height of the semiconductor wafer 2 is detected by irradiating the surface of the semiconductor wafer 2 with light obliquely,
This is done by detecting the reflected light.

The calculation unit 5b, based on the data transmitted from the buffer memory 5a, for example, drawing data, reference mark position detection data, stage position data, or the like.
Blanking control signal data for controlling on / off of the electron beam 7 is created, first deflection control signal data for selecting a predetermined pattern formed on the second mask 12 is created, and second blanking signal of the second mask 12 is created. The control signal data for controlling the movement amount is created, or the second deflection control signal data for controlling the irradiation area and the irradiation position of the electron beam 7 on the semiconductor wafer 2 is created.

The EB drawing unit 6 is composed of an electron beam optical system 6a which is a charged and focused beam irradiation means and an XY stage system 6b which is an XY stage means. The electron beam optical system 6a includes an electron beam source 8, a first mask 9, a blanking electrode 10, a first deflector 11, a second mask 12,
An electron lens 13 and a second deflector 14 are provided, and the electron beam 7 emitted from the electron beam source 8 is applied to a predetermined position on the semiconductor wafer 2 on the XY stage 15 via these components.

The blanking electrode 10 is a component for controlling on / off of the electron beam 7. Electron beam 7
Is controlled based on beam irradiation parameter data or the like transmitted from the calculation unit 5b to the blanking electrode 10 via the control signal generation unit 5c and the blanking electrode control unit 5d.

The first deflector 11 is a component for irradiating the electron beam 7 transmitted through the electron lens 13 to a predetermined position on the second mask 12. The selection of the predetermined pattern of the second mask 12 is controlled based on the graphic selection parameter data transmitted from the calculation unit 5b to the first deflector 11 via the control signal generation unit 5c and the first deflection control unit 5e. It

The electron lens 13 focuses, for example, the electron beam 7, corrects the rotation of the electron beam 7 in the direction around the optical axis, reduces the cross-sectional shape of the electron beam 7, and collects electrons from the semiconductor wafer 2. It is a component for focusing the beam 7.

The second deflector 14 is a component for irradiating the electron beam 7 transmitted through the electron lens 13 to a predetermined position on the semiconductor wafer 2. The irradiation position of the electron beam 7 on the semiconductor wafer 2 is determined by the calculation unit 5b to the control signal generation unit 5.
It is controlled based on the irradiation information parameter data (the data in which the irradiation area and the irradiation position coordinates are written) transmitted to the second deflector 14 via the c and the second deflection control unit 5g.

The second deflector 14 is composed of an electrode deflector for large angle deflection and an electrostatic deflector for two stages of small angle and high speed deflection. That is, the irradiation position of the electron beam 7 on the semiconductor wafer 2 is determined by an electromagnetic deflector for large-angle deflection of about 5 mm square and an electrostatic deflector for two-stage high-speed deflection of about 500 μm and 80 μm square, for example. It is controlled by adjusting the
It is configured to realize high-speed electron beam deflection.

The first mask 9 and the second mask 12 are provided so as to be finely movable, and are placed on a mask moving stage (not shown). The movement of the second mask 12 is controlled based on the movement control parameter data or the like transmitted from the calculation unit 5b to the drive unit via the control signal generation unit 5c and the movement control unit 5f. The predetermined pattern is set so as to fall within the deflection area of the electron beam 7. The movement of the first mask 9 is also controlled in the same manner.

As shown in FIGS. 3A and 3B, the semiconductor wafer 2 is fixed on the electrostatic pallet 32 of the electrostatic chuck via the positioning roller 35. Although the flatness of the semiconductor wafer 2 gradually decreases as the manufacturing process progresses, the electrostatic chuck can fix the semiconductor wafer 2 having a warp of about 100 μm evenly.

Semiconductor wafer 2 fixed to the electrostatic chuck
Is energized through the knife edge contact pin 34 that contacts the side surface. The tip of a soft contact pin 33, which is a ground terminal, is in contact with the conductive polymer 22 applied to the surface of the semiconductor wafer 2 in order to make the surface potential of the conductive polymer 22 a ground potential. This soft contact pin 33
The surface of the tip is extremely lightly contacted so as not to damage or penetrate the conductive polymer 22. A small part of the electric charge generated by the irradiation of the electron beam is grounded to the outside through the soft contact pin 33. By doing so, it is possible to reliably prevent the irradiation position of the electron beam from moving due to the electric charge.

As shown in FIG. 4, the electron beam drawing apparatus 1
The position variation measuring mechanism is roughly divided into a mark detecting system 41, which is a mark detecting means for detecting the reference mark 43 on the semiconductor wafer 2, and a data comparing system 42, which compares the two pieces of information received. .

The mark detection system 41 is a light source 41 that emits light.
a (which may be the electron beam 7 emitted from the electron beam source 8 shown in FIG. 1), a lens 41b for converging or deflecting the light emitted from the light source 41a, and a sensor 41c for detecting this light. Composed of. The data comparison system 42 is composed of a pattern memory 42a for storing the information taken in via the sensor 41c and a comparator 42b for comparing the information taken in later with the information taken in earlier. .

A method of measuring the position variation of the sample by the position variation measuring mechanism will be described. First, the semiconductor wafer 2
Is mounted on the XY stage 15, and the reference mark 43 formed on the surface thereof is irradiated with the light emitted from the light source 41a.
The reflected light is detected by the sensor 41c, and this pattern information is stored in the pattern memory 42a.

Thereafter, the XY stage 15 is temporarily moved at a predetermined speed (preferably, a speed equal to or higher than the speed at which the XY stage 15 is moved at the time of drawing) and then returned to the original position again. And the same reference mark 4
3 is detected again, and the information in the pattern memory 42a taken in before the temporary movement is compared with the information taken in after the temporary movement by the comparator 42b, so that the relative position of the semiconductor wafer 2 with respect to the XY stage 15 changes. Determine if the minutes are less than or equal to the reference value.

Reference mark 4 formed on semiconductor wafer 2
If the measurement reproducibility of 3 is less than or equal to the reference value, the position of the reference mark 43 is detected using the electron beam 7. This allows
The integrated circuit pattern formed on the semiconductor wafer 2 can be aligned for each chip. On the other hand, when the value is equal to or larger than the reference value, an error is displayed and the semiconductor wafer 2 is unloaded from the electrostatic chuck or the electrostatic chuck is operated again to detect the position of the reference mark 43 and the XY stage 15.
And move again to determine again.

After the semiconductor wafer 2 is accurately positioned on the XY stage 15 in this way, the drawing data stored in the data storage unit 3a of the data storage unit 3 (the drawing data corresponding to the inside of the actual pattern of the connection hole) is stored. ), The surface of the semiconductor wafer 2 is irradiated with the electron beam 7. By the irradiation of the electron beam 7, the acid generator in the positive type electron beam resist 21 is hydrolyzed to generate an acid.

Next, when the positive electron beam resist 21 is baked, the acid acts as a catalyst on the dissolution inhibitor,
The deprotection (depyranylation) reaction proceeds. Then, the substance after the deprotection reaction is changed to polyvinylphenol, and the resist dissolution rate in the electron beam irradiation portion is increased. Depending on the combination of the positive-type electron beam resist 21 and the conductive polymer 22, an unnecessary reaction may occur at the interface between the two during baking, but in such a case, the conductive polymer 22 is preceded by the baking. May be removed by washing with water and then baked.

Next, prior to development, the semiconductor wafer 2 is washed with water to remove the conductive polymer 22 on the surface, and then the positive electron beam resist 21 is developed with an organic solvent to form a resist pattern.

Next, the insulating film 20 is etched using this resist pattern as a mask to form connection holes 23 for wiring connection on the integrated circuit element, and then the positive electron beam resist 21 is removed from the surface of the semiconductor wafer 2. To do.

FIG. 5 is a flowchart showing another part of the method of manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention in the order of steps.

First, a metal film 24 such as Al is deposited on the main surface of the semiconductor wafer 2 on which a predetermined integrated circuit is formed, and a chemical amplification type negative electron beam resist 25 is formed on the metal film 24. Apply. The negative electron beam resist 25 is composed of, for example, cresol novolac resin as a base resin, melamine as a cross-linking agent, tris (bromoacetyl) benzene as an acid generator, cyclohexanone (solvent), and the like. The negative electron beam resist 25 is subjected to a baking treatment (pre-baking or post-baking) before and after exposure in order to improve the adhesion with the metal film 24.

Next, the negative electron beam resist 25 is used.
The above-mentioned conductive polymer 22 is applied onto the above. The conductive polymer 22 is applied for the purpose of preventing charge-up of the semiconductor wafer 2 at the time of exposure and reducing and stabilizing the change with time of the positive electron beam resist 21 after exposure. When the negative type electron beam resist 25 is exposed without exposure to the conductive polymer 22, the acid generated by the electron beam irradiation is assumed to be gradually deactivated, and the dimensional accuracy of the resist pattern is accordingly increased. Deteriorates.

Next, the semiconductor wafer 2 is positioned on the XY stage 15 of the electron beam drawing apparatus 1 shown in FIG. 2, and the drawing data stored in the data storage section 3a of the data storage section 3 (actual wiring pattern) is stored. The surface of the semiconductor wafer 2 is irradiated with the electron beam 7 according to the drawing data corresponding to the inside). By the irradiation of the electron beam 7, the acid generator in the negative electron beam resist 25 is hydrolyzed to generate an acid.

Next, the negative type electron beam resist 25 is baked to increase the resist dissolution rate in the unirradiated portion of the electron beam, the semiconductor wafer 2 is washed with water to remove the conductive polymer 22 on the surface, and then the organic A resist pattern is formed by developing the negative electron beam resist 25 with a solvent. Depending on the combination of the negative type electron beam resist 25 and the conductive polymer 22, an unnecessary reaction may occur at the interface between the two during baking, but in such a case, the conductive polymer 22 is preceded by the baking.
May be removed by washing with water and then baked.

Next, the metal film 24 is etched by using this resist pattern as a mask to form the wiring 24A.
After forming, the negative electron beam resist 25 is removed from the surface of the semiconductor wafer 2.

As described above, in the present embodiment, the positive electron beam resist 21 and the negative electron beam resist 25 are selectively used in the step of forming the connection hole 23 and the step of forming the wiring 24A, so that the electron beam drawing time is shortened. can do.

Further, by forming the conductive polymer 22 on the positive type electron beam resist 21 and the negative type electron beam resist 25, the conductive polymer 22 prevents the charge up of the resist at the time of electron beam drawing, and at the same time the resist is resisted. Since it functions so as to stabilize, the drawing accuracy can be improved.

Next, the manufacturing method of this embodiment applied to the manufacturing process of the ASIC bipolar LSI will be described with reference to FIGS. 6 and 7.

FIG. 6 is a sectional view of an essential part of a semiconductor substrate showing an essential part of the bipolar LSI, and FIG.
FIG. 3 is a schematic plan view showing the layout of second to fourth layer metal wirings of FIG. Note that the semiconductor element is not shown in FIG. 7.

As shown in FIG. 6, an n-type buried layer 101 is provided on a part of a semiconductor substrate 100 made of, for example, p-type single crystal silicon. In addition, the semiconductor substrate 10
On 0, an n-type epitaxial layer 102 is provided. A field insulating film 103 for element isolation made of a silicon oxide film is formed on a part of the epitaxial layer 102.
Are provided, thereby separating between the semiconductor elements and for each characteristic portion in the semiconductor element.

A p-type channel stopper region 104 is provided below the field insulating film 103 so as to be embedded in the semiconductor substrate 100. Further, in the portion of the epitaxial layer 102 surrounded by the field insulating film 103, the p-type intrinsic base region 105, the p-type graft base region 106, and the n-type collector extraction region 108.
Is provided. Further, in the intrinsic base region 105, an n-type emitter region 107 is provided. Then, the emitter region 107 and the intrinsic base region 10
5. Each epitaxial layer 102 below the intrinsic base region 105 and the collector region formed of the buried layer 101 form an npn-type bipolar transistor.

In each step until the bipolar transistor is formed, a light projection exposure method using a photomask is used. After that, the electron beam exposure method of the present embodiment is used in the step of forming wiring on the bipolar transistor and the step of forming a connection hole for connecting the bipolar transistor and the wiring or the wiring in the upper and lower layers.

By performing the transistor formation by the light projection exposure method using a photomask, the number of wafers processed per unit time can be increased as compared with the electron beam exposure method, so that the exposure cost can be reduced. it can.
On the other hand, in the subsequent wiring formation, the electron beam exposure method is more suitable for the purpose of manufacturing an integrated circuit in a short period of time according to the user's request.

As shown in FIG. 6, the field insulating film 10 is formed.
3 to the insulating film 109 continuously provided on the graft base region 1
06, emitter region 107 and collector extraction region 1
08 corresponding to each of the connection holes 109a, 109b, 10
9c is provided. Also, the graft base region 10
A base extraction electrode 110 made of a polycrystalline silicon film is connected to 6 through a connection hole 109a. Further, an emitter electrode 111 made of a polycrystalline silicon film is provided on the emitter region 107.

On the upper part of the field insulating film 103,
Insulating films 112 and 113 made of a silicon oxide film are provided. These insulating films 112 and 113 are provided with connection holes 114, 116, corresponding to the base extraction electrode 110, the emitter electrode 111, and the collector extraction region 108, respectively.
118 is provided. These connection holes 114, 11
6, 118 are opened by the method shown in FIG. 1, that is, by etching using a positive electron beam resist as a mask.

By opening these connection holes 114, 116 and 118 by an electron beam exposure method, for example, AS
It is possible to form efficiently even in the case where the opening location is different among the types, such as a semiconductor integrated circuit for IC. When the locations where the connection holes 114, 116, and 118 are opened are the same for different types, a light projection exposure method using a photomask may be used as in the transistor forming step.

A first-layer metal wiring 115 made of, for example, an Al film is connected to the base extraction electrode 110 through a connection hole 114. Further, the first-layer metal wiring 117 is connected to the emitter electrode 111 through the connection hole 116. Further, a first layer metal wiring 119 is connected to the collector extraction region 108 through a connection hole 118 and the connection hole 109c.

The first layer metal wirings 115, 117, 1
19 is formed by the method shown in FIG. 5, that is, etching using a negative electron beam resist as a mask.
In this wiring forming process, the metal film for the first layer wiring is present under the negative type electron beam resist, so that the influence of charge-up during electron beam drawing is small. Therefore, the conductive polymer on the negative type electron beam resist mainly functions as a stabilizing film of the negative type electron beam resist.

The first layer metal wirings 115, 117, 1
An interlayer insulating film 1 in which a silicon nitride film, an SOG (spin on glass) film, and a silicon oxide film are laminated on the upper layer 19
20 are provided. The SOG film is deposited by spin coating, and the silicon nitride film and the silicon oxide film are plasma CV.
It is deposited by the D method.

On the upper layer of the interlayer insulating film 120, a second layer metal wiring 82a made of, for example, an Al film is provided. As shown in FIG. 7, the second-layer metal wiring group 57 mainly extends along the Y-axis direction in the figure. The wirings 82a to 82f of the second-layer metal wiring group 57 have, for example, a pitch of 5 μm and a width of 3.5 μm. These wirings 82a-
82f is formed by etching using a negative electron beam resist as a mask.

The second layer metal wiring 82a is connected to the first layer metal wiring 119 through a connection hole 122 formed in the interlayer insulating film 120. This connection hole 122
Has a step-like stepped surface, this shape allows the second-layer metal wiring 82a inside the connection hole 122 to be formed.
The step coverage of can be improved. This connection hole 122 is opened by etching using a positive electron beam resist as a mask.

In the upper layer of the second layer metal wiring 82a,
An interlayer insulating film 123 similar to the interlayer insulating film 120 is provided. The upper layer of the inter-layer insulation film 123 may be made of, for example, Al.
Third layer metal wirings 83a, 83b, 83c made of a film are provided. As shown in FIG. 7, the third-layer metal wiring group 59 mainly extends along the X-axis direction in the figure. The wirings 83a to 83h of the third layer metal wiring group 59 are
It has a width of 3.5 μm with a pitch of 5 μm and is arranged according to the need of interconnection. The wiring 83X is a spare wiring provided every 5 pitches. These wirings 83a to 83
f and 83X are formed by etching using a negative electron beam resist as a mask.

The third layer metal wiring 83a is connected to the second layer metal wiring 82a through a connection hole 125 formed in the interlayer insulating film 123. This connection hole 125
Are opened by etching using a positive electron beam resist as a mask.

The third layer metal wirings 83a, 83b, 8
An interlayer insulating film 126 similar to the interlayer insulating films 120 and 123 is provided on the upper layer of 3c. Interlayer insulating film 12
Fourth layer metal wirings 81a, 81b, 81c made of, for example, an Al film are provided in the upper layer of layer 6.

As shown in FIG. 7, the fourth-layer metal wiring group 6
Reference numeral 1 mainly extends along the Y-axis direction in the figure. In the fourth layer metal wiring group 61, the wirings 81a to 81g are
Power supply wiring or reference voltage wiring each having a width of 50 to 200 μm (in the case of an ECL circuit, VESL = -4V, VEE =-
3V, VTT = -2V, VCC1, VCC2, VCC3 = 0V). The thickness of the wirings 81a to 81g is 2 μm, and the wiring space between them is 2 μm. The wirings 84Y are preliminary wirings each having a width of 10 μm. These wiring 81a
81 g and 84Y are formed by etching using a negative electron beam resist as a mask.

The fourth layer metal wirings 81a, 81b, 8
An insulating film 128 is provided on the upper layer of 1c for the purpose of surface flattening. The insulating film 128 is formed by, for example, a bias sputtering method of a silicon oxide film, a combination of plasma CVD and sputter etching, or the like. Alternatively, PSG (Phospho-Silicate Glass) film formed by a combination of atmospheric pressure CVD and sputter etching, BS
G (Boro-Silicate Glass) film, BPSG (Boro-Phospho
It is also possible to use a silicate glass film such as a -Silicate Glass) film. The insulating film 128 fills the groove between the fourth-layer metal wirings 81a, 81b, 81c, and the surface of the insulating film 128 becomes substantially flat.

Plasma C is formed on the insulating film 128.
A silicon nitride film 129 deposited by the VD method is provided, and a silicon oxide film 130 deposited by the plasma CVD method is further provided on the silicon nitride film 129. Then, the silicon nitride film 129 and the silicon oxide film 13 are formed.
The passivation film 131 that protects the surface of the semiconductor substrate 100 is configured by the laminated film of 0.

As described above, since the surface of the insulating film 128 is flattened, the film thickness and film quality of the silicon nitride film 129 are relatively uniform, and passivation with high moisture resistance in which water and the like hardly enter. It is the film 131. Therefore, as the LSI package, not only the hermetically sealed package but also the non-hermetically sealed package can be used.

Next, a twin well CMOS
The manufacturing method of this embodiment applied to the manufacturing process of the static RAM (SRAM) will be described with reference to FIGS.

FIG. 8 shows the n by the twin well process.
7 shows a well and p-well formation process. In the figure, 200 is a semiconductor substrate made of n ⁻ type silicon single crystal, 260n is an n type well, and 260p is a p type well.

FIG. 9 shows the subsequent gate forming process and the process of forming the source and drain of each MOSFET by ion implantation by self-alignment using the formed gate as a mask. In the figure, 261 is a field oxide film, 262n and 262p are gate oxide films, 263n and 263p are polycrystalline silicon gate electrodes, 264n and 264p are n-type and p-types, respectively.
The source and drain of the mold.

FIG. 10 shows an interlayer insulating film forming process, a second layer polycrystalline silicon wiring and a high resistance forming process. In the figure, 265 is an interlayer insulating film, 266 is a polycrystalline silicon wiring, and 266r is a polycrystalline silicon high resistance which serves as a load resistance of the SRAM memory cell.

FIG. 11 shows a flattening process and a contact hole forming process by spin-on-glass. In the figure, 267 is a spin-on-glass film, 268a is a connection hole with the semiconductor substrate 200, and 268b is a connection hole with the polycrystalline silicon wiring 266 and the upper layer.

FIG. 12 shows the first layer Al wiring forming process. In the figure, 269 is a first layer Al wiring.

FIG. 13 shows an interlayer insulating film forming process on the first layer Al wiring 269 and a second layer Al wiring forming process. In the figure, 270 is the first layer Al wiring 269.
The upper interlayer insulating film 271 is a second-layer Al wiring connected to the first-layer Al wiring 269 through a connection hole.

FIG. 14 shows a final passivation film forming process on the second layer Al wiring 271. In the figure, 272 is a final passivation film.

FIG. 15 is an exposure process flow chart showing the steps related to photolithography of the SRAM manufacturing process, that is, the exposure steps extracted and made into a flow. In the figure, the n-well photo step P1 is n
A step of forming a photoresist pattern on the silicon nitride film (on the semiconductor substrate) so as to cover a portion other than the portion to be the mold well 260n, a field photo step P
Step 2 is a step of depositing and patterning a photoresist film on the silicon nitride film so as to cover the active regions of the n-channel and p-channel.

In the p-well photo step P3, in order to form the channel stopper region of the p-type well 260p,
In the step of patterning the photoresist film covering the n-type well 260n, the gate / photo step P4 is to pattern the photoresist film on the polycrystalline silicon layer deposited on the entire surface to pattern the gate electrodes 263n and 263p. It is a process to do.

The n-channel photo step P6 is a step of patterning a photoresist film on the p-channel side for ion-implanting n-type impurities using the gate electrode 263n as a mask on the n-channel side, and the p-channel photo step P6.
On the contrary, it is a step of patterning a photoresist film on the n-channel side to ion-implant p-type impurities using the gate electrode 263p as a mask on the p-channel side.

In the polycrystalline silicon photo step P7, the polycrystalline silicon wiring 266 or the polycrystalline silicon high resistance 26 is used.
The step of patterning a photoresist film on the polycrystalline silicon layer deposited on the entire surface in order to pattern the second layer polycrystalline silicon film to be 6r (FIG. 10), the R / photo step P8, is a step of increasing the polycrystalline silicon film. Resistor 266r (Fig. 1
0) This is a step of patterning the photoresist film serving as a mask for injecting impurity ions into other portions with the photoresist film covering the upper surface by a negative process.

In the contact photo step P9, the semiconductor substrate 200, the sources and drains 264n and 264p, the first-layer polycrystalline silicon layer, the second-layer polycrystalline silicon layer, etc. and the first-layer Al wiring (Al-1) 269 are formed. Process for depositing and patterning a photoresist pattern for forming connection holes 268a, 268b (FIG. 11) for making contact with each other by a positive process, Al-1 photo process P10 is the first layer Al wiring. 269 is a photoresist patterning process for patterning 269.

The through hole photo step P11 is a step of forming a photoresist pattern for opening a connection hole hole for connecting the first layer Al wiring 269 and the second layer Al wiring 271, Al- 2. Photo process P1
2 is a photoresist patterning process for patterning the second layer Al wiring 271, and a bonding pad photo step P13 is a pad for forming an opening of about 100 μm square corresponding to the bonding pad in the final passivation film 272. It is a step of depositing a photoresist film on the final passivation film 272 other than the above.

Of these exposure processes, n well
In the photo process P1, the n-channel photo process P5, the p-channel photo process P6, and the bonding pad photo process P13, the minimum dimension is relatively large, so it is generally unnecessary to use electron beam exposure, but in other photo processes. The electron beam exposure of the present invention is used.

Particularly, in the gate photo step P4, the gate electrode 2 is formed by using the chemical amplification type negative electron beam resist.
63n and 263p are formed, and a source and a drain 264n and 264 are formed by using a chemically amplified positive type electron beam resist.
By forming connection holes 268a and 268b for making a contact between p and the first layer Al wiring 269, the gate lengths of the gate electrodes 263n and 263p and the connection holes 26 are formed.
The aperture diameters of 8a and 268b can be made finer than the wavelength of the exposure light used in the light exposure method (for example, about 0.3 μm).

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above-mentioned embodiment, the case where the present invention is applied to the wiring forming step and the connection hole forming step has been described, but the present invention is not limited to this, and it can be applied to the forming step of the integrated circuit element.

[0113]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

When a resist pattern obtained by irradiating a chemically amplified electron beam resist formed on a semiconductor wafer with an electron beam is used as a mask to form an integrated circuit pattern, chemical amplification is performed depending on the manufacturing process of the integrated circuit. The writing time can be shortened by properly using the system positive type electron beam resist and the chemically amplified negative type electron beam resist. Therefore, high throughput electron beam direct writing can be realized by using the chemically amplified type electron beam resist. be able to.

By depositing a conductive polymer on the chemically amplified electron beam resist, resist charge-up at the time of electron beam writing is prevented, and at the same time,
Since the chemically amplified electron beam resist is stabilized, highly accurate electron beam direct writing can be realized using the chemically amplified electron beam resist.

[Brief description of drawings]

FIG. 1 is a flowchart showing a part of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in process order.

FIG. 2 is an overall configuration diagram of an electron beam drawing apparatus used in this embodiment.

3A and 3B are explanatory views showing an example of a method of holding a semiconductor wafer by an electrostatic chuck of the electron beam drawing apparatus shown in FIG. 2, in which FIG. 3A is a perspective view of the electrostatic chuck and FIG. is there.

4 is an explanatory diagram showing an example of a configuration of a position variation measuring mechanism of the electron beam drawing apparatus shown in FIG.

FIG. 5 is a flowchart showing another part of the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention in the order of steps.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

7 is a second through fourth layers of the semiconductor integrated circuit device shown in FIG.
It is a schematic plan view which shows the layout of a layer metal wiring.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 15 is a flowchart showing a part (photoresist process) of a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention in process order.

[Explanation of symbols]

 1 Electron Beam Drawing Apparatus 2 Semiconductor Wafer 3 Data Storage Section 3a Data Storage Section 3b Data Transfer Section 4 Drawing Control Section 5 Control I / O Section 5a Buffer Memory 5b Computing Section 5c Control Signal Generation Section 5d Blanking Electrode Control Section 5e First Deflection control section 5f Movement control section 5g Second deflection control section 5h Detection section 5i Signal processing section 5j Stage control section 5k Loader control section 5l Vacuum control section 6 EB drawing section 6a Electron beam optical system (charge focused beam irradiation means) 6b XY Stage system (XY stage means) 7 Electron beam (charge focusing beam) 8 Electron beam source 9 First mask 10 Blanking electrode 11 First deflector 12 Second mask 13 Electron lens 14 Second deflector 15 XY stage 16 Laser measurement Long part 20 Insulating film 21 Positive type electron beam resist 22 Conductive polymer 23 Connection hole 24 Metal film 24A Wiring 25 Negative electron beam resist 32 Electrostatic pallet 33 Soft contact pin 34 Knife edge contact pin 35 Positioning roller 41 Mark detection system (mark detection means) 41a Light source 41b Lens 41c Sensor 42 Data comparison system 42a Pattern Memory 42b Comparator 43 Reference mark 57 Second layer metal wiring group 59 Third layer metal wiring group 61 Fourth layer metal wiring group 81a to 81g Fourth layer metal wiring 82a to 82f Second layer metal wiring 83a to 83h Third layer Metal wiring 83X wiring 84Y wiring 100 Semiconductor substrate 101 Buried layer 102 Epitaxial layer 103 Field insulating film 104 Channel stopper region 105 Intrinsic base region 106 Graft base region 107 Emitter region 108 Core Lead-out region 109 Insulating film 109a to 109c Connection hole 110 Base extraction electrode 111 Emitter electrode 112 Insulating film 113 Insulating film 114 Connection hole 115 First layer metal wiring 116 Connection hole 117 First layer metal wiring 118 Connection hole 119 First layer metal Wiring 120 Interlayer insulation film 122 Connection hole 123 Interlayer insulation film 125 Connection hole 126 Interlayer insulation film 128 Insulation film 129 Silicon nitride film 130 Silicon oxide film 131 Passivation film 200 Semiconductor substrate 260n n-type well 260p p-type well 261 Field oxide film 262n gate Oxide film 262p Gate oxide film 263n Gate electrode 263p Gate electrode 264n Source, drain 264p Source, drain 265 Interlayer insulating film 266 Polycrystalline silicon wiring 266r Polycrystalline silicon High resistance 267 spin-on-glass film 268a connecting hole 268b connecting hole 269 first layer Al wirings 270 interlayer insulating film 271 second layer Al wiring 272 final passivation film

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location G03F 7/26

Claims (17)

[Claims] 1. An electron for irradiating a chemical amplification type electron beam resist deposited on a semiconductor wafer with an electron beam and forming a resist pattern by utilizing a difference in resist dissolution rate between a irradiated portion and a non-irradiated portion of a developing solution. A method of manufacturing a semiconductor integrated circuit device comprising a plurality of beam exposure steps, wherein a positive type electron beam resist is used in a part of the plurality of electron beam exposure steps, and a negative type electron beam resist is used in another part of the steps. A method for manufacturing a semiconductor integrated circuit device, characterized by using a beam resist. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a conductive polymer is deposited on the surface of the chemically amplified electron beam resist prior to irradiation with the electron beam. And method for manufacturing a semiconductor integrated circuit device. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the electron beam is irradiated based on electron beam drawing pattern data corresponding to the inside of the actual pattern of the integrated circuit. Manufacturing method of semiconductor integrated circuit device. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the method is applied to a semiconductor integrated circuit device for a specific purpose. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein when the chemical amplification type electron beam resist is irradiated with an electron beam, a ground terminal is brought into contact with the conductive polymer to cause the conductivity A method for manufacturing a semiconductor integrated circuit device, wherein the surface potential of the conductive polymer is set to ground potential. 6. A method of manufacturing a semiconductor integrated circuit device, comprising: a plurality of exposure steps of exposing a resist deposited on a semiconductor wafer to form a resist pattern, the steps being a part of the plurality of exposure steps. Is a method for forming a resist pattern by irradiating a chemically amplified electron beam resist with an electron beam. In some other steps, the resist pattern is formed by a light projection exposure method using a photomask. Method of manufacturing circuit device. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein in the step of forming the integrated circuit element, a resist pattern is formed by the light projection exposure method in at least one step of the steps. A method of manufacturing a semiconductor integrated circuit device, wherein a resist pattern is formed by an electron beam exposure method using the chemically amplified electron beam resist in the step of forming a wiring on the element. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein a chemically amplified positive electron beam resist is used in a part of the step of forming the integrated circuit element, and chemically amplified in another part. A method for manufacturing a semiconductor integrated circuit device, characterized in that a negative type electron beam resist is used. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 6, comprising a plurality of electron beam exposure steps of irradiating the chemically amplified electron beam resist with an electron beam to form a resist pattern. A method of manufacturing a semiconductor integrated circuit device, wherein a positive electron beam resist is used in a part of a plurality of electron beam exposure steps, and a negative electron beam resist is used in another part of the steps. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the minimum dimension of the resist pattern formed by irradiating the chemically amplified electron beam resist with an electron beam is the light projection exposure method. A method of manufacturing a semiconductor integrated circuit device, wherein the wavelength of the exposure light is equal to or less than the wavelength of the exposure light used. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein a chemically amplified positive type electron beam resist is used in a part of the step of forming wiring on the integrated circuit element, and another method is used. A method of manufacturing a semiconductor integrated circuit device, characterized in that a chemically amplified negative type electron beam resist is used in part. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein a gate electrode of a MISFET is formed using the chemically amplified negative electron beam resist, and the chemically amplified positive electron beam resist is used. Using the above M
A method of manufacturing a semiconductor integrated circuit device, comprising forming a through hole connecting an ISFET and a wiring formed on the ISFET. 13. A step of forming a contact hole for wiring connection by using a resist pattern obtained by irradiating a chemically amplified electron beam resist deposited on a semiconductor wafer with an electron beam as a mask, A method of manufacturing a semiconductor integrated circuit device, comprising: a) to (e). (a) An insulating film is deposited on a semiconductor wafer on which an integrated circuit element is formed, a chemically amplified positive electron beam resist is applied on the insulating film, and a conductive film is further formed on the chemically amplified positive electron beam resist. A step of depositing a polymer, (b) a step of irradiating the chemically amplified positive type electron beam resist with an electron beam based on electron beam writing pattern data corresponding to the inside of the actual pattern of the contact hole, (c)
By baking the chemically amplified positive electron beam resist, accelerating the resist dissolution reaction using the acid generated by the irradiation of the electron beam as a catalyst, (d)
A step of forming a resist pattern by developing the chemically amplified positive type electron beam resist to remove the irradiated portion, and (e) etching the insulating film using the resist pattern as a mask to form a wiring. A step of forming a contact hole for connection. 14. When forming wiring by using a resist pattern obtained by irradiating a chemical amplification type electron beam resist deposited on a semiconductor wafer with an electron beam as a mask, the following steps (a) to (e) are performed. ) Are provided. The manufacturing method of the semiconductor integrated circuit device characterized by the above-mentioned. (a) A conductive film is deposited on a semiconductor wafer on which an integrated circuit element is formed, a chemically amplified negative electron beam resist is applied to the conductive film, and a conductive polymer is further coated on the chemically amplified negative electron beam resist. And (b) irradiating the chemical amplification system negative type electron beam resist with an electron beam based on the electron beam drawing pattern data corresponding to the inside of the actual pattern of the wiring, (c) the chemical amplification system By baking the negative electron beam resist, accelerating the resist cross-linking reaction using the acid generated by the irradiation of the electron beam as a catalyst, (d) developing the chemical amplification type negative electron beam resist and irradiating it. A step of forming a resist pattern by removing a portion, (e)
A step of forming a wiring by etching the conductive film using the resist pattern as a mask. 15. An electron beam exposure step of irradiating an electron beam resist deposited on a semiconductor wafer with an electron beam, and forming a resist pattern by utilizing a difference in resist dissolution rate between a irradiated portion and a non-irradiated portion of a developing solution. A method of manufacturing a semiconductor integrated circuit device comprising a plurality of steps, wherein a positive type electron beam resist is used in a part of the plurality of electron beam exposure steps, and a negative type electron beam resist is used in another part of the steps. A method for manufacturing a semiconductor integrated circuit device, which is used. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein a conductive polymer is deposited on the surface of the electron beam resist prior to the irradiation of the electron beam. Manufacturing method of integrated circuit device. 17. The method for manufacturing a semiconductor integrated circuit device according to claim 15, wherein the electron beam resist is irradiated with an electron beam formed into a rectangular shape or a graphic shape. .