JPH09246155A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-precision alignment mark detecting technique which concerns the electron beam exposing technique for correcting a position to be exposed to an electron beam. SOLUTION: An alignment mark is composed of a mark construction 2 formed on a semiconductor substrate 1 and a flattening layer 3 covering the mark construction 2, and the surface of the flattening layer 3 is flattened by using flat film forming technique such as CMP(chemical mechanical polishing) technique or etchback, etc. By forming the flattening layer 3 protrusions, stepped parts, or inclination on the surface in the vicinity of the alignment mark are removed, and an error of a reflection electronic signal by reflected electrons of an electron beam emitted on the alignment mark is excluded. Consequently, it becomes possible to improve the precision of position detection and the precision of position correction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to selective etching and ion etching in the manufacture of a semiconductor integrated circuit device, a thin film integrated circuit device, a liquid crystal display device and the like having high integration density. The present invention relates to a technique effectively applied to alignment of an electron beam exposure technique used when forming a resist pattern as a driving shielding film.

[0002]

2. Description of the Related Art In the manufacture of semiconductor integrated circuit devices, miniaturization is being advanced with the aim of achieving higher speed semiconductor integrated circuit devices and higher performance semiconductor integrated circuit devices.

As a method of miniaturization, an electron beam drawing apparatus has been put into practical use in the lithographic technique in place of the reduction projection exposure apparatus.

The technique relating to electron beam drawing is, for example, 1
It is described in "Introduction to Ultrafine Machining", p26-p32, issued by Ohmsha Co., Ltd. on June 20, 989, and its outline is briefly described below.

The following three points are typical characteristics of electron beam drawing exposure.

(1) High resolution can be obtained.

(2) The electron as the exposure medium can be easily electronically controlled using a computer or the like.

(3) Highly accurate mask alignment is possible by observing the reflected electrons or secondary electrons from the object like an electron microscope.

Therefore, as an alignment method in an electron beam drawing apparatus, an alignment mark is formed on a layer to be processed, and the alignment mark is observed by observing a difference in intensity of reflected electrons of an electron beam applied to the alignment mark. The method of obtaining the coordinates of is adopted.

[0010]

The alignment mark is
Although it can be composed of a metal mark or a step structure mark, the alignment mark formed on the layer to be processed has a step due to the thickness of the metal mark or the step structure mark. When a resist or the like is applied, a step may be formed on the surface of the resist or the like. The step existing on this surface or the upper surface of the layer to be processed changes the intensity of the reflected electrons in that region, and is detected as a signal superimposed with the reflected electrons from the original alignment mark.

Although the reflected electrons due to these steps are caused by the alignment mark, they are not accurately formed along the ridgeline of the alignment mark, so that the signal is from the original alignment mark. A deviation from the signal occurs, which causes an error signal.

Further, if any protrusion is present in the vicinity of the alignment mark, the unevenness of the surface due to this protrusion also causes an error signal.

Furthermore, when there is an inclination on the surface of the alignment mark, that is, when there is a distribution in the film thickness of the thin film covering the alignment mark, there is a difference in the depth from the thin film surface to the alignment mark. Occurs, which causes a difference in the intensity of reflected electrons, which causes an error in the detection result of the alignment mark.

An object of the present invention is to provide a semiconductor integrated circuit device having high alignment accuracy in electron beam lithography and a method for manufacturing the same.

Another object of the present invention is to provide a semiconductor integrated circuit device and a method of manufacturing the same in which the cause of the error in the alignment mark is removed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In the semiconductor integrated circuit device of the present invention, any one of the electrodes, wirings, connection holes and other members constituting the semiconductor integrated circuit device formed on the main surface of the semiconductor substrate is an electron beam. A semiconductor integrated circuit device, which is a member formed by electron beam lithography by direct drawing, for specifying a pattern formation position by electron beam drawing on a part of a layer to be processed by electron beam lithography or a lower layer thereof. It has an alignment mark, and the surface of the alignment mark has a flat structure.

According to such a semiconductor integrated circuit device,
Detecting alignment mark detection signals during patterning alignment in electron beam lithography in order to eliminate steps, protrusions or inclinations on the surface or surrounding processed layer and to make the surface of the alignment mark formed on the processed layer flat. The error signal contained in can be reduced. As a result, it is possible to detect the alignment mark with high accuracy and prevent patterning deviation. The prevention of this patterning deviation means an improvement in the overlay accuracy of lithography, and the overlay margin 50 to 6 required in the ULSI having the minimum processing dimension of about 0.2 μm.
It can be cited as one of effective measures for clearing 0 nm.

(2) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (1) above, wherein the mark structure formed in the layer to be processed is covered with a flat film as an alignment mark. Alternatively, the step structure mark formed on the layer to be processed is covered with a flat film.

According to such a semiconductor integrated circuit device,
As the alignment mark, the mark structure formed on the processed layer is covered with a flat film, or the step structure mark formed on the processed layer is covered with a flat film. It is possible to cope with various processes such as a wiring forming process and a dielectric film through hole forming process.

(3) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (2) above, wherein the mark structure is a metal having a secondary electron emission coefficient higher than that of the flat film.
The flat film covering it is a dielectric film made of silicon oxide or silicon nitride, or the step structure mark is a dielectric film made of silicon oxide or silicon nitride, and the flat film covering it is A metal having a higher secondary electron emission coefficient than the step structure mark is used.

According to such a semiconductor integrated circuit device,
The mark structure is made of a metal having a higher secondary electron emission coefficient than the flat film, and the flat film in that case is made of a dielectric film made of silicon oxide or silicon nitride, or
Since the step structure mark is a dielectric made of silicon oxide or silicon nitride and the flat film in that case is a metal having a higher secondary electron emission coefficient than the step structure mark, the material forming the mark and the flat film It is possible to give a difference in molecular weight to the substance constituting the. As a result, a difference in electron scattering coefficient between the two occurs, and a large difference in reflected electron intensity can occur between the outside and the inside of the alignment mark. That is, the contrast of the alignment mark becomes clear, and the detection sensitivity can be improved.

As the metal having a high secondary electron emission coefficient, aluminum, tungsten, molybdenum, platinum,
Nickel, tantalum, ruthenium, titanium, cobalt,
Examples thereof include palladium, gold, copper and the like, or alloys thereof.

(4) In the method of manufacturing a semiconductor integrated circuit device of the present invention, the pattern formation position is specified by referring to the alignment mark provided in the layer to be processed on the main surface of the semiconductor substrate, and the pattern is directly exposed to the electron beam. A method of manufacturing a semiconductor integrated circuit device having an electron beam lithography step of forming by drawing, comprising: (a) a step of flattening a surface of an alignment mark of a processed layer to be processed by electron beam lithography;
(B) irradiating the flattened alignment mark with an electron beam, and detecting the coordinates of the layer to be processed by the reflected electrons of the electron beam.

According to such a method for manufacturing a semiconductor integrated circuit device, since the step (a) of flattening the surface of the alignment mark of the layer to be processed is included, the alignment mark is formed in the step (b). It is possible to accurately detect the coordinates of the layer to be processed, which is detected by reflected electrons by irradiating an electron beam. As a result, it is possible to reduce the positional deviation of the electron beam irradiation performed based on the detected coordinate data of the layer to be processed, and improve the processing accuracy of lithography.

The flattening method is the etchback method,
A method of flattening by a flattening film forming method such as a reflow method, or CMP (Chemical Mechanical Polishing)
g) The method can be exemplified.

(5) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to (4) above, in which the strain of the layer to be processed is detected based on the detected coordinates, It has a step of correcting the pattern so as to compensate for the distortion.

According to such a method for manufacturing a semiconductor integrated circuit device, the distortion of the layer to be processed is detected and the pattern is corrected so as to compensate the distortion.
Even if expansion and contraction occur, it is possible to minimize the pattern shift.

[0030]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1A is a sectional view showing an example of a semiconductor integrated circuit device according to an embodiment of the present invention with respect to its alignment mark portion, and FIG. 2] is a graph showing the intensity of the reflected electron signal with respect to the electron beam scanning position when the alignment mark shown in FIG. 1A is irradiated with the electron beam.

The semiconductor integrated circuit device according to the first embodiment is
A known semiconductor integrated circuit element is formed on a semiconductor substrate 1, and has an alignment mark at any position on the semiconductor substrate 1. For semiconductor integrated circuit elements, MISF such as NMOS, PMOS, CMOS, etc.
An ET element, a bipolar element such as a junction-type FET, a Bi-CMOS element, or the like can be illustrated, but any of them can be manufactured using a known technique, and thus details thereof are omitted.

The alignment mark formed on the semiconductor substrate 1 includes the mark structure 2 formed on the semiconductor substrate 1,
It is composed of a flattening layer 3 coated thereon.

The mark structure 2 is made of a material having a secondary electron emission coefficient higher than that of the flattening layer 3, and is made of aluminum, tungsten, molybdenum, platinum, nickel, tantalum, ruthenium, titanium, cobalt, palladium, gold, copper or the like. Or these alloys can be illustrated. Flattening layer 3
Can use silicon oxide or silicon nitride.

By making the surface of the alignment mark flat as described above, the surface of the layer to be processed can be made flat.

When the alignment mark is irradiated with the electron beam 4, the electron beam 4 passes through the flattening layer 3 and reaches the mark structure 2 to generate a reflected electron beam, as shown in FIG. 1 (b). A backscattered electron signal is detected at. As shown in the figure, the edge of the backscattered electron signal is detected relatively sharply, and the position and strain of the layer to be processed can be accurately measured.

On the other hand, an example in which the surface is not flattened is shown in FIG.
Shown in In FIG. 8A, since the convex portion 5 is formed on the upper portion of the mark structure 2, the electron beam 4 is scattered by the convex portion 5, and the reflected electron signal has its edge as shown in FIG. 8B. It becomes dull.

The layer to be processed may be formed on the surface of the flattening layer 3, or the flattening layer 3 itself may be the layer to be processed.

The mark structure 2 is formed on the surface of the semiconductor substrate 1.
In addition to the case where the mark structure 2 is formed, the mark structure 2 may be formed on the surface of the semiconductor substrate 1 after a suitable thin film is formed.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described.

The method of manufacturing the semiconductor integrated circuit device according to the first embodiment is to manufacture the semiconductor integrated circuit device using the alignment mark in an arbitrary electron beam lithography process. Therefore, other thin film formation, etching, impurity introduction, impurity region forming process using photolithography, thin film forming process, patterning process and the like can be performed using known techniques, and therefore description thereof is omitted here. The alignment mark forming process and the electron beam lithography process using the alignment mark will be described.

The method of manufacturing the semiconductor integrated circuit device of FIG. 1A will be described below.

First, on the semiconductor substrate 1 which has undergone the step of forming a known semiconductor integrated circuit element, aluminum, tungsten, molybdenum, platinum, nickel, tantalum, ruthenium, titanium, cobalt, palladium, gold, copper or the alloys thereof are used. A metal thin film made of is formed by a sputtering method or the like, and this is patterned to form the mark structure 2 (FIG. 2).

Next, a dielectric film 6 of silicon oxide or silicon nitride is formed (FIG. 3). The dielectric film 6 can be formed by a plasma CVD method, a thermal CVD method, or the like.

Next, the surface of the dielectric film 6 is flattened by CMP to form the flattening layer 3, and the alignment mark shown in FIG. 1A is completed.

As a method of manufacturing the flattening layer 3, the dielectric film 6 is used.
In addition to the above method of planarizing by CMP after formation of
A film forming method for flattening the dielectric film itself, for example, an etch back method, an SOG film forming method, an organic film coating method or the like can also be used.

Next, an electron beam lithography process using the alignment mark will be described.

FIG. 4 is a conceptual diagram showing an outline of the electron beam drawing apparatus.

The electrons emitted from the filament 42, which is an electron gun connected to the high-voltage power supply 41, are focused by a focusing lens 43.
Is focused by the diaphragm 44 and unnecessary beams are removed by the diaphragm 44. Further, the electrons pass through the blanking plate 45,
The distribution deflected by the deflection system 46 and expanded is narrowed down by the objective lens 47 and reaches the drawing surface of the wafer 48.
The wafer 48 is a stage 5 that can be moved by a motor 49.
The position of the stage 50 can be detected by the laser interferometer 51. Further, the electron beam drawing apparatus is provided with a sample exchange chamber 52, and the inside of the apparatus is kept in a high vacuum state by a vacuum exhaust system 53.

Next, a positioning mechanism using this electron beam drawing apparatus will be described.

In general, when the deflection of the electron beam is increased, a deflection aberration which cannot be ignored in terms of accuracy is caused. Therefore, the movement of the electron beam forming the pattern with respect to the wafer 48 is carried out by both mechanical movement and deflection of the electron beam.

For mechanical movement, the stage 50 is moved by the motor 49, and the wafer 48 placed on the stage 50 is moved.
Perform a rough alignment of. A laser interferometer 51 may be used for positioning.

For the alignment by deflecting the electron beam, the position is detected by referring to the alignment mark composed of the mark structure 2 and the flattening layer 3 provided on the wafer 48, and the relative position with the alignment mark is detected. The position of the pattern to be drawn is determined by such a positional relationship. The generation of the pattern including the drawing pattern position is performed by the control system 54 of the electron beam drawing apparatus.
It can be calculated by the computer 55 connected to. In the generation of the drawing pattern in the computer 55, if there is a deviation from the design value of the plurality of detection positions of the alignment mark, it is considered that the semiconductor substrate 1 is distorted, and this should be corrected. A drawing pattern can be generated. In addition, the CAD data regarding the drawing pattern is loaded into the computer 55,
It is also possible to automate everything from design to patterning.

According to the semiconductor integrated circuit device having the alignment mark and the method for manufacturing the semiconductor integrated circuit device to which the alignment mark is applied in the electron beam writing apparatus as described above, the surface of the alignment mark is flat. Therefore, the position can be detected with high precision by the alignment mark, and high overlay precision can be realized in the electron beam drawing method which is often applied to fine processing.

Further, in the method of manufacturing such a semiconductor integrated circuit device, an interlayer insulating film is formed on the wiring formed at the same time as the mark structure 2, and a part of this interlayer insulating film is used as the alignment mark flattening layer 3. In this case, the formation of through holes in the interlayer insulating film can be applied to the step of forming holes by electron beam lithography.

The mark structure 2 in the semiconductor integrated circuit device according to the first embodiment has been described as an example in which the portion where metal is present is used as the mark, but as shown in FIG. 5A, no metal is present. It may be a negative type in which a mark is displayed by a part. The reflected electron signal intensity in this case is shown in FIG.

According to such a semiconductor integrated circuit device,
In addition to the effects described above, since the mark is a negative type, peeling of the mark structure is less likely to occur, and the occurrence of short-circuit defects and the like due to the peeled metal can be suppressed.

(Second Embodiment) FIG. 6A is a sectional view showing an example of a semiconductor integrated circuit device according to another embodiment of the present invention with respect to the alignment mark portion thereof.
FIG. 6B is a graph showing the intensity of the reflected electron signal with respect to the electron beam scanning position when the alignment mark shown in FIG. 6A is irradiated with the electron beam.

The semiconductor integrated circuit device according to the second embodiment is
Similar to the first embodiment, a known semiconductor integrated circuit element is formed on the semiconductor substrate 1 and has an alignment mark at any position on the semiconductor substrate 1. A description of the semiconductor integrated circuit device will be omitted.

The alignment mark formed on the semiconductor substrate 1 is the step structure mark 7 formed on the semiconductor substrate 1.
And a planarizing layer 10 coated on it.

The step structure mark 7 has a lower layer 8 having an opening.
And the upper layer 9, and both the lower layer 8 and the upper layer 9 can use silicon oxide or silicon nitride. Further, the upper layer 9 can be omitted.

The flattening layer 10 is made of a material having a secondary electron emission coefficient higher than that of the step structure mark 7, and is made of aluminum, tungsten, molybdenum, platinum, nickel, tantalum, ruthenium, titanium, cobalt, palladium,
Gold, copper, etc. or alloys thereof can be exemplified, and the flattening method is the same as in the first embodiment.
Planarization using the MP method, or etch back,
The flat film can be formed using a flat film forming method such as the SOG method.

When the alignment mark is irradiated with the electron beam 4, the electron beam 4 passes through the flattening layer 10 and reaches the step structure mark 7 to generate a reflected electron beam, which is reflected as shown in FIG. 6B. An electronic signal is detected. As in the first embodiment,
The edge of the backscattered electron signal is detected relatively sharply, and the position and strain of the layer to be processed can be accurately measured.

Since the manufacturing process of the alignment mark and the pattern forming process by electron beam drawing are the same as those in the first embodiment, the description thereof will be omitted.

According to such a semiconductor integrated circuit device and its manufacturing method, since the step structure mark 7 is used as the alignment mark, in addition to the effect shown in the first embodiment, for example, a via hole is opened in the interlayer insulating film. It can also be applied to a step of forming metal wiring after forming holes.

The step structure mark 7 in the semiconductor integrated circuit device according to the second embodiment has been described with respect to the case where the concave portion is used as the mark. However, as shown in FIG. 7A, the convex portion is used as the mark. May be The reflected electron signal intensity in this case is shown in FIG.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-described first or second embodiment, an example in which the member for forming the mark and the member for forming the flattening layer are each a metal or a dielectric is shown. -It may be a combination of dielectrics. Further, the semiconductor may be replaced with any layer. However, it is preferable that the flattening layer and the layer forming the mark have different molecular weights.

In the layer to be processed patterned by the electron beam drawing apparatus, the flattening layer itself may be the layer to be processed, or the thin film formed on the flattening layer may be the layer to be processed. .

Furthermore, in the first or second embodiment,
An example in which a dielectric film or a metal film to be a flat film is formed after the mark structure or the step structure mark is formed and flattened by the CMP technique or the like has been shown. However, the mark structure or the step structure mark is formed after the flat film is formed. The flat film may be subjected to etching to form the metal, or the metal or dielectric forming the mark structure or the step structure mark may be formed flat on the etched portion. Further, a metal layer or a dielectric layer may be further formed on this upper layer,
It goes without saying that as long as the surface is flat, it is included in the concept of the present invention.

[0071]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Since the surface of the alignment mark is made flat, the error signal included in the detection signal of the alignment mark can be reduced during alignment of patterning in electron beam lithography, and the alignment mark can be detected. It can be done accurately. As a result, deviation of patterning can be prevented and the overlay accuracy of lithography can be improved.

(2) As the alignment mark, the mark structure formed on the layer to be processed is covered with a flat film, or the step structure mark formed on the layer to be processed is covered with a flat film. Therefore, it becomes possible to apply it when electron beam lithography performs various processes such as a wiring forming process by etching a metal film and a through hole forming process of a dielectric film.

(3) The mark structure is made of a material having a higher secondary electron emission coefficient than that of the flat film, and the flat film in that case is a dielectric film made of silicon oxide or silicon nitride, or a step structure mark. Is a dielectric made of silicon oxide or silicon nitride, and the flat film in that case is made of a material having a higher secondary electron emission coefficient than the step structure mark. The substance and the substance can have different molecular weights, and a large difference in reflected electron intensity, that is, a clear contrast can be generated between the outside and the inside of the alignment mark. As a result, the detection sensitivity of the alignment mark can be improved.

(4) Since the distortion of the layer to be processed is detected and the pattern is corrected so as to compensate for the distortion, even if the semiconductor substrate is warped or expanded or contracted, the pattern shift can be minimized. You can

[Brief description of drawings]

FIG. 1A is a sectional view showing an example of a semiconductor integrated circuit device according to an embodiment of the present invention with respect to an alignment mark portion thereof, and FIG. 1B is shown in FIG. 6 is a graph showing the intensity of a reflected electron signal with respect to an electron beam scanning position when the alignment mark is irradiated with an electron beam.

FIG. 2 is a cross-sectional view showing an example of a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention with respect to the alignment mark portion thereof.

FIG. 3 is a cross-sectional view showing an example of the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention with respect to the position of the alignment mark.

FIG. 4 is a conceptual diagram showing an outline of an electron beam drawing apparatus used in a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

5A is a cross-sectional view showing another example of the semiconductor integrated circuit device according to the embodiment of the present invention with respect to the alignment mark portion, and FIG. 5B is a cross-sectional view of FIG. 6 is a graph showing the intensity of a reflected electron signal with respect to an electron beam scanning position when the alignment mark shown is irradiated with an electron beam.

FIG. 6A is a sectional view showing an example of a semiconductor integrated circuit device according to another embodiment of the present invention with respect to an alignment mark portion thereof, and FIG. 6B is shown in FIG. 6 is a graph showing the intensity of a reflected electron signal with respect to an electron beam scanning position when the alignment mark is irradiated with an electron beam.

7A is a cross-sectional view showing another example of a semiconductor integrated circuit device according to another embodiment of the present invention with respect to the alignment mark portion, and FIG. 7B is a sectional view of FIG. 6 is a graph showing the intensity of the reflected electron signal with respect to the electron beam scanning position when the alignment mark shown in FIG.

8A is a cross-sectional view showing a portion of an alignment mark when the surface is not flattened, and FIG.
6A is a graph showing the intensity of a reflected electron signal with respect to an electron beam scanning position when the alignment mark shown in FIG.

[Explanation of symbols]

 1 semiconductor substrate 2 mark structure 3 flattening layer 4 electron beam 5 convex portion 6 dielectric film 7 step structure mark 8 lower layer 9 upper layer 10 flattening layer 41 high voltage power supply 42 filament 43 focusing lens 44 diaphragm 45 blanking plate 46 deflection system 47 Objective lens 48 Wafer 49 Motor 50 Stage 51 Laser interferometer 52 Sample exchange chamber 53 Vacuum exhaust system 54 Control system 55 Computer

Claims (7)

[Claims] 1. An electrode formed on a main surface of a semiconductor substrate,
A semiconductor integrated circuit device in which any one of the members constituting the semiconductor integrated circuit device such as the wiring, the connection hole and the like is a member formed by electron beam lithography by direct drawing of an electron beam. A layer to be processed which is a member to be formed has an alignment mark for specifying a formation position of a pattern by drawing the electron beam in a part or a lower layer thereof, and the alignment mark has a flat surface. A semiconductor integrated circuit device having a different structure. 2. The semiconductor integrated circuit device according to claim 1, wherein the alignment mark has a mark structure formed on the layer to be processed covered with a flat film. apparatus. 3. The semiconductor integrated circuit device according to claim 2, wherein the flat film is a dielectric film made of silicon oxide or silicon nitride, and the mark structure is more secondary than the flat film. A semiconductor integrated circuit device comprising a metal having a high electron emission coefficient. 4. The semiconductor integrated circuit device according to claim 1, wherein the alignment mark is formed by covering a step structure mark formed on the layer to be processed with a flat film. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 4, wherein the step structure mark is a dielectric made of silicon oxide or silicon nitride, and the flat film is formed to have a thickness smaller than that of the step structure mark. A semiconductor integrated circuit device comprising a metal having a high secondary electron emission coefficient. 6. A pattern formation position is specified with reference to an alignment mark provided on a layer to be processed on a main surface of a semiconductor substrate,
A method of manufacturing a semiconductor integrated circuit device having an electron beam lithography step of forming a pattern by direct drawing of an electron beam, comprising: (a) the alignment mark of the processed layer processed by the electron beam lithography step. And (b) irradiating the flattened alignment mark with an electron beam and detecting the coordinates of the layer to be processed by the reflected electrons of the electron beam. A method for manufacturing a semiconductor integrated circuit device, comprising: 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein distortion of the layer to be processed is detected based on the detected coordinates, and the pattern is corrected so as to compensate the distortion. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: