JP2001274074A - Graphic data dividing method, exposure method, pattern forming method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration of the performance of an element or a decrease in yield due to a decrease in an pattern overlapping accuracy caused by deformation of the shape of an exposure region. SOLUTION: A first active region 12a, a first gate electrode 13a formed on the first active region 12a, a first contact 14a formed on the first gate electrode 13a, and a first contact pad 15a1 of a part connected by the first contact 14a in wiring connected to the first gate electrode 13a via the first contact 14a, are overlapped on the same exposure region and are pattern-exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for dividing graphic data of a semiconductor integrated circuit pattern, an exposure method and a pattern forming method using the same, and a semiconductor device.

[0002]

2. Description of the Related Art The direct writing method of an electron beam is characterized by high resolution performance and the necessity of an original mask. For this reason, the electron beam direct writing method has been conventionally used as a lithography means for a high-performance semiconductor integrated circuit requiring a fine pattern or a small amount device for a specific application.

In the electron beam direct writing method, unlike the reduced projection exposure method using ultraviolet light or the like, the divided exposure of the semiconductor integrated circuit pattern is performed in a plurality of small exposure areas (fields) of about several mm square or less. In an electron beam lithography system using a multi-stage deflection system, one field is further divided by a plurality of subfields,
Divided exposure of the semiconductor integrated circuit pattern is performed in the subfield. In the following description, a field includes a subfield.

FIG. 9 is a diagram showing an example of an array of fields in a conventional exposure method.

As shown in FIG. 9, several tens μm square to several μm square
A total of nine fields 61 each having a size of about 3 (a region surrounded by a broken line) are arranged in a row direction (horizontal direction) and a column direction (vertical direction). Further, a pattern 62 formed by joining the partial patterns exposed in each field 61 is formed so as to cross the boundary of the field 61.

By the way, a finite connection error (hereinafter, referred to as a field connection error) occurs in a portion near the boundary of each field due to an error in the arrangement position of the field or distortion of the field itself.

For example, in the case shown in FIG. 9, the arrangement of the fields 61 in the first and third rows is shifted downward with respect to the arrangement of the fields 61 in the second row. For this reason, as a result of the arrangement of the fields 61 on the first and second rows overlapping, the dimension of the pattern 62 is relatively large in the portion where the arrangement overlaps, that is, in the first area RA, As a result of the arrangement of the field 61 in the third row being separated, the second area RB between the boundaries of the field 61 in the second and third rows
, The dimensions of the pattern 62 are relatively thin.

For example, in the case shown in FIG. 9, the arrangement of the fields 61 in the first and second columns is vertically shifted from each other, and the arrangement of the fields 61 in the second and third columns is mutually shifted in the vertical direction. It is shifted. Therefore, in the vicinity of the portion where the boundary between the fields 61 of the first and second columns is in contact and the portion near the boundary of the field 61 of the second and third columns, that is, in the third region RC, The pattern 62 is deformed due to the misalignment of the pattern 61.

Conventionally, two types of fields having a shift of 1/2 to 1/3 pitch, for example, in order to suppress dimensional fluctuation or deformation of a pattern due to a field connection error, that is, a decrease in pattern drawing accuracy. Or a multiple drawing method in which the same pattern is overlapped and exposed (hereinafter referred to as a first conventional example), or a pattern in which a margin area is provided outside a field and which is included in a field including the margin area, that is, an extended field (Hereinafter referred to as a second conventional example) has been used.

FIG. 10 is a view showing an exposure method according to a first conventional example.

As shown in FIG. 10, three fields 71 (regions surrounded by thick solid lines) are arranged in the row direction and the column direction, that is, nine fields 71 in total. Of the multiple drawing fields 72 (regions surrounded by broken lines) having a shift in the row direction and the column direction, four in the row direction and the column direction, respectively, for a total of 16
Are arranged.

In the first conventional example, first, a pattern 73 is exposed in a field 71 with a half exposure amount when the pattern 73 is formed by one exposure. At this time, since the pattern 73 crosses the boundary of the field 71, the drawing error of the pattern 73 is reduced due to the connection error of the field 71.

Next, the pattern 73 is exposed again in the multiple drawing field 72 with the same exposure amount as the field 71. At this time, the pattern 73 is the multiple drawing field 7
Since it does not cross the boundary of 2, the writing accuracy of the pattern 73 does not decrease due to the connection error of the multiple writing field 72.

According to the first conventional example, since the same pattern is overlapped and exposed in two types of fields having a shift of 1/2, the drawing accuracy of the pattern is reduced due to a field connection error. Can be alleviated.

FIG. 11 is a view showing an exposure method according to a second conventional example.

As shown in FIG. 11, a margin area is provided outside a field 81 (an area surrounded by a thick solid line) in an area where electron beams can be deflected, that is, in a maximum deflection area 82. A field 83 including the margin area, that is, a pattern 83 that fits in the extension field 81A is exposed in the extension field 81A. However, the pattern 84 that does not fit in the extension field 81A is divided on the boundary of the field 81 (or the extension field 81A), and the portion of the pattern 84 outside the field 81 (or the extension field 81A) is adjacent to the field 81. Is exposed in another field (not shown).

According to the second conventional example, even if a pattern crosses the boundary of a field and falls within the extended field, the pattern is divided into a plurality of Therefore, it is possible to suppress a decrease in pattern drawing accuracy due to a field connection error.

[0018]

The writing time T1 in the ordinary electron beam direct writing method is obtained by the following equation: T1 = (shot time + deflector stabilization time) × total number of shots (Equation 1). At this time, the shot time is determined based on the resist sensitivity and the current density of the electron beam. For example, when an electron beam having a current density of 10 A / cm ² is irradiated on a resist film having a resist sensitivity of 3 μC / cm ² , the shot time is about 300 nsec. Also,
The deflector stabilization time is about 100 nsec in the case of the currently marketed maximum speed electron beam direct writing apparatus.
Although the total number of shots varies greatly depending on the semiconductor integrated circuit pattern, it is 5 to 10 in the case of a semiconductor integrated circuit having a design rule of 0.18 μm using a wafer having a diameter of 200 mm.
Gshot / wafer.

Using the above values, the total number of shots is 5
From (Equation 1), the writing time T1 for Gshot / wafer is given by T1 = (300 nsec + 100 nsec) × (5
× 10 ⁹ ) = 2000 sec / wafer. Similarly, when the total number of shots is 10 Gshot / wafer, the writing time T1 is calculated from (Equation 1) as follows: T1 = (300 nsec)
+100 nsec) × (10 × 10 ⁹ ) = 4000 sec
c / wafer.

On the other hand, the drawing time T2 in the first conventional example (multiple drawing method) is the case of double drawing using two types of fields, T2 = (shot time / 2 + deflector stabilization time) × (2 × Total number of shots) ... (Equation 2)

Using the above numerical values, the total number of shots is 5
The drawing time T2 at the time of Gshot / wafer is calculated from (Equation 2) as follows: T2 = (300 nsec / 2 + 100 nsec) ×
(2 × 5 × 10 ⁹ ) = 2500 sec / wafer is calculated. Similarly, when the total number of shots is 10 Gshot / wafer, the writing time T2 is expressed by T2 = (300
nsec / 2 + 100nsec) × (2 × 10 × 1
0 ⁹ ) = 5000 sec / wafer.

That is, in the first conventional example, the throughput is two times smaller than that of the ordinary electron beam direct writing method.
There is a problem that it is reduced by about 0%. In particular, as the resist sensitivity becomes higher, in other words, as the shot time becomes shorter, the throughput in the first conventional example is reduced by the normal electron beam direct writing due to the difference between (Equation 1) and (Equation 2). It is significantly lower than that of the law.

In the first conventional example, as described above, while it is possible to alleviate a decrease in pattern writing accuracy due to a field connection error, it is not possible to completely eliminate the decrease in pattern writing accuracy. For example, when a pattern dimensional variation caused by a field connection error occurs by about 50 nm in a normal electron beam direct writing method, a multiple writing method (double writing) is used instead of the normal electron beam direct writing method. In addition, the dimensional fluctuation of the pattern due to the field connection error can be suppressed to about 20 nm. At this time, the dimensional variation of the pattern can be regarded as a pattern defect, while the pattern defect that can be normally tolerated is 1/1 of the design rule.
Since it is about 0, the dimensional variation of the pattern of 20 nm is 1
It is not allowed for the design rule of 80 nm (0.18 μm).

In the second conventional example, as described above, a pattern which does not fit in the extended field is divided and exposed on the boundary of the field or the extended field.
As a result, for example, when the gate electrode pattern is divided and exposed on the active region, a dimensional change or deformation of the gate electrode pattern due to a field connection error occurs on the active region, so that the device performance deteriorates. The problem arises.

Further, the field connection error not only lowers the pattern writing accuracy but also lowers the pattern overlay accuracy.

A description will now be given, with reference to FIG. 12, of a reduction in pattern overlay accuracy due to a field connection error.

FIG. 12 is a diagram showing a state where a field connection error has occurred.

As shown in FIG. 12, a total of nine fields 91 (areas surrounded by thick solid lines) are arranged in three rows and columns. At this time, if the shape of each field 91 matches the ideal lattice (usually a square lattice), no field connection error occurs. On the other hand, as shown in FIG.
In the case where the boundary is non-orthogonal as in a, for example, when there is a rotation error with respect to the ideal grating as in the field 91b, or in the case where a magnification (gain) error in respect to the ideal grating as in the field 91c, If the field 91 has such a field, that is, if the shape of each field 91 is distorted (hereinafter referred to as field shape distortion), a field connection error occurs. In addition, if the lower layer pattern is misaligned due to the field shape distortion, unless the upper layer pattern is exposed so as to cause the same misalignment as the lower layer pattern, the lower layer pattern and the upper layer pattern are overlapped. An error occurs and the element performance deteriorates or the yield decreases.

The above description has been made on the premise that the electron beam direct writing method is used. However, SCALPEL or PREVA which has been studied as a next-generation EB (electron beam) exposure method in recent years.
In the EB exposure method of the reduction projection method such as the IL, the partial pattern obtained by dividing the semiconductor integrated circuit pattern is transferred for each exposure region of about 250 μm □ or less that divides the main surface of the substrate to be exposed. A semiconductor integrated circuit pattern is transferred by joining the partial patterns. In addition, in order to miniaturize a semiconductor integrated circuit and increase a chip area, a similar exposure method is being studied in a conventional optical reduction projection exposure method. Therefore, in the future, it is expected that the above-described problem will occur in the EB exposure method of the reduction projection method or the optical reduction projection exposure method.

In view of the above, it is a first object of the present invention to prevent deterioration of element performance or yield due to deterioration of pattern overlay accuracy due to distortion of the shape of an exposure region. A second object is to prevent a dimensional change or the like of a gate electrode pattern caused by a field connection error from occurring on an active region, and a third object to improve a throughput by shortening a pattern writing time. .

[0031]

In order to achieve the first object, a first graphic data dividing method according to the present invention is for drawing a pattern of a semiconductor integrated circuit composed of a plurality of layers. Is divided into a plurality of figures, and a figure data division method of allocating each of the plurality of figures to any one of the plurality of exposure regions is assumed. The second layer is adjacent to each other and has a first layer corresponding to the first layer.
From the graphic data of the first layer, a first graphic corresponding to a portion of the first layer that is electrically coupled to the second layer is separated, and the first graphic is divided into one of a plurality of exposure areas. Allocating to an exposure area, and separating, from the second graphic data corresponding to the second layer, a second graphic corresponding to a portion of the second layer that is electrically coupled to the first layer. Allocating the second figure to one exposure area.

According to the first graphic data division method, the first
A first figure corresponding to a portion of the second layer electrically connected to the second layer, and a second figure corresponding to a portion electrically connected to the first layer of the second layer.
Is assigned to the same exposure area.
Of the layer electrically connected to the second layer in the second layer, that is, the first partial pattern, and the pattern of the portion of the second layer electrically connected to the first layer, that is, the second pattern. The partial pattern can be exposed in the same exposure area. For this reason, even when the shape of the exposure region is distorted, the positional deviation of the first partial pattern and the positional deviation of the second partial pattern become substantially equal. Since the relative positional deviation between the first partial pattern and the second partial pattern is reduced, the overlay accuracy of the first partial pattern and the second partial pattern is improved. Accordingly, since no electrical coupling failure occurs in the semiconductor integrated circuit, it is possible to prevent the element performance from deteriorating or the yield from lowering.

In this specification, the term "electrically coupled" means both capacitive coupling and direct electrical connection.

In order to achieve the first object, a second graphic data dividing method according to the present invention is a method of dividing graphic data for drawing a pattern of a semiconductor integrated circuit comprising a field effect transistor into a plurality of graphic data. And a first pattern corresponding to a first layer including an active region of a field-effect transistor is assumed on the premise of a figure data dividing method in which each of a plurality of figures is assigned to any one of a plurality of exposure regions. Separating a first figure corresponding to the active area from the figure data of the first area and allocating the first figure to one of the plurality of exposure areas; and a gate electrode formed on the active area. Separating the second figure corresponding to the gate electrode from the second figure data corresponding to the second layer including the second layer, and allocating the second figure to one exposure area;
A third pattern corresponding to a contact is separated from third pattern data corresponding to a third layer including a contact formed on an active region or a gate electrode, and the third pattern is exposed by one exposure. A step of allocating to a region, a fourth layer including a wiring connected to an active region or a gate electrode via a contact, and a fourth graphic data corresponding to the fourth layer, the contact pad being a portion of the wiring to which the contact is connected; Separating the corresponding fourth figure and allocating the fourth figure to one exposure area.

According to the second graphic data dividing method, a first graphic corresponding to the active region, a second graphic corresponding to the gate electrode formed on the active region, an active region or the gate electrode are formed. A third figure corresponding to the contact
Also, since the fourth figure corresponding to the contact pad to which the contact is connected in the wiring connected to the active region or the gate electrode via the contact is allocated to the same exposure region, the active region pattern and the gate electrode pattern , The contact pattern and the contact pad pattern can be exposed in the same exposure area. For this reason, even when the shape of the exposure region is distorted, the respective positional deviations of the active region pattern, the gate electrode pattern, the contact pattern, and the contact pad pattern become substantially equal. Since the relative displacement between the electrode pattern, the contact pattern, and the contact pad pattern is reduced, the overlay accuracy of the active region pattern, the gate electrode pattern, the contact pattern, and the contact pad pattern, that is, the wiring pattern is improved. Therefore,
Since the electric coupling failure does not occur in the field-effect transistor included in the semiconductor integrated circuit, it is possible to prevent the element performance from deteriorating or the yield from lowering.

In order to achieve the first object, a third graphic data dividing method according to the present invention divides graphic data for drawing a pattern of a semiconductor integrated circuit comprising bipolar transistors into a plurality of graphics. Then, on the premise of a figure data division method of allocating each of the plurality of figures to any one of the plurality of exposure regions, the first figure data corresponding to the first layer including the collector region of the bipolar transistor is used. The first corresponding to the collector region
And allocating the first graphic to one of the plurality of exposure regions, and a second layer including a base region and an emitter region formed on the collector region. Separating a second graphic corresponding to the base region and the emitter region from the second graphic data and allocating the second graphic to one exposure region; and forming the second graphic on the collector region, the base region or the emitter region. Separating the third graphic corresponding to the contact from the third graphic data corresponding to the third layer including the contact formed on the third layer, and allocating the third graphic to one exposure area;
From the fourth graphic data corresponding to the fourth layer including the wiring connected to the collector region, the base region or the emitter region via the contact, the fourth graphic data corresponding to the contact pad corresponding to the portion of the wiring to which the contact is connected, And separating the fourth figure into one exposure area.

According to the third graphic data dividing method, the first graphic corresponding to the collector region, the second graphic corresponding to the base region and the emitter region formed on the collector region, the collector region, and the base region Or third graphic data corresponding to a contact formed on the emitter region,
In addition, since the fourth pattern corresponding to the contact pad, which is the portion to which the contact is connected in the wiring connected to the collector region, the base region, or the emitter region via the contact, is assigned to the same exposure region,
The collector region pattern, the base region pattern and the emitter region pattern, the contact pattern, and the contact pad pattern can be exposed in the same exposure region. For this reason, even when the shape of the exposure region is distorted, the positional deviations of the collector region pattern, the base region pattern and the emitter region pattern, the contact pattern, and the contact pad pattern become substantially equal, in other words, Since the relative displacement between the collector region pattern, the base region pattern and the emitter region pattern, the contact pattern, and the contact pad pattern is reduced, the collector region pattern, the base region pattern and the emitter region pattern, the contact pattern, and In addition, the overlay accuracy of the contact pad pattern, that is, the wiring pattern is improved. Accordingly, since no electrical coupling failure occurs in the bipolar transistor constituting the semiconductor integrated circuit, it is possible to prevent the element performance from deteriorating or the yield from lowering.

In order to achieve the first object, a fourth graphic data dividing method according to the present invention is to convert graphic data for drawing a pattern of a semiconductor integrated circuit having a multilayer wiring structure into a plurality of graphics. The multi-layer wiring structure is based on a premise of a graphic data dividing method of dividing and allocating each of a plurality of figures to any one of a plurality of exposure regions. Wiring and the first
The first figure corresponding to the first via pad, which is the portion to which the via in the first wiring is connected, is separated from the first figure data corresponding to the first layer including the wiring of FIG. Allocating one figure to one of the plurality of exposure areas, and separating the second figure corresponding to the via from the second figure data corresponding to the second layer including the via; Allocating the second graphic to one exposure area; and a third layer corresponding to a third layer including a second wiring.
Separating the third graphic corresponding to the second via pad, which is the portion to which the via of the second wiring is connected, from the graphic data of the second pattern, and allocating the third graphic to one exposure area. Have.

According to the fourth graphic data dividing method, the first
The first figure corresponding to the first via pad to which the via of the second wiring is connected, the second figure corresponding to the via, and the second via pad to which the via of the second wiring is connected Since the third graphic is allocated to the same exposure area, the first via pad pattern, the via pattern, and the second via pad pattern can be exposed in the same exposure area. For this reason, even when the shape of the exposure region is distorted, the positional deviation of each of the first via pad pattern, the via pattern, and the second via pad pattern becomes substantially equal. Since the relative displacement between the via pad pattern, the via pattern, and the second via pad pattern is reduced, the first via pad pattern, that is, the first wiring pattern, the via pattern, and the second via pad pattern, that is, The overlay accuracy of the second wiring pattern is improved. Accordingly, since there is no occurrence of electrical coupling failure in the multilayer wiring structure forming the semiconductor integrated circuit, it is possible to prevent deterioration of element performance or reduction in yield.

In order to achieve the second object, a fifth graphic data dividing method according to the present invention is directed to a graphic data dividing method for converting a graphic data for drawing a pattern of a semiconductor integrated circuit comprising a field effect transistor into a plurality of graphic data. And a layer including a gate electrode formed on an active region of a field-effect transistor, on the premise of a figure data dividing method of dividing each of a plurality of figures into any one of a plurality of exposure regions. The corresponding graphic data is divided so that the gate electrode pattern is not divided and exposed on the active region.

According to the fifth graphic data dividing method, the graphic data corresponding to the layer including the gate electrode is divided so that the gate electrode pattern is not divided and exposed on the active region. The dimensional variation of the gate electrode pattern does not occur on the active region. Therefore, deterioration of transistor characteristics due to local fluctuation of the gate length or the like can be prevented, and a high-performance semiconductor integrated circuit device can be formed with a high yield.

In order to achieve the second object, a sixth graphic data dividing method according to the present invention is directed to a graphic data dividing method for drawing graphic data for drawing a pattern of a semiconductor integrated circuit comprising field effect transistors into a plurality of graphic data. And a first pattern corresponding to a first layer including an active region of a field-effect transistor is assumed on the premise of a figure data dividing method in which each of a plurality of figures is assigned to any one of a plurality of exposure regions. Determining the position of the center of gravity of the first figure corresponding to the active area using the figure data of the first figure, separating the first figure from the first figure data, and dividing the first figure into a plurality of exposure areas. Allocating to the one exposure area including the center of gravity of the first figure, generating a virtual active area in which the dimension of the active area is largely corrected by a predetermined length, and forming the virtual active area on the active area. Ruge A gate, which is a portion of the gate electrode overlapping the virtual active area, based on the logical product of the graphic corresponding to the virtual active area and the graphic corresponding to the gate electrode from the second graphic data corresponding to the second layer including the gate electrode Separating the second figure corresponding to the electrode logical product part,
Allocating the figure to one exposure area; and, based on the difference between the figure corresponding to the gate electrode and the figure corresponding to the gate electrode logical product unit, from the second figure data, the portion of the gate electrode that does not overlap with the virtual active area. And a third pattern corresponding to the gate electrode difference portion is separated, and the third pattern is formed by joining the pattern of the gate electrode logical product portion and the pattern of the gate electrode difference portion to form a gate electrode pattern. Allocating to at least one of the plurality of exposure areas so that

According to the sixth graphic data division method, after generating a virtual active region in which the size of the active region is greatly corrected by a predetermined length, the virtual active region corresponding to the gate electrode logical product portion overlapping the virtual active region in the gate electrode is generated. Is assigned to the same exposure area as the active area. For this reason,
Since the gate electrode pattern can be divided and exposed outside the active region, that is, on the element isolation region, in other words, the gate electrode pattern is not divided and exposed on the active region, which results from a field connection error. No dimensional fluctuation of the gate electrode pattern occurs on the active region. Therefore, deterioration of transistor characteristics due to local fluctuation of the gate length or the like can be prevented, and a high-performance semiconductor integrated circuit device can be formed with a high yield.

According to the sixth graphic data dividing method, the first graphic corresponding to the active area is allocated to the exposure area including the position of the center of gravity, and the gate electrode overlapping the virtual active area in the gate electrode. The second graphic corresponding to the logical product is assigned to the same exposure area as the active area. For this reason, a figure corresponding to each of the active region and the gate electrode, which overlaps with the active region, that is, a figure corresponding to each of the gate electrode functional portions is allocated to the exposure region having the largest area. In each of the partial patterns, the pattern portion exposed near the boundary between the exposure region and the maximum deflection region can be reduced. Therefore, it is possible to prevent the deterioration of the positional accuracy of the active region pattern and the gate electrode function part pattern, that is, the deterioration of the transistor characteristics, and to form a high-performance semiconductor integrated circuit device at a high yield.

In order to achieve the first object, a first exposure method according to the present invention divides a pattern of a semiconductor integrated circuit composed of a plurality of layers into a plurality of partial patterns, and Assuming an exposure method of exposing each of the partial patterns with any one of the plurality of exposure regions, a first layer and a second layer of the plurality of layers are adjacent to each other, and Exposing a first partial pattern corresponding to a portion of the layer that is electrically coupled to the second layer in one of the plurality of exposure regions; Exposing a second partial pattern corresponding to a portion electrically connected to the layer in one exposure region.

According to the first exposure method, since exposure is performed using the first graphic data division method of the present invention,
Deterioration of element performance or yield can be prevented.

In order to achieve the first object, a second exposure method according to the present invention divides a pattern of a semiconductor integrated circuit composed of a field effect transistor into a plurality of partial patterns, The first partial pattern corresponding to the active region of the field effect transistor is exposed to one of the plurality of exposure regions by assuming an exposure method in which each of the patterns is exposed by any one of the plurality of exposure regions. Exposing in a region, exposing a second partial pattern corresponding to a gate electrode formed on the active region in one exposure region, and corresponding to a contact formed on the active region or the gate electrode A step of exposing the third partial pattern in one exposure region, and a step of exposing the contact in a wiring connected to the active region or the gate electrode through the contact. The fourth and the corresponding contact pads that
Exposing the partial pattern in one exposure region.

According to the second exposure method, since the exposure is performed using the second graphic data division method of the present invention,
Deterioration of element performance or yield can be prevented.

In order to achieve the third object, the second
It is preferable that the exposure method further includes a step of exposing the fourth partial pattern with a charged particle beam and exposing the fifth partial pattern corresponding to a portion of the wiring other than the contact pads with ultraviolet light.

In this manner, since the ultraviolet light exposure of the reduced projection method can be performed for most of the wiring patterns, the pattern writing time can be shortened and the throughput can be improved.

In order to achieve the first object, a third exposure method according to the present invention divides a pattern of a semiconductor integrated circuit comprising a bipolar transistor into a plurality of partial patterns, and The first partial pattern corresponding to the collector region of the bipolar transistor is exposed by one of the plurality of exposure regions, assuming an exposure method of exposing each of the plurality of exposure regions. A step of exposing a second partial pattern corresponding to a base region and an emitter region formed on the collector region in one exposure region, and a contact formed on the collector region, the base region or the emitter region Exposing a third partial pattern corresponding to the first and second exposure patterns in one exposure region, and a collector region, a base region or an emitter region through a contact. And a step of exposing a fourth portion pattern corresponding to the contact pad is a portion where the contact is connected in the wiring to be connected to the area in one exposure area.

According to the third exposure method, since the exposure is performed using the third graphic data division method of the present invention,
Deterioration of element performance or yield can be prevented.

In order to achieve the third object, a third
It is preferable that the exposure method further includes a step of exposing the fourth partial pattern with a charged particle beam and exposing the fifth partial pattern corresponding to a portion of the wiring other than the contact pads with ultraviolet light.

In this way, since the ultraviolet light exposure of the reduced projection method can be performed on most of the wiring patterns, the pattern writing time can be shortened and the throughput can be improved.

In order to achieve the first object, a fourth exposure method according to the present invention comprises dividing a pattern of a semiconductor integrated circuit having a multilayer wiring structure into a plurality of partial patterns, Is exposed on any one of the plurality of exposure regions, the multilayer wiring structure includes at least a first wiring and a second wiring connected via a first wiring, and a first wiring. Exposing a first partial pattern corresponding to a first via pad, which is a portion to which the via is connected, in one of the plurality of exposure regions, and a second portion corresponding to the via Exposing a pattern in one exposure region; and exposing a third partial pattern corresponding to a second via pad, which is a portion to which a via of the second wiring is connected, in the one exposure region. And .

According to the fourth exposure method, since the exposure is performed using the fourth graphic data division method of the present invention,
Deterioration of element performance or yield can be prevented.

In order to achieve the third object, the fourth object
In the exposure method, the first partial pattern and the third partial pattern are exposed by a charged particle beam, and the fourth partial pattern corresponding to a portion other than the first via pad in the first wiring, and the second partial pattern. It is preferable that the method further includes a step of exposing a fifth partial pattern corresponding to a portion other than the second via pad in the wiring with ultraviolet light.

In this way, since the ultraviolet light exposure of the reduced projection method can be performed on most of the wiring patterns, the pattern writing time can be shortened and the throughput can be improved.

In order to achieve the second object, a fifth exposure method according to the present invention comprises dividing a pattern of a semiconductor integrated circuit composed of a field effect transistor into a plurality of partial patterns, Assuming an exposure method in which each of the patterns is exposed by any one of a plurality of exposure regions, the pattern of the gate electrode formed on the active region of the field effect transistor is divided and exposed on the active region. do not do.

According to the fifth exposure method, since the exposure is performed using the fifth graphic data division method of the present invention,
Variations in dimensions of the gate electrode pattern due to field connection errors do not occur on the active region.

In order to achieve the second object, a sixth exposure method according to the present invention comprises dividing a pattern of a semiconductor integrated circuit composed of a field effect transistor into a plurality of partial patterns, Assuming an exposure method of exposing each of the patterns with any one of the plurality of exposure regions, the pattern of the active region of the field-effect transistor is defined as a partial pattern and corresponds to the active region of the plurality of exposure regions. A step of exposing in one exposure region including the center of gravity of the figure, and a gate which is a portion of the gate electrode formed on the active region which overlaps the virtual active region in which the dimension of the active region is largely corrected by a predetermined length. A step of exposing in one exposure region the pattern of the electrode logical product part as a partial pattern, and a step of exposing the gate which is a portion of the gate electrode that does not overlap with the virtual active region Exposure is performed in at least one of the plurality of exposure regions so that a pattern of the gate electrode is formed by joining the pattern of the gate electrode logical product part and the pattern of the gate electrode difference part with the pattern of the pole difference part as a partial pattern. And a step of performing

According to the sixth exposure method, since the exposure is performed using the sixth graphic data division method of the present invention,
Variations in dimensions of the gate electrode pattern due to field connection errors do not occur on the active region.

The pattern forming method according to the present invention comprises the steps of forming a resist film made of a positive type chemically amplified resist on a substrate, exposing a first pattern forming region in the resist film with ultraviolet light, Forming a first pattern on the resist film by performing a post-exposure bake treatment on the film at a first temperature, and then developing the resist film; and a resist film on which the first pattern is formed. After exposing the second pattern forming region in the above with a charged particle beam, the resist film is subjected to a post-exposure bake treatment at a second temperature, and then the resist film is developed, whereby the second pattern is formed on the resist film. Wherein the first temperature is higher than the second temperature.

According to the pattern forming method of the present invention, the first temperature in the post-exposure bake treatment when forming the first pattern on the resist film by ultraviolet light exposure is changed to the second temperature on the resist film by charged particle beam exposure. It is higher than the second temperature in the post-exposure bake treatment when forming a pattern. For this reason, the resist sensitivity to the charged particle beam exposure is lower than the resist sensitivity to the ultraviolet light exposure, so that the influence of the proximity effect of the charged particle beam exposure on the dimensional accuracy of the first pattern can be suppressed. Therefore, without performing the design dimension correction of the first pattern,
Since the first pattern can be formed with desired dimensions, the process can be simplified and the throughput can be improved.

In order to achieve the first object, a first semiconductor device according to the present invention is based on a semiconductor device having a semiconductor integrated circuit composed of a plurality of layers. A first layer and a second layer are adjacent to each other and electrically coupled to the second layer in the first layer, and electrically connected to the first layer in the second layer. Are overlapped and pattern-exposed in the same exposure area.

According to the first semiconductor device, the first semiconductor device of the present invention
Since pattern exposure is performed using the above-described exposure method, it is possible to prevent deterioration of device performance or reduction of yield.

In order to achieve the first object, the second semiconductor device according to the present invention is based on the premise that the semiconductor device has a semiconductor integrated circuit composed of a field-effect transistor. Region, a gate electrode formed on the active region, a contact formed on the active region or the gate electrode, and a portion where a contact in a wiring connected to the active region or the gate electrode through the contact is connected. A certain contact pad is pattern-exposed in the same exposure area.

According to the second semiconductor device, the second semiconductor device of the present invention
Since pattern exposure is performed using the above-described exposure method, it is possible to prevent deterioration of device performance or reduction of yield.

In order to achieve the third object, the second
In the semiconductor device described above, it is preferable that the contact pads are pattern-exposed with a charged particle beam and that portions of the wiring other than the contact pads are pattern-exposed with ultraviolet light.

In this manner, since a large portion of the wiring pattern can be subjected to the reduced projection type ultraviolet light exposure, the pattern drawing time can be reduced and the throughput can be improved.

In order to achieve the first object, the third semiconductor device according to the present invention is based on the premise that the semiconductor device includes a semiconductor integrated circuit comprising a bipolar transistor. A contact formed on the base region and the emitter region, a collector region, a contact formed on the base region or the emitter region, and a contact connected to the collector region, the base region or the emitter region via the contact. Contact pads, which are connected portions, are pattern-exposed in the same exposure area.

According to the third semiconductor device, the third semiconductor device of the present invention
Since pattern exposure is performed using the above-described exposure method, it is possible to prevent deterioration of device performance or reduction of yield.

In order to achieve the third object, a third
In the semiconductor device described above, it is preferable that the contact pads are pattern-exposed with a charged particle beam and that portions of the wiring other than the contact pads are pattern-exposed with ultraviolet light.

In this manner, since the ultraviolet light exposure of the reduced projection method can be performed on most of the wiring patterns, the pattern writing time can be shortened and the throughput can be improved.

In order to achieve the first object, the fourth semiconductor device according to the present invention is based on the premise that the semiconductor device has a semiconductor integrated circuit having a multilayer wiring structure, and the multilayer wiring structure has at least a via. A first via pad, a via, and a via in the second wiring, which are portions to which the via in the first wiring is connected, including a first wiring and a second wiring connected through the first wiring; The second part is
Are subjected to pattern exposure in the same exposure area.

According to the fourth semiconductor device, the fourth semiconductor device of the present invention
Since pattern exposure is performed using the above-described exposure method, it is possible to prevent deterioration of device performance or reduction of yield.

In order to achieve the third object, the fourth
In the semiconductor device of the first aspect, the first via pad and the second via pad are pattern-exposed by a charged particle beam, and a portion of the first wiring other than the first via pad and a portion other than the second via pad of the second wiring. Is preferably pattern-exposed with ultraviolet light.

In this manner, since the ultraviolet light exposure of the reduced projection method can be performed on most of the wiring patterns, the pattern drawing time can be shortened and the throughput can be improved.

In order to achieve the second object, the fifth semiconductor device according to the present invention is based on the premise that the semiconductor device has a semiconductor integrated circuit composed of a field effect transistor, The gate electrode formed on the region is not divided and pattern-exposed on the active region.

According to the fifth semiconductor device, the fifth semiconductor device of the present invention
Since the pattern exposure is performed by using the above exposure method, a dimensional change or the like of the gate electrode pattern due to a field connection error does not occur on the active region.

In order to achieve the second object, a sixth semiconductor device according to the present invention is based on the premise that the semiconductor device has a semiconductor integrated circuit composed of a field effect transistor, The region is pattern-exposed in one exposure region including the center of gravity of the figure corresponding to the active region among the plurality of exposure regions, and the dimension of the active region in the gate electrode formed on the active region is a predetermined length. The gate electrode logical product part that overlaps with the virtual active region that has been greatly corrected is pattern-exposed in one exposure region, and the gate electrode difference part that does not overlap with the virtual active region in the gate electrode is the gate electrode logical part. A small part of the plurality of exposure regions is formed so that the gate electrode pattern is formed by joining the pattern of the stacked portion and the pattern of the gate electrode difference portion. Kutomo one in which pattern exposure.

According to the sixth semiconductor device, the sixth semiconductor device of the present invention
Since the pattern exposure is performed by using the above exposure method, a dimensional change or the like of the gate electrode pattern due to a field connection error does not occur on the active region.

[0083]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a method for dividing graphic data according to a first embodiment of the present invention and an exposure method using the same will be described with reference to a semiconductor integrated circuit comprising field-effect transistors. An example in which a pattern is drawn by charged particle beam exposure, specifically, electron beam exposure will be described with reference to the drawings. In the first embodiment, for simplicity, the field-effect transistor comprises a first layer including an active region, a second layer including a gate electrode formed on the active region, and a second layer including a gate electrode formed on the active region. And a fourth layer including a wiring connected to the gate electrode via the contact, and a fourth layer including a wiring connected to the gate electrode through the contact.
Further, as graphic data for drawing a semiconductor integrated circuit pattern by an exposure apparatus, first graphic data corresponding to the first layer, second graphic data corresponding to the second layer, and third graphic data corresponding to the third layer. It is assumed that the third graphic data to be processed and the fourth graphic data corresponding to the fourth layer are used.

FIG. 1 is a diagram showing a graphic data dividing method according to the first embodiment.

As shown in FIG. 1, the exposure field 11
(Regions surrounded by broken lines) are two-dimensionally arranged. The size of each exposure field 11 is smaller than the width in which the electron beam can be deflected. In other words, each exposure field 11 is provided in a region where electron beam deflection is possible, that is, in a maximum deflection region. A margin area is provided outside the exposure field 11 within the maximum deflection area, and the field 11 can be extended to the margin area.

As shown in FIG. 1, the semiconductor integrated circuit includes three field effect transistors. Specifically, the first field-effect transistor is formed on the first active region 12a, the first gate electrode 13a formed on the first active region 12a, and the first gate electrode 13a. The first contact 14a and the first contact 1
4a connected to the first gate electrode 13a via the first gate electrode 13a.
Of wiring 15a. The second field-effect transistor includes a second active region 12b, a second gate electrode 13b formed on the second active region 12b, and a second active region 12b.
And a second wiring 15b connected to the second gate electrode 13b via the second contact 14b formed on the gate electrode 13b. The third field-effect transistor includes a third active region 12c, a third gate electrode 13c formed on the third active region 12c, and a third gate electrode 13c formed on the third gate electrode 13c. It comprises a third wiring 15c connected to the third gate electrode 13c via the contact 14c and the third contact 14c.

In FIG. 1, wirings connected to the first to third active regions 12a to 12C are omitted for simplicity.

The portion of the first wiring 15a to which the first contact 14a is connected, that is, the first contact pad 15a1, is provided with the first wiring 15a in order to provide a margin for alignment with the first contact 14a. It has a larger width than the other parts, that is, the first wiring body 15a2. Similarly, the second contact pad 15b1 of the second wiring 15b to which the second contact 14b is connected has a larger width than the second wiring main body 15b2, and the third contact pad 15b2 has a larger width. The third contact pad 15c1 to which the third contact 14c is connected has a larger width than the third wiring body 15c2.

In the graphic data dividing method according to the first embodiment, first, first graphic data corresponding to the first layer including the first to third active regions 12a to 12c is divided. Specifically, the first active region 12a is adjacent to the first active region 12a.
Exposure field 11a and second exposure field 11
b, while the first active region 12a
Is included in the second exposure field 11b, the figure corresponding to the first active area 12a is separated from the first figure data, and the figure is stored in the margin area in the second exposure field 11b. Assign using. Also, the second
Of the second exposure field 1
1b, the graphic corresponding to the second active area 12b is separated from the first graphic data, and the graphic is allocated to the second exposure field 11b. In addition, the third
Of the second exposure field 11
b and the third exposure field 11c, while the majority of the third active area 12c is included in the third exposure field 11c. The graphic corresponding to 12c is separated, and the graphic is allocated to the third exposure field 11c using a margin area. A detailed method of determining the exposure field 11 to which each active region 12 is allocated will be described later (see the third embodiment).

Next, the first to third gate electrodes 13a to 13c
Is divided into the second graphic data corresponding to the second layer including. Specifically, since the first gate electrode 13a is capacitively coupled to the first active region 12a, a figure corresponding to the first gate electrode 13a is separated from the second figure data, and the figure is separated. A second exposure field 11b, which is the same as the first active area 12a, is allocated using a margin area. Further, the second gate electrode 13b is connected to the second active region 1
2b, the figure corresponding to the second gate electrode 13b is separated from the second figure data, and the figure is allocated to the same second exposure field 11b as the second active region 12b. . Further, the third gate electrode 13
Since c is capacitively coupled to the third active region 12c,
The graphic corresponding to the third gate electrode 13c is separated from the second graphic data, and the graphic is allocated to the same third exposure field 11c as the third active area 12c using the margin area.

Next, the first to third contacts 14a to 14c
Is divided into the third graphic data corresponding to the third layer including. Specifically, since the first contact 14a is connected to the first gate electrode 13a, a graphic corresponding to the first contact 14a is separated from the third graphic data, and the graphic is converted to the first graphic. The second exposure field 11b that is the same as the gate electrode 13a (that is, the same as the first active region 12a) is allocated using a margin area. Also, the second
Since the contact 14b is connected to the second gate electrode 13b, the figure corresponding to the second contact 14b is separated from the third figure data, and the figure is the same as the second gate electrode 13b ( That is, it is assigned to the second exposure field 11b (same as the second active area 12b). The third contact 14c is connected to the third gate electrode 13c.
Is separated from the third graphic data, the graphic corresponding to the third contact 14c is separated from the third graphic data, and the graphic is the same as the third gate electrode 13c (that is, the same as the third active region 12c). 3.) Allocate to the third exposure field 11c using the margin area.

Next, the fourth graphic data corresponding to the fourth layer including the first to third wirings 15a to 15c is divided.

Incidentally, unlike a transistor pattern, a wiring pattern is often formed over a long distance so as to cross a plurality of exposure fields. Therefore, it is difficult to expose the entire wiring pattern with the same exposure field. difficult. On the other hand, an important point in forming the wiring is the overlay accuracy with respect to the contact.

Therefore, in the first embodiment, the first
Wiring 15a is connected to the first contact 14a at the first contact pad 15a1,
Of the first wiring 15a, the figure corresponding to the first contact pad 15a1 is separated from the figure data, and the figure is used for the second exposure field 11b, which is the same as the first contact 14a, using a margin area. Assign. Further, the second wiring 15b is connected to the second contact pad 15b.
1 is connected to the second contact 14b, the figure corresponding to the second contact pad 15b1 of the second wiring 15b is separated from the fourth figure data, and the figure is converted to the second figure. It is assigned to the same second exposure field 11b as the contact 14b. Further, the third wiring 15c is connected to the third contact pad 15c1 by the third wiring 15c.
Is separated from the fourth figure data, the figure corresponding to the third contact pad 15c1 of the third wiring 15c is separated from the fourth figure data, and the figure is made the same as the third contact 14c. Is allocated to the third exposure field 11c using a margin area.

The first to third wiring body portions 15a2 to 15a-1
The figure corresponding to each of 5c2 is divided by a conventional method. At this time, if each of the contact pads and the corresponding wiring body are not subjected to pattern exposure in the same exposure field, the connection between the contact pad and the wiring body in the wiring pattern is caused due to a field connection error. A position shift occurs in the portion. Therefore, in the first embodiment, the first contact pad 15a1 and the first wiring main body 15a2
Is provided, a second overlap portion 16b is provided between the second contact pad 15b1 and the second wiring body portion 15b2, and the third contact pad 15c1 and the third Wiring body 15c2
A third overlap portion 16c is provided between the second overlap portion 16c.

FIGS. 2 (a) and 2 (b) show the first embodiment shown in FIG.
FIG. 11 is a diagram showing a state in which a semiconductor integrated circuit pattern is divided and exposed in each exposure field by an exposure method using the graphic data division method according to the embodiment. FIG.
In (a) and (b), the same members as those of the semiconductor integrated circuit shown in FIG.

FIG. 2A shows the second exposure field 11.
b shows a portion of the semiconductor integrated circuit pattern exposed to light, and as shown in FIG.
a, a second active region 12b, a first gate electrode 13a,
Second gate electrode 13b, first contact 14a, second contact 14b, first contact pad 15a
The first and second contact pads 15b1 are pattern-exposed in the second exposure field 11b. However, the second
Outside the exposure field 11b, that is, a part of the first active region 12a, the first gate electrode 13a
, A first contact 14a and a first contact pad 15a1 are subjected to pattern exposure using a margin area provided in a second maximum deflection area 17b corresponding to the second exposure field 11b.

FIG. 2B shows a part of the semiconductor integrated circuit pattern exposed in the third exposure field 11c. As shown in FIG. 2B, the third active region 12c, The third gate electrode 13c, the third contact 14c, and the third contact pad 15c1 are pattern-exposed in the third exposure field 11c. However,
A portion located outside the third exposure field 11c, that is, a part of the third active region 12c, the third gate electrode 1
A part of 3c, the third contact 14c, and the third contact pad 15c1 are subjected to pattern exposure using a margin area provided in a third maximum deflection area 17c corresponding to the third exposure field 11c. .

According to the first embodiment, the figure corresponding to the active region, the figure corresponding to the gate electrode formed on the active region, the figure corresponding to the contact formed on the gate electrode, and the contact Since the pattern corresponding to the contact pad to which the contact in the wiring connected to the gate electrode is connected is assigned to the same exposure field, the active area pattern, gate electrode pattern, contact pattern and contact pad pattern are exposed to the same exposure field. Can be drawn in the field. For this reason, even when the shape of the exposure field is distorted, the positional deviations of the active region pattern, the gate electrode pattern, the contact pattern, and the contact pad pattern become substantially equal. Since the relative displacement between the electrode pattern, the contact pattern, and the contact pad pattern is reduced, the overlay accuracy of the active region pattern, the gate electrode pattern, the contact pattern, and the contact pad pattern, that is, the wiring pattern is improved. Accordingly, electric coupling failure does not occur in the field-effect transistor included in the semiconductor integrated circuit, so that it is possible to prevent deterioration of element performance or a decrease in yield.

In the first embodiment, the figure corresponding to the gate electrode, the figure corresponding to the contact formed on the gate electrode, and the contact in the wiring connected to the gate electrode via the contact are connected. The figure corresponding to the contact pad is assigned to the same exposure area, but is not limited to this. The figure corresponding to the active area, the figure corresponding to the contact formed on the active area, and the active A contact pad to which a contact in a wiring connected to the region is connected may be allocated to the same exposure region.

In the first embodiment, a pattern corresponding to a contact pad is exposed by a charged particle beam, and a pattern corresponding to a wiring body (a portion other than the contact pad in the wiring) is exposed to ultraviolet light. Is preferred. By doing so, the ultraviolet light exposure of the reduced projection method can be performed on most of the wiring patterns, so that the pattern writing time can be shortened and the throughput can be improved.

In the first embodiment, a pattern of a semiconductor integrated circuit composed of a field effect transistor is drawn. However, the present invention is not limited to this, and a pattern of a semiconductor integrated circuit composed of a bipolar transistor may be drawn.
Alternatively, a pattern of a semiconductor integrated circuit having a multilayer wiring structure may be drawn.

When drawing a pattern of a semiconductor integrated circuit composed of bipolar transistors, the graphic data dividing method includes the first method including the collector region of the bipolar transistor.
Separating a first figure corresponding to the collector region from the first figure data corresponding to the first layer, and allocating the first figure to one of a plurality of exposure fields; The second figure corresponding to the base area and the emitter area is separated from the second figure data corresponding to the second layer including the base area and the emitter area formed thereon, and the second figure is separated into one. And separating a third figure corresponding to the contact from third figure data corresponding to the third layer including the contact formed on the collector area, the base area or the emitter area. Allocating the third figure to one exposure field, and including a wiring connected to a collector region, a base region, or an emitter region via a contact. From the fourth graphic data corresponding to the fourth layer, the fourth graphic corresponding to the contact pad where the contact in the wiring is connected is separated from the fourth graphic data, and the fourth graphic is converted into one exposure field. And a allocating step. At this time, it is preferable to expose the pattern corresponding to the contact pad with the charged particle beam and to expose the pattern corresponding to the wiring body with ultraviolet light. By doing so, the ultraviolet light exposure of the reduced projection method can be performed on most of the wiring patterns, so that the pattern writing time can be shortened and the throughput can be improved.

When drawing a pattern of a semiconductor integrated circuit having a multilayer wiring structure, the figure data dividing method is as follows.
A first via pad which is a portion to which the via of the first wiring is connected, based on the first graphic data corresponding to the first layer including the first wiring connected to the second wiring via the via; Separating the first figure corresponding to the first figure and assigning the first figure to one of the plurality of exposure fields; and extracting the first figure corresponding to the second layer including the via from the second figure data corresponding to the second layer. Separating the second graphic corresponding to the via and allocating the second graphic to one exposure field; and extracting the third graphic data corresponding to the third layer including the second wiring from the third graphic data. The third via corresponding to the second via pad which is the portion to which the via in the second wiring is connected
And allocating the third graphic to one exposure field area. At this time, the first
A pattern corresponding to each of the first via pad and the second via pad is exposed by a charged particle beam, and a portion of the first wiring other than the first via pad and a portion of the second wiring other than the second via pad are respectively It is preferable to expose a pattern corresponding to the above with ultraviolet light. By doing so, the ultraviolet light exposure of the reduced projection method can be performed on most of the wiring patterns, so that the pattern writing time can be shortened and the throughput can be improved.

(Second Embodiment) Hereinafter, with respect to a pattern forming method according to a second embodiment of the present invention, a pattern corresponding to a contact pad or a via pad is formed on the same resist film by charged particle beam exposure. An example in which a pattern corresponding to a wiring body (a part other than a contact pad or a via pad in a wiring) is formed by ultraviolet light exposure will be described with reference to FIGS.

First, as shown in FIG.
A resist film 22 is formed by spin-coating a positive chemically amplified resist thereon and performing a pre-bake process. At this time, the chemically amplified resist has a wavelength of 1
One having sensitivity to both the deep ultraviolet light of 95 to 248 nm and the electron beam, for example, OE manufactured by Tokyo Ohka Kogyo Co., Ltd.
BR CAP100, MESEP manufactured by Nippon Synthetic Rubber Co., Ltd.
20G, UVIII manufactured by Shipley Co., Ltd. or the like is used. Also,
The pre-bake treatment is performed using a hot plate, for example, at a temperature of about 90 to 110 ° C. and for a time of about 90 to 120 seconds.

Next, after exposing a first pattern formation region (corresponding to, for example, a wiring main body) in the resist film 22 with ultraviolet light, specifically, far ultraviolet light 23, the resist film 22 is exposed using a hot plate, for example. A post-exposure bake process is performed on the substrate 22 at the first temperature T1 for about 90 to 120 seconds. Thereby, as shown in FIG. 3B, the first pattern forming region 22a becomes alkali-soluble.

In this embodiment, the resist film 2
In order to use No. 2 under a condition of high sensitivity to far ultraviolet light, the first temperature T1 is set to a temperature higher than that of a normal post-exposure bake treatment, for example, about 130 ° C.

Next, as shown in FIG. 3C, the resist film 22 is developed using an aqueous solution of TMAH (4-methylammonium hydroxide) having a concentration of 2.38% by mass, so that the first resist film 22 is formed. Is formed.

Next, as shown in FIG. 3D, a second pattern formation region (corresponding to, for example, a contact pad or a via pad) in the resist film 22 is applied to a charged particle beam, specifically, an acceleration voltage of 50%. After exposure with the electron beam 25 of about 70 kV, a post-exposure bake treatment is performed on the resist film 22 at a second temperature T2 for about 90 to 120 seconds using, for example, a hot plate. As a result, FIG.
As shown in (e), the second pattern formation region 22b becomes alkali-soluble.

In the present embodiment, the second temperature T
2 is set to a temperature lower than the first temperature T1, for example, about 110 ° C. In this case, since the resist sensitivity to electron beam exposure is lower than the resist sensitivity to ultraviolet light exposure, a new resist is formed around the first pattern 24 formed with a higher resist sensitivity (that is, a smaller exposure amount). The generation of an alkali-soluble region can be prevented. In addition, since the influence of fogging (proximity effect of electron beam exposure, which will be described later) due to backscattered electrons is also reduced, when developing the resist film 22 after performing the second post-exposure bake process, the first pattern 24 is developed. Can be avoided.

Next, as shown in FIG. 3F, the resist film 22 is developed using an aqueous solution of TMAH (4-methylammonium hydroxide) having a concentration of 2.38% by mass, so that the second resist film 22 is formed. Is formed.

In the exposure using a charged particle beam, particularly an electron beam having a small mass, electrons are scattered (backscattered) in the substrate to be exposed, and the backscattering radius (several to several tens μm) from the incident point. Up to the realm. For this reason, in the electron beam exposure, a proximity effect occurs in that patterns exposed through a distance equal to or less than the backscattering radius interact with each other. As a result, when one pattern is formed on a resist film by ultraviolet light exposure, and then another pattern is formed on the resist film by charged particle beam exposure, specifically, electron beam exposure, the dimensional accuracy of one pattern is reduced. Is affected by electron beam exposure. At this time, when the design dimension of one pattern is corrected by calculating the stored energy distribution of the resist film due to the back scattering of the electron beam in order to form one pattern with a desired dimension, the ultraviolet light exposure is usually reduced. Since it is performed by projection exposure,
It is necessary to perform the design dimension correction by correcting the mask pattern, which causes a problem that the process becomes complicated.

On the other hand, according to the second embodiment,
After exposing the first pattern formation region 22a in the resist film 22 made of a positive type chemically amplified resist with ultraviolet light, the resist film 22 is subjected to a post-exposure bake treatment at a first temperature T1, and then the resist A step of forming a first pattern 24 on the resist film 22 by developing the film 22; and a step of forming a second pattern forming region 22b in the resist film 22 on which the first pattern 24 is formed by a charged particle beam. Specifically, after exposure with an electron beam, the resist film 22 is subjected to a post-exposure bake treatment at a second temperature T2, and then the resist film 22 is developed to form a second pattern 26 on the resist film 22. Forming the first temperature T1 to the second temperature T2.
Is set higher than the temperature T2. Generally, the resist sensitivity of a chemically amplified resist increases as the temperature of the post-exposure bake treatment increases. For this reason, the resist sensitivity to the charged particle beam exposure is lower than the resist sensitivity to the ultraviolet light exposure, so that the influence of the proximity effect of the charged particle beam exposure on the dimensional accuracy of the first pattern 24 can be suppressed. Therefore, the first pattern 24
Without correcting the design dimension of the first pattern 24.
Can be formed in desired dimensions, so that the process can be simplified and the throughput can be improved.

(Third Embodiment) Hereinafter, a pattern of a semiconductor integrated circuit composed of a field-effect transistor will be described by using a charged particle method according to a graphic data division method and an exposure method using the same according to a third embodiment of the present invention. An example in which writing is performed by beam exposure, specifically, electron beam exposure will be described with reference to the drawings. In the third embodiment, for simplicity, the field-effect transistor is constituted by a first layer including an active region and a second layer including a gate electrode formed on the active region. The first graphic data corresponding to the first layer and the second graphic data corresponding to the second layer are used as graphic data for drawing the semiconductor integrated circuit pattern by the exposure apparatus. Shall be

FIGS. 4 to 7 are diagrams showing each step of the graphic data dividing method according to the third embodiment.

As shown in FIGS. 4 to 7, a plurality of exposure fields 31 (regions surrounded by broken lines) are two-dimensionally arranged. The size of each exposure field 31 is smaller than the width in which the electron beam can be deflected. In other words, each exposure field 31 is provided in a region where electron beams can be deflected, that is, in a maximum deflection region. A margin area is provided outside the exposure field 31 within the maximum deflection area, and the field 31 can be extended to the margin area.

In the graphic data dividing method according to the third embodiment, first, as shown in FIG. 4, a first active region 32a, a second active region 32b, and a third active region
The first graphic data corresponding to the first layer including 2c is divided. Specifically, using the first graphic data, a first center of gravity 33a of the graphic corresponding to the first active area 32a is used.
, The coordinates of the second centroid 33b of the graphic corresponding to the second active area 32b, and the coordinates of the third centroid 33c of the graphic corresponding to the third active area 32c, respectively,
A graphic corresponding to each active area 32 is separated from the first graphic data, and the graphic is allocated to the exposure field 31 including each center of gravity 33 using a margin area. In this way, the first active region 32a extends over both the adjacent first and second exposure fields 31a and 31b, while the first center of gravity 33a is included in the second exposure field 31b. Therefore, the figure corresponding to the first active area 32a is allocated to the second exposure field 31b using the margin area. Further, since the second center of gravity 33b is included in the second exposure field 31b, the figure corresponding to the second active region 32b is allocated to the second exposure field 31b. Further, the third active region 32c is adjacent to the second exposure field 31b.
And the third center of gravity 33c is located on the third exposure field 31c.
c, the figure corresponding to the third active area 32c is allocated to the third exposure field 31c using the margin area.

Next, as shown in FIG. 5, the first active region 32a, the second active region 32b, and the third active region
2c is largely corrected by a predetermined length, and a first virtual active region 34a corresponding to the first active region 32a, a second virtual active region 34b corresponding to the second active region 32b, And a third virtual active region 34c corresponding to the third active region 32c.

As shown in FIG. 5, the semiconductor integrated circuit comprises three field effect transistors. In particular,
The first field-effect transistor includes a first active region 32
a and a first gate electrode 35a formed on the first active region 32a. The second field-effect transistor includes a second active region 32b and a second active region 3a.
The third field-effect transistor includes a second gate electrode 35b formed on the second active region 32b, and a third gate electrode formed on the third active region 32c. 35c.

Next, a second gate electrode 35a including a first gate electrode 35a, a second gate electrode 35b, and a third gate electrode 35c.
And the second graphic data corresponding to the layer No. 1 is divided. Specifically, as shown in FIG. 6, the first virtual active region 34a
From the second graphic data based on the logical product of the graphic corresponding to the first gate electrode 35a and the graphic corresponding to the first gate electrode 35a.
Virtual active region 34a in gate electrode 35a of
Then, the figure corresponding to the first gate electrode AND unit 35a1 overlapping with the figure is separated, and the figure is allocated to the second exposure field 31b, which is the same as the first active region 32a, using the margin area. Further, based on the logical product of the graphic corresponding to the second virtual active region 34b and the graphic corresponding to the second gate electrode 35b, the second virtual data in the second gate electrode 35b is obtained from the second graphic data. The graphic corresponding to the second gate electrode AND unit 35b1 overlapping the active region 34b is separated, and the graphic is allocated to the same second exposure field 31b as the second active region 32b. Further, the figure corresponding to the third virtual active region 34c and the third gate electrode 3
Based on the logical product of 5c and the corresponding graphic, a third gate electrode logical product part 35 overlapping the third virtual active region 34c in the third gate electrode 35c is obtained from the second graphic data.
The graphic corresponding to c1 is separated, and the graphic is allocated to the same third exposure field 31c as the third active area 32c using the margin area.

Thereafter, as shown in FIG. 7, based on the difference between the figure corresponding to the first gate electrode 35a and the figure corresponding to the first gate electrode AND section 35a1, the second figure data is obtained. The figure corresponding to the first gate electrode difference section 35a2 which does not overlap with the first virtual active region 34a in the first gate electrode 35a is separated, and the figure is separated into the first exposure field 31a or the second exposure field 31b.
Assign to Further, based on the difference between the figure corresponding to the second gate electrode 35b and the figure corresponding to the second gate electrode AND unit 35b1, the second figure data
Virtual active region 34b in gate electrode 35b
The figure corresponding to the second gate electrode difference section 35b2 which does not overlap with the second exposure field 31 is separated.
Assign to b. Also, based on the difference between the figure corresponding to the third gate electrode 35c and the figure corresponding to the third gate electrode AND unit 35c1, the third figure in the third gate electrode 35c is obtained from the second figure data. Virtual active area 34
c is separated from the figure corresponding to the third gate electrode difference section 35c2 which does not overlap with the second exposure field 3c.
1b or the third exposure field 31c.

In the present embodiment, the first gate electrode difference portion 35a2 and the second gate electrode difference portion 35b2
And the figure corresponding to each of the third gate electrode difference section 35c2 is based on the position coordinates of the first gate electrode difference section 35a2, the second gate electrode difference section 35b2, and the third gate electrode difference section 35c2. It is assigned to any one of the plurality of exposure fields 31.

In this embodiment, the first virtual active area 34a, the second virtual active area 34b, and the third virtual active area 34c are virtual areas for performing graphic data division. For pattern exposure of each active area 32, a figure corresponding to each active area 32 itself is used instead of a figure corresponding to each virtual active area 34.

FIGS. 8A to 8C show a semiconductor integrated circuit pattern divided by an exposure method using the graphic data division method according to the third embodiment shown in FIGS. It is a figure which shows a mode that it is exposing. 8A to 8C, the same members as those of the semiconductor integrated circuit shown in FIGS. 4 to 7 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 8A shows a first exposure field 31.
8A shows a part of the semiconductor integrated circuit pattern exposed to light, and as shown in FIG. 8A, a part of the first gate electrode difference part 35a2 is pattern-exposed in the first exposure field 31a. .

FIG. 8B shows the second exposure field 31.
b shows a part of the semiconductor integrated circuit pattern exposed to light, and as shown in FIG.
a, the second active region 32b, a part of the first gate electrode logical product part 35a1, the first gate electrode differential part 35a2, the second gate electrode logical product part 35b1, the second gate electrode differential part 35b2, A part of the third gate electrode difference section 35c2 is pattern-exposed in the second exposure field 31b. However, a portion located outside the second exposure field 31b, that is, a part of the first active region 32a and a part of the first gate electrode logical product part 35a1 are the maximum corresponding to the second exposure field 31b. Pattern exposure is performed using a margin area provided in the deflection area.

FIG. 8C shows the third exposure field 31.
c shows a part of the semiconductor integrated circuit pattern exposed to light, and as shown in FIG.
c, a part of the third gate electrode logical product part 35c1 and the third gate electrode difference part 35c2 is the third exposure field 3
The pattern is exposed at 1c. However, a portion located outside the third exposure field 31c, that is, a part of the third active region 32c and the third gate electrode AND section 35c
A part of 1 is pattern-exposed using a margin area provided in the maximum deflection area corresponding to the third exposure field 31c.

In this embodiment, the pattern of the first gate electrode 35a is the first gate electrode logical product 3
5a1 is formed by joining the pattern of the first gate electrode difference portion 35a2 with the pattern of the first gate electrode difference portion 35a2.
The pattern of the gate electrode 35b is different from the pattern of the second gate electrode logical product section 35b1 in the second gate electrode difference section 3
The third gate electrode 35c is formed by connecting the pattern of the third gate electrode AND part 35c1 and the pattern of the third gate electrode difference part 35c2. It is formed.

If it is necessary to perform wiring between transistors using a layer including a gate electrode, the gate electrode is routed outside the active region.
The gate electrode pattern no longer fits within the maximum deflection area corresponding to the exposure field. For this reason, it is necessary to divide the gate electrode pattern into a plurality of partial patterns and expose each partial pattern in a plurality of exposure regions. In the field-effect transistor, the transistor characteristics greatly depend on the width of the cross section of the gate electrode on the active region, that is, the gate length. Accordingly, when the gate electrode pattern is divided and exposed on the active region, local variations in the gate length and the like due to a field connection error occur on the active region. In addition, there arises a problem that the yield is deteriorated.

In the charged particle beam exposure, when the beam is deflected in each exposure field, the width of each exposure field is set smaller than the maximum deflection swing width of the beam, as described above. , A margin region having a predetermined margin width is provided.
In other words, each exposure field is provided within the maximum deflection area. However, the margin is finite,
If pattern exposure is performed in the vicinity of the boundary of the maximum deflection area, deflection distortion becomes large and the positional accuracy of the pattern deteriorates. Therefore, it is desirable that a pattern portion exposed in a margin area corresponding to each exposure field is small.

On the other hand, according to the third embodiment,
After generating the virtual active region 34 in which the size of the active region 32 is greatly corrected by a predetermined length, the figure corresponding to the gate electrode AND part overlapping the virtual active region 34 in the gate electrode 35 is the same as the active region 32. Exposure field 31
Assigned to. Therefore, the pattern of the gate electrode 35 can be divided and exposed outside the active region 32, that is, on the element isolation region. In other words, the pattern of the gate electrode 35 can be divided and exposed on the active region 32. Since there is no field connection error, a dimensional change of the pattern of the gate electrode 35 due to the field connection error does not occur on the active region 32. Therefore, deterioration of transistor characteristics due to local fluctuation of the gate length or the like can be prevented, and a high-performance semiconductor integrated circuit device can be formed with a high yield.

According to the third embodiment, the figure corresponding to the active region 32 is allocated to the exposure field 31 including the position of the center of gravity, and the gate electrode 35
Are assigned to the same exposure field 31 as the active region 32, corresponding to the gate electrode AND part overlapping the virtual active region 34 in FIG. Therefore, the figure corresponding to each of the active region 32 and the portion of the gate electrode 35 that overlaps with the active region 32, that is, the gate electrode functional portion,
Since the area is allocated to the exposure field 31 including the largest area, the pattern portion exposed in the vicinity of the boundary between the exposure field 31 and the maximum deflection area in each of the pattern of the active region 32 and the pattern of the gate electrode function part is determined. Can be smaller. Therefore, deterioration of the positional accuracy of the pattern of the active region 32 and the pattern of the gate electrode function part, that is, deterioration of the transistor characteristics can be prevented, and a high-performance semiconductor integrated circuit device can be formed with a high yield.

[0134]

According to the present invention, since the overlapping accuracy of the patterns of the electrically coupled portions in each of the adjacent layers is improved, electrical coupling failure in the semiconductor integrated circuit does not occur. In addition, it is possible to prevent the performance of the device from deteriorating or the yield from decreasing.

Further, according to the present invention, since the gate electrode pattern is not divided and exposed on the active region, a dimensional change of the gate electrode pattern due to a field connection error does not occur on the active region. In addition, it is possible to prevent the transistor characteristics from deteriorating due to local variations in the gate length.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a graphic data dividing method according to a first embodiment of the present invention.

FIGS. 2 (a) and (b) show a semiconductor integrated circuit pattern divided by an exposure method using a graphic data division method according to a first embodiment of the present invention, and exposure is performed in each exposure field. It is a figure showing a situation.

FIGS. 3A to 3F are views showing respective steps of a pattern forming method according to a second embodiment of the present invention.

FIG. 4 is a diagram showing one step of a graphic data dividing method according to a third embodiment of the present invention.

FIG. 5 is a diagram showing one step of a graphic data dividing method according to a third embodiment of the present invention.

FIG. 6 is a diagram showing one step of a graphic data dividing method according to a third embodiment of the present invention.

FIG. 7 is a diagram showing one step of a graphic data dividing method according to a third embodiment of the present invention.

FIGS. 8 (a) to 8 (c) show a semiconductor integrated circuit pattern divided by an exposure method using a graphic data division method according to a third embodiment of the present invention, and exposure is performed in each exposure field. It is a figure showing a situation.

FIG. 9 is a diagram showing an example of a field arrangement in a conventional exposure method.

FIG. 10 is a view showing an exposure method according to a first conventional example.

FIG. 11 is a view showing an exposure method according to a second conventional example.

FIG. 12 is a diagram illustrating a state where a field connection error has occurred.

[Explanation of symbols]

 Reference Signs List 11 exposure field 11a first exposure field 11b second exposure field 11c third exposure field 12 active area 12a first active area 12b second active area 12c third active area 13 gate electrode 13a first gate Electrode 13b Second gate electrode 13c Third gate electrode 14 Contact 14a First contact 14b Second contact 14c Third contact 15 Wiring 15a First wiring 15a1 First contact pad 15a2 First wiring main body 15b 2nd wiring 15b1 2nd contact pad 15b2 2nd wiring main body 15c 3rd wiring 15c1 3rd contact pad 15c2 3rd wiring main body 16a 1st overlap part 16b 2nd overlap part 16c Third overlap 17b Second maximum deflection area 17c Third maximum deflection area 21 Substrate 22 Resist film 22a First pattern formation area 22b Second pattern formation area 23 Far ultraviolet light 24 First pattern 25 Electron beam 26 Second pattern 31 Exposure field 31a First exposure field 31b Second exposure field 31c Third exposure field 32 Active area 32a First active area 32b Second active area 32c Third active area 33 Center of gravity 33a First center of gravity 33b Second centroid 33c Third centroid 34 Virtual active area 34a First virtual active area 34b Second virtual active area 34c Third virtual active area 35 Gate electrode 35a First gate electrode 35a1 First gate electrode logic Stacking part 35a2 First gate electrode difference part 35b Second gate electrode 3 b1 second gate electrode logical unit 35b2 second gate electrode difference portion 35c the third gate electrode of 35c1 third gate electrode logical unit 35c2 third gate electrode differential unit

Claims (25)

[Claims] 1. A graphic data for drawing a pattern of a semiconductor integrated circuit composed of a plurality of layers is divided into a plurality of figures, and each of the plurality of figures is assigned to one of a plurality of exposure regions. A graphic data dividing method for allocating the first and second layers, wherein a first layer and a second layer of the plurality of layers are adjacent to each other, and A first figure corresponding to a portion of the first layer that is electrically coupled to the second layer is separated, and the first figure is assigned to one of the plurality of exposure areas. Allocating, separating, from the second graphic data corresponding to the second layer, a second graphic corresponding to a portion of the second layer that is electrically coupled to the first layer. , The second figure Allocating to the one exposure area. 2. A graphic data for drawing a pattern of a semiconductor integrated circuit comprising a field effect transistor is divided into a plurality of figures, and each of the plurality of figures is one of a plurality of exposure regions. And separating a first graphic corresponding to the active region from first graphic data corresponding to a first layer including an active region of the field-effect transistor. Allocating a first figure to one of the plurality of exposure areas; and obtaining a gate from the second figure data corresponding to a second layer including a gate electrode formed on the active area. Separating a second figure corresponding to an electrode and allocating the second figure to the one exposure region; and a step including a contact formed on the active region or on the gate electrode. Separating the third graphic corresponding to the contact from the third graphic data corresponding to the third layer, and allocating the third graphic to the one exposure area; A fourth layer corresponding to a fourth layer including a region or a wiring connected to the gate electrode;
Separating a fourth figure corresponding to a contact pad, which is a portion of the wiring to which the contact is connected, from the figure data, and allocating the fourth figure to the one exposure area. A graphic data division method characterized by the following. 3. A graphic data for drawing a pattern of a semiconductor integrated circuit comprising bipolar transistors is divided into a plurality of figures, and each of the plurality of figures is assigned to one of a plurality of exposure regions. A method for dividing graphic data, comprising: a first region including a collector region of the bipolar transistor.
Separating a first figure corresponding to the collector area from first figure data corresponding to the layer of the first pattern, and allocating the first figure to one of the plurality of exposure areas; From second graphic data corresponding to a second layer including a base region and an emitter region formed on the collector region, a second graphic data corresponding to the base region and the emitter region is obtained.
Separating the figure from the first figure and allocating the second figure to the one exposure area; and corresponding to a third layer including a contact formed on the collector area, the base area or the emitter area. Separating a third figure corresponding to the contact from the third figure data to be assigned, and allocating the third figure to the one exposure area; and the collector area and the base area via the contact. Or a fourth wiring including a wiring connected to the emitter region.
The fourth graphic data corresponding to the contact pad, which is the portion of the wiring to which the contact is connected, is separated from the fourth graphic data corresponding to the fourth layer.
Allocating the figure to the one exposure area. 4. A graphic data for drawing a pattern of a semiconductor integrated circuit having a multilayer wiring structure is divided into a plurality of figures, and each of said plurality of figures is assigned to one of a plurality of exposure regions. A method for dividing graphic data to be allocated, wherein the multilayer wiring structure includes a first wiring and a second wiring connected via a via, and a first layer corresponding to a first layer including the first wiring. Of the first via pad corresponding to the first via pad which is the portion of the first wiring to which the via is connected,
Separating the first figure into one of the plurality of exposure areas, and allocating the first figure to the second figure data corresponding to the second layer including the via. Separating a second figure corresponding to the second figure and assigning the second figure to the one exposure area; and a third figure data corresponding to a third layer including the second wiring, A third via corresponding to a second via pad which is a portion of the second wiring to which the via is connected;
Separating the figure and allocating the third figure to the one exposure area. 5. A graphic data for drawing a pattern of a semiconductor integrated circuit composed of a field effect transistor is divided into a plurality of figures, and each of the plurality of figures is one of a plurality of exposure regions. A graphic data dividing method for dividing a graphic data corresponding to a layer including a gate electrode formed on an active region of the field-effect transistor into corresponding graphic data, wherein the pattern of the gate electrode is divided on the active region. A graphic data division method characterized in that the pattern data is not exposed to light. 6. A graphic data for drawing a pattern of a semiconductor integrated circuit composed of a field effect transistor is divided into a plurality of figures, and each of the plurality of figures is one of a plurality of exposure regions. A first graphic data corresponding to a first layer including an active region of the field-effect transistor, using a first graphic data corresponding to the active region, the position of the center of gravity of the first graphic corresponding to the active region. Calculating the first figure from the first figure data,
Allocating the first figure to one of the plurality of exposure areas, the exposure area including a center of gravity of the first figure; and a virtual activity in which the size of the active area is greatly corrected by a predetermined length. Generating a region; and, from a second graphic data corresponding to a second layer including a gate electrode formed on the active region, a graphic corresponding to the virtual active region and a graphic corresponding to the gate electrode. Separating a second graphic corresponding to a gate electrode logical product portion, which is a portion of the gate electrode overlapping the virtual active region, based on the logical product, and allocating the second graphic to the one exposure region; Based on a difference between a figure corresponding to the gate electrode and a figure corresponding to the gate electrode logical product unit from the second figure data, and does not overlap with the virtual active region in the gate electrode. Third and the corresponding gate electrode differential unit is minute
And the third pattern is divided into the plurality of exposure regions so that the pattern of the gate electrode is formed by joining the pattern of the gate electrode logical product part and the pattern of the gate electrode difference part. At least one of
And a step of allocating the figure data. 7. Exposure for dividing a pattern of a semiconductor integrated circuit composed of a plurality of layers into a plurality of partial patterns, and exposing each of the plurality of partial patterns to one of a plurality of exposure regions. A method, wherein a first layer and a second layer of the plurality of layers are adjacent to each other and correspond to a portion of the first layer that is electrically coupled to the second layer. Exposing a first partial pattern to be exposed in one of the plurality of exposure regions, and a second portion corresponding to a portion of the second layer that is electrically coupled to the first layer. Exposing the second partial pattern in the one exposure area. 8. A pattern of a semiconductor integrated circuit comprising a field-effect transistor is divided into a plurality of partial patterns,
An exposure method for exposing each of the plurality of partial patterns in any one of a plurality of exposure regions, the first method corresponding to an active region of the field-effect transistor.
Exposing the partial pattern in one of the plurality of exposure regions to an exposure region; and a second pattern corresponding to a gate electrode formed on the active region.
Exposing the partial pattern in the one exposure region; and exposing a third partial pattern corresponding to a contact formed on the active region or on the gate electrode in the one exposure region; Exposing a fourth partial pattern corresponding to a contact pad, which is a portion to which the contact is connected, in a wiring connected to the active region or the gate electrode via a contact in the one exposure region. An exposure method, comprising: 9. The method further comprising exposing the fourth partial pattern with a charged particle beam and exposing a fifth partial pattern corresponding to a portion of the wiring other than the contact pad with an ultraviolet light. The exposure method according to claim 8, wherein: 10. An exposure method for dividing a pattern of a semiconductor integrated circuit comprising a bipolar transistor into a plurality of partial patterns and exposing each of the plurality of partial patterns to one of a plurality of exposure regions. Exposing a first partial pattern corresponding to the collector region of the bipolar transistor in one of the plurality of exposure regions, and corresponding to a base region and an emitter region formed on the collector region. Exposing the second partial pattern to be exposed in the one exposure area; and exposing the third partial pattern corresponding to a contact formed on the collector area, the base area or the emitter area to the one exposure area. Exposing in a region, the collector region, the base region or the emitter region through the contact Exposure method characterized by comprising the step of exposing the fourth part patterns corresponding to the contact pad is a portion in which the contact of the wiring to be continued is connected with the one exposure area. 11. The method according to claim 1, further comprising a step of exposing the fourth partial pattern with a charged particle beam and exposing a fifth partial pattern corresponding to a portion of the wiring other than the contact pad with ultraviolet light. The exposure method according to claim 10, wherein: 12. An exposure method for dividing a pattern of a semiconductor integrated circuit having a multi-layer wiring structure into a plurality of partial patterns and exposing each of the plurality of partial patterns to one of a plurality of exposure regions. Wherein the multilayer wiring structure includes at least a first wiring and a second wiring connected via a via, and a first via pad which is a portion of the first wiring to which the via is connected; Exposing a corresponding first partial pattern in one of the plurality of exposure regions in an exposure region; exposing a second partial pattern corresponding to the via in the one exposure region; Exposing a third partial pattern corresponding to a second via pad, which is a portion of the second wiring, to which the via is connected, in the one exposure region. Method. 13. A fourth partial pattern corresponding to a portion of the first wiring other than the first via pad, while exposing the first partial pattern and the third partial pattern by a charged particle beam, and Fifth portions corresponding to portions of the second wiring other than the second via pad
13. The exposure method according to claim 12, further comprising a step of exposing said partial pattern with ultraviolet light. 14. An exposure method for dividing a pattern of a semiconductor integrated circuit comprising a field effect transistor into a plurality of partial patterns and exposing each of the plurality of partial patterns to one of a plurality of exposure regions. An exposure method, wherein a pattern of a gate electrode formed on an active region of the field effect transistor is not divided and exposed on the active region. 15. An exposure method for dividing a pattern of a semiconductor integrated circuit composed of a field effect transistor into a plurality of partial patterns and exposing each of the plurality of partial patterns to one of a plurality of exposure regions. A step of exposing the pattern of the active region of the field effect transistor as the partial pattern in one exposure region including the center of gravity of a figure corresponding to the active region among the plurality of exposure regions, In the gate electrode formed on the active region, a pattern of a gate electrode logical product portion which is a portion overlapping a virtual active region in which the dimension of the active region is largely corrected by a predetermined length is defined as the partial pattern. Exposing in an exposure region of the gate electrode; and a pattern of a gate electrode difference portion which is a portion of the gate electrode that does not overlap with the virtual active region. With the pattern as the partial pattern, at least one of the plurality of exposure regions is formed such that the pattern of the gate electrode is formed by joining the pattern of the gate electrode logical product portion and the pattern of the gate electrode difference portion. An exposing step. 16. A step of forming a resist film made of a positive chemically amplified resist on a substrate, and exposing a first pattern formation region in the resist film to ultraviolet light. Performing a post-exposure bake treatment at a temperature of 1 and then developing the resist film to form a first pattern on the resist film; and forming a first pattern on the resist film on which the first pattern is formed. After exposing the second pattern formation region with the charged particle beam, the resist film is subjected to a post-exposure bake treatment at a second temperature, and then the resist film is developed, whereby the second Forming a pattern, wherein the first temperature is higher than the second temperature. 17. A semiconductor device including a semiconductor integrated circuit including a plurality of layers, wherein a first layer and a second layer among the plurality of layers are adjacent to each other, and A portion of the second layer that is electrically coupled to the second layer and a portion of the second layer that is electrically coupled to the first layer are overlapped in the same exposure area to form a pattern. A semiconductor device which is exposed. 18. A semiconductor device provided with a semiconductor integrated circuit comprising a field effect transistor, comprising: an active region of the field effect transistor, a gate electrode formed on the active region, the active region or the gate. A contact formed on an electrode, and a contact pad, which is a portion to which the contact is connected in a wiring connected to the active region or the gate electrode via the contact, are overlapped and patterned in the same exposure region. A semiconductor device which is exposed. 19. The semiconductor according to claim 18, wherein said contact pads are pattern-exposed by a charged particle beam, and portions of said wiring other than said contact pads are pattern-exposed by ultraviolet light. apparatus. 20. A semiconductor device provided with a semiconductor integrated circuit comprising a bipolar transistor, comprising: a collector region of the bipolar transistor; a base region and an emitter region formed on the collector region;
A contact formed on the collector region, the base region or the emitter region, and the contact in a wire connected to the collector region, the base region or the emitter region via the contact is connected A contact pad, which is a part of the semiconductor device, which is pattern-exposed in the same exposure area. 21. The method according to claim 2, wherein the fourth contact pad is pattern-exposed with a charged particle beam, and a portion of the wiring other than the contact pad is pattern-exposed with ultraviolet light.
0. The semiconductor device according to 0. 22. A semiconductor device provided with a semiconductor integrated circuit having a multilayer wiring structure, wherein the multilayer wiring structure includes at least a first wiring and a second wiring connected via a via, and A first via pad connected to the via in the first wiring, the via, and a second via connected to the via in the second wiring;
Wherein the via pad is subjected to pattern exposure in the same exposure area. 23. The first via pad and the second via pad are pattern-exposed by a charged particle beam, and a portion of the first wiring other than the first via pad and the second wiring of the second wiring. 23. The semiconductor device according to claim 22, wherein a portion other than the second via pad is pattern-exposed with ultraviolet light. 24. A semiconductor device provided with a semiconductor integrated circuit including a field effect transistor, wherein a gate electrode formed on an active region of the field effect transistor is divided on the active region to perform pattern exposure. A semiconductor device characterized by not being performed. 25. A semiconductor device including a semiconductor integrated circuit including a field effect transistor, wherein an active region of the field effect transistor has a center of gravity of a figure corresponding to the active region among the plurality of exposure regions. The gate electrode logic is a portion of the gate electrode formed on the active region, which is pattern-exposed in one exposure region including the virtual active region in which the dimension of the active region is largely corrected by a predetermined length. The product portion is pattern-exposed in the one exposure region, and the gate electrode difference portion that is a portion of the gate electrode that does not overlap with the virtual active region is the pattern of the gate electrode logical product portion and the pattern of the gate electrode difference portion. In at least one of the plurality of exposure areas, the pattern is formed so that the pattern of the gate electrode is formed by joining the gate electrodes. A semiconductor device characterized by being subjected to turn exposure.