JPS62130525A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To execute etching for several times to the film or region provided by the same processing through dividing of semiconductor wafer surface in accordance with a number of times of etching and selective etching. CONSTITUTION:A semiconductor wafer 10 has a plurality of chips 20 which are separated by the scribe region. First, only the scribe region 11 in the vertical direction is etched and then the region 12 in the lateral direction is etched. Otherwise, the crossing part of scribe region is defined as the first etching region and the remaining part as the second region, or the region 31 is defined as the first etching region and the region 32 as the second etching region. In any case, etching is carried out using the resist mask by the photolithography technology. In case the film or region to be etched is SiO2 and the lower semiconductor substrate is Si, it is superior to detect the etching end point from the change from hydrophilicity to hydrophobicity generated at the interface of them but it is possible to employ the observation means by an optical means. With this structure, the etching end point of film provided by the same process during manufacture of IC, for example, SiO2 can be detected easily in every time.

Description

[Detailed Description of the Invention] [Summary] For example, the BIC cell and MO8F'EF' described in detail below
Disclosed is a method for manufacturing semiconductor integrated circuits such as FROM (field effect transistor) and other semiconductor integrated circuits.

In the fabrication of such semiconductor integrated circuits, films or regions formed in the same process, for example, 5IO2IO2 films, are often removed by repeating two or more etching steps. According to the present invention, the end point of such etching can be accurately, simply and easily detected each time.

[Industrial application field]

The present invention relates to a method of manufacturing semiconductor integrated circuits such as BICPROM and others. In other words, the present invention relates to a method for manufacturing a semiconductor integrated circuit that includes all steps of removing a film or region formed in the same process by etching multiple times.

[Conventional technology]

It is a well-known fact that etching is one of the processing techniques for manufacturing semiconductor integrated circuits. The finer the holes and turns in the integrated circuit being manufactured, the more elaborate the etching process must be.
The end point is also accurately detected by observing with the naked eye the change in properties from hydrophilic to hydrophobic. This is because, for example, an oxide film such as 5LO2 exhibits hydrophilicity, and the underlying Si substrate exhibits hydrophobicity (water repellency). It glues well, but on the other hand, is the latter water? This is because it repels. Since this detection method is very simple, it is often used in etching processes.

[Problem that the invention seeks to solve]

The etching end point detection method described above can be used without any problems if films or regions formed in the same process are removed by one etching. However, recently, as setan has become more complex,
Removal of a film or region formed by the same process by etching it twice or more, e.g., by etching part of the film or region in the first time and the remaining part in the second time. There are many opportunities to do so. In such a case, the end point of the first etching can be detected based on the change in the scribe area, so there is no problem, but if the scribe area is used to detect the end point of the first etching, Detection of the end point of the second and subsequent etchings becomes a problem. Conventionally,
It is common practice to detect the end point of the second etching by performing a complete microscopic examination of the contact hole formed by the etching. however,
In this end point detection method, in addition to the complicated inspection itself, it is difficult to evaluate whether or not etching is being performed reliably.

Therefore, if you perform all etching multiple times now, 2
It is desired to provide a method that makes it possible to reliably and easily detect the end point of etching from the second etching.

[Means to solve all problems]

In view of the above-mentioned problem of detecting the end point of etching during the manufacture of semiconductor integrated circuits, according to the present invention, when the entire film or region formed in the same process is removed by etching multiple times, the etching rate is adjusted according to the number of times of etching. 1 no \'s Suguwia Raishi; ・ Sochinku 7 initial area 112 ri ・ Nuri no 1 ma 6 each area expansion 'E 'laM f'" 7-? This problem can be solved by a method for manufacturing semiconductor integrated circuits, which is characterized by the following characteristics:

In carrying out the present invention, when the film or region to be etched is S+02 and the underlying semiconductor substrate is Si, the end point of etching is detected by the change from hydrophilicity to hydrophobicity that occurs at the interface between the two. It is recommended that Of course, in some cases, it is also possible to detect the end point of etching by observing the scribe area using an optical means such as a microscope, rather than observing the change from hydrophilicity to hydrophobicity.

In the present invention, as described above, the scribe area of the semiconductor wafer is divided into a plurality of portions depending on the number of etching operations. Therefore, when starting etching, the selected areas other than the area to be etched must be protected in some way from etching. Other parts can be advantageously protected by using a resist mask according to commonly used photolithography techniques.

〔Example〕

The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a partial plan view of a wafer showing a preferred embodiment of the present invention. As shown, a semiconductor wafer 10
Is it multiple ticks 7°20? A scribe area shown by diagonal lines exists between adjacent chips. In this example, only the vertical scribe area (first etch area) 11 is etched in the first etching, and the remaining area (horizontal scribe area; second etch area) 11 is etched in the second etching.
Etch 2.

FIG. 2 is a partial plan view of a wafer illustrating another preferred embodiment of the invention. As shown in the figure, the intersecting portion of the scribe area constitutes a first etch area 21, and the remaining portion constitutes a second etch area 22.

Furthermore, unlike the above-described examples of etch area distribution shown in FIGS. 1 and 2, it is also possible to entirely adopt a special etch area distribution as shown in FIG. In this example, reference number 3
1 indicates the first etching area and reference number 32 indicates the second etching area.
Shows the erotic area.

Next, the method of the present invention will be explained by taking as an example the manufacture of a FROM cell (BICPROM) having a BIC cell.

Before that, let me briefly explain the BIC cell.

The present inventors first discovered that the breakdown of an insulator
We have developed a new type of programmable cell using BIC cells (Breakdown-of-In
sulator-for-Conduction Ce
1l) and the named digit. It is effective for reducing programming time on BIC'IC, and is also effective for reducing programming time, for example, on MOSF
Easily combine with ET to create FROM cells and FRO
M cell arrays can be manufactured. BIC cell is
It consists of a thin insulating film that covers the contact region formed on the n-diffusion layer on the surface of the semiconductor element substrate, and a metal wiring such as aluminum (for example) is formed on the surface of this insulating film.
electrodes) are connected. In this BIC cell, the n-diffusion layer and the electrode are isolated before programming, but when a write voltage is applied externally at the start of programming, breakdown of the insulating film is caused. The diffusion layer and the electrode are connected, thus allowing desired programming.

In manufacturing a FROM cell having a BIC cell, it is first necessary to form a transistor, so the Si substrate 1
Formation of selective field oxide film (5T02 film) 2 on top, formation of dirt oxide film, dirt electrode (PolySl) 4, formation of self-aligned source layer and drain layer,
After forming an insulating film (PSG film) 3 by the CVD method and forming contact holes 13a and 13b by removing the PSG film only on the source and drain layers, the device structure as shown in the cross section in FIG. 4 is created. Obtained. The PSG film 3 is made of C
A film having a thickness of 1 .mu.m was formed by VD method, and the contact holes 13a and 13be were formed by dry etching the entire film.

Next, oxidation was performed at 900°C in a dry state to reduce the film thickness to 6.
Oxide films (5102) 23a and 23b of 00X were grown in the contact holes (see FIG. 5).

Next, only 231 L of the 8102 membrane in the BIC cell formation portion was removed by etching with an aqueous solution of total hydrofluoric acid (HF).

A new contact hole 33 was formed (see FIG. 6).

In detail, this contact hole was formed through the following steps: resist application, removal of the etched portion from the resist film (development), etching with an aqueous solution of hydrofluoric acid, and removal of the remaining resist film. The end point of this etching was detected in FIG. 3 when the first etched region 31 changed from hydrophilic to hydrophobic (exposing the Si substrate 1).

Subsequently, as shown in FIG. 7, a Po1ySi film 5 and its thermally oxidized film (SiO□) 6 were sequentially formed. A detailed explanation of this process is as follows: First, P
o1y Si film 5''lr: c' Film thickness 100 by VD method
It was grown doped to 0X. Next, arsenic (Aa) ions were implanted at a t-acceleration voltage of 40 keV.

Next, the ion-implanted As was heated at 90°C in a nitrogen atmosphere.
Drive-in was performed by annealing at 0° C. for 30 minutes. Further, the A3-doped Pa1ySi film 5 was turned by 74 times by dry etching.

Finally, complete thermal oxidation was performed at 850° C. using Dry 02 to form a thermal oxide film (s+o2) 6t−.

After forming the insulating film in the BIC cell formation area as described above, the SiO film 23b as a stone/plate in the other cell formation area is removed in the same manner as the removal of the SiO □ film 23a in FIG. 6 above. It was removed by etching with an aqueous acid solution. A new contact hole 43 was formed (see FIG. 8). Note that the end point of etching in this case is the second etching area 32.
(Figure 3) was detected by changing from hydrophilic to hydrophobic.

Finally, follow the normal wiring method and connect the aluminum <ht>
The At wiring 7a is deposited by sputtering to a thickness of 1.0 μm, and then patterned.
and 7b (Fig. 9) were formed. FIG. 9 is a cross-sectional view of a FROM cell having a BIC cell according to the present invention.

〔Effect of the invention〕

According to the present invention, during the manufacture of semiconductor integrated circuits, the end point detection of all etching can be carried out accurately, easily, and simply using only the entire scribe area.

Furthermore, according to the present invention, it is possible to detect the end point using optical means such as a microscope, so the total inspection time can be significantly shortened. Therefore, according to the present invention, throughput can be increased and manufacturing costs can be reduced.

[Brief explanation of drawings]

1, 2 and 3 are partial plan views showing a preferred embodiment of the invention, and FIGS. 4 to 9 show an example of the method of the invention in full order. FIG. In the figure, 10 is a wafer, 11 is a first etch area, 12 is a second etch area, and 2o is a chip.

Claims (1)

[Claims] 1. In the process of manufacturing a semiconductor integrated circuit, when a film or region formed in the same process is removed by multiple etchings, the scribe line of the semiconductor wafer is etched according to the number of etchings. A method for manufacturing a semiconductor integrated circuit characterized by dividing a region and selectively etching each division each time. 2. When the film or region to be etched is SiO_2 and the underlying semiconductor substrate is Si, the end point of etching is detected by the change from hydrophilicity to hydrophobicity that occurs at the interface between the two. The manufacturing method described in Scope 1.