JPH0653493A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having gate electrode formed on a semiconductor substrate through a gate oxide in which degradation of withstand voltage is prevented while preventing deformation of gate by forming the gate electrode in such structure as crossing an active region obliquely. CONSTITUTION:In a MOS transistor structure of semiconductor device, gate electrode 2 thereof is formed to ride on an isolation region 3 continuously while crossing with an active region 1 at an angle of 45 deg.. The gate electrode 2 has such size as increasing gradually from a part corresponding with the active region 1 toward the isolation region 3, and a source 4 and a drain 5 are formed on the opposite sides of the gate electrode 2 in the active region 1. This constitution suppress concentration of field at a crossing part in PN junction formed by the active region 1 and underlying substrate region thus preventing degradation of withstand voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to alleviate an electric field at a crossing portion of a gate electrode and an active region in a MOS (Metal Oxide Semiconductor) type transistor structure and suppress deterioration of breakdown voltage. At the same time, it relates to a semiconductor device in which a defective shape of a gate is prevented.

[0002]

2. Description of the Related Art Conventionally, LSI (Large Scale Integration)
Submicron size devices have been developed and are being used with the miniaturization of ated circuits. Such a fine L
In the SI MOS type transistor, its shape has a great influence on the characteristics of the MOS type transistor.

In general, the gate electrode of the MOS transistor is formed in a state of continuously riding on the element isolation region (LOCOS region) and has a structure intersecting the active region at a right angle. The source region and the drain region are determined by the end of the element isolation region and the end of the gate electrode. That is, the source and the drain are formed so as to intersect the gate electrode at a right angle.

[0004]

However, the above-mentioned M
In the OS type transistor structure, since the gate electrode and the active region intersect at a substantially right angle, an electric field concentrates at this intersection at the PN junction formed by the active region and the lower substrate region, and the breakdown voltage deteriorates. There was a problem of causing. In addition, since the gate electrode continuously runs from the active region to the element isolation region at the intersection, the gate electrode is easily affected by the step difference in the photoresist process (patterning process) of the gate electrode. However, there is a problem that it causes a defect such as a thin shape.

An object of the present invention is to solve such a problem and to alleviate the electric field at the intersection of the gate electrode and the active region to suppress the deterioration of breakdown voltage and the shape of the gate. An object is to provide a semiconductor device in which defects are prevented.

[0006]

To achieve this object, the present invention provides a semiconductor device having a structure in which a gate electrode is formed on a semiconductor substrate via a gate oxide film, wherein the gate electrode is active. It is intended to provide a semiconductor device having a structure that diagonally intersects a region.

The present invention provides a semiconductor device characterized in that the intersection angle is 45 degrees.

[0008]

According to the present invention, since the gate electrode and the active region are diagonally intersected with each other, it is possible to prevent the electric field from being concentrated at the intersection at the PN junction formed by the active region and the lower substrate region. Therefore, it is possible to prevent the breakdown voltage from deteriorating. Further, the gate electrode has a shape in which the size in the vicinity of the element isolation region is larger than the size of the portion corresponding to the active region. Therefore, it is possible to reduce the thinning of the gate electrode caused by the step difference between the element isolation region and the active region, which has occurred in the photoresist process performed when patterning the gate electrode.

Further, by setting the intersection angle between the gate electrode and the active region to be 45 degrees, it is possible to more efficiently suppress the concentration of the electric field at the intersection portion, and to prevent the breakdown voltage from further deteriorating. be able to.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment according to the present invention will be described with reference to the drawings. 1 is a plan view showing a MOS type transistor structure of a semiconductor device according to the present invention, and FIGS. 2 and 3 are partial cross-sectional views showing steps of manufacturing the MOS type transistor structure of the semiconductor device shown in FIG. , A- in FIG.
The A section is shown.

The gate electrode 2 of the MOS type transistor structure of the semiconductor device shown in FIG. 1 is formed in a state of continuously riding on the element isolation region 3, and has a structure intersecting the active region 1 at an angle of 45 degrees. Have That is, the gate electrode 2 has a shape in which the size in the vicinity of the element isolation region 3 gradually becomes thicker toward the element isolation region 3 than the size of the portion corresponding to the active region 1. A source 4 and a drain 5 are formed on the left and right sides of the active region 1 with the gate electrode 2 interposed therebetween.

Next, the MO of the semiconductor device having this structure
The manufacturing process of the S-type transistor structure will be described. In the step shown in FIG. 2, the semiconductor substrate 11 is subjected to a known selective oxidation technique, and the element isolation region 3 of the semiconductor substrate 11 is
The field oxide film 12 is formed, and the active region 1 and the element isolation region 3 are separated. Then, the semiconductor substrate 11 of the active region 1 is exposed.

Next, in the step shown in FIG. 3, the semiconductor substrate 11 obtained in the step shown in FIG. 2 is thermally oxidized to form a film having a thickness of 20 to 20 on the semiconductor substrate 11 and the field oxide film 12.
An oxide film of about 200Å is formed. Then, a polycrystalline silicon film having a film thickness of about 1000 to 5000 Å is deposited on the oxide film by a CVD (Chemical Vapor Deposition) method. Next, impurities are ion-implanted into the polycrystalline silicon film to reduce the resistance of the polycrystalline silicon film. Next, a photoresist film is applied on the polycrystalline silicon film and patterned to form a resist pattern for forming a gate electrode. At this time, the resist pattern is formed such that the gate electrode 2 to be formed later has the shape shown in FIG. Next, using the resist pattern as a mask, the polycrystalline silicon film and the oxide film are anisotropically etched to form the gate oxide film 13 and the gate electrode 2. Then, using the gate electrode 2 as a mask, impurities are ion-implanted, and then heat treatment is performed to form the source 4 and the drain 5.

In this way, the MOS type transistor shown in FIG. 1 was formed. Then, desired steps are performed to complete the semiconductor device. In this embodiment, as shown in FIG. 1, the intersection angle between the gate electrode 2 and the active region 1 is set to 45 degrees, but the present invention is not limited to this, and the gate electrode 2 and the active region 1 intersect obliquely. You can do it.

Further, in the present embodiment, the gate electrode 2 is formed by using the polycrystalline silicon film, but the present invention is not limited to this, and the gate electrode can be formed without affecting the performance of the gate electrode. Of course, other materials may be used as long as they are materials.

[0016]

As described above, since the semiconductor device according to the present invention has a structure in which the gate electrode and the active region are obliquely intersected with each other, the PN junction formed from the active region and the underlying substrate region is formed. In the above, it is possible to prevent the electric field from concentrating at this crossing portion and prevent the breakdown voltage from deteriorating. Further, since the gate electrode has a shape in which the size in the vicinity of the element isolation region is thicker than the size of the portion corresponding to the active region, the gate caused by the step difference between the element isolation region and the active region is formed. It is possible to reduce the thinness of the electrodes. As a result, it is possible to provide the semiconductor device in which the electric field at the intersection of the gate electrode and the active region is relaxed, the breakdown voltage is suppressed from being deteriorated, and the defective shape of the gate is prevented.

Further, by setting the intersection angle between the gate electrode and the active region to be 45 degrees, it is possible to more efficiently suppress the concentration of the electric field at the intersection portion, and prevent the breakdown voltage from further deteriorating. You can

[Brief description of drawings]

FIG. 1 is a plan view showing a MOS type transistor structure of a semiconductor device according to the present invention.

2 is a partial cross-sectional view showing a process of manufacturing a MOS type transistor structure of the semiconductor device shown in FIG.

FIG. 3 is a partial cross-sectional view showing a process of manufacturing a MOS transistor structure of the semiconductor device shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Active region 2 Gate electrode 3 Element isolation region 4 Source 5 Drain 11 Semiconductor substrate 12 Field oxide film 13 Gate oxide film

Claims (2)

[Claims] 1. A semiconductor device having a structure in which a gate electrode is formed on a semiconductor substrate via a gate oxide film, wherein the gate electrode has a structure diagonally intersecting an active region. . 2. The semiconductor device according to claim 1, wherein the intersecting angle is 45 degrees.