JPS6058644A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6058644A
JPS6058644A JP16785183A JP16785183A JPS6058644A JP S6058644 A JPS6058644 A JP S6058644A JP 16785183 A JP16785183 A JP 16785183A JP 16785183 A JP16785183 A JP 16785183A JP S6058644 A JPS6058644 A JP S6058644A
Authority
JP
Japan
Prior art keywords
layer
electrode
film
substrate
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16785183A
Other languages
Japanese (ja)
Inventor
Toru Mochizuki
徹 望月
Takeshi Tanaka
剛 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP16785183A priority Critical patent/JPS6058644A/en
Publication of JPS6058644A publication Critical patent/JPS6058644A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain the titled device of small parasitic capacitance by a method wherein a contact electrode and a gate electrode are composed of the structure of lamination of a polycrystalline Si layer containing an impurity in the lower layer and a metallic film or a metal silicide layer in the upper layer, and an inner wiring electrode is composed of the structure of lamination of a polycrystalline Si layer containing no impurity in the lower layer and a metallic layer of the same condition in the upper layer. CONSTITUTION:A thick field oxide film 2 for element isolation is formed in the periphery of a P type Si substrate 1, and a thin gate oxide film 7 is adhered to the substrate surface surrounded by that film. Next, the gate electrode 5 is provided at the center of the surface of the film 7. At this time, the electrode 5 is composed of the structure of lamination of the As-doped polycrystalline Si layer 41 of the lower layer and the TaSi2 layer 3 of the upper layer. Besides, the contact electrode 12 mounted on N type source and drain regions 8 and 9 provided on both sides of the layers is put in the same structure, and the inner wiring electrode 6 positioned above the film 2 and intersecting rectangularly to those is composed of a non-doped polycrystalline Si layer 42 of the lower layer and the same TaSi2 layer of the upper layer.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、配線技術を改良した半導体装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device with improved wiring technology.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

周知の如く、半導体装置例えばMO8型トランジスタに
おいては、基板表面のソース、ドレイン領域と接続する
コンタクト電極や基板上に素子分離領域を介して設けら
れた内部配線電極等の材料として、At等に代って下層
が不純物をドープした多結晶シリコンで、上層がAt等
の金属又は金属硅化物からなる積層構造のものが用いら
れている。なお、下層に多結晶シリコンを用いる理由と
しては、At等の金属が直接基板と接触すると熱処理時
に基板につきぬが生ずるからである。
As is well known, in semiconductor devices such as MO8 type transistors, At and the like are used as materials for contact electrodes connected to the source and drain regions on the substrate surface, internal wiring electrodes provided on the substrate through element isolation regions, etc. A laminated structure in which the lower layer is made of polycrystalline silicon doped with impurities and the upper layer is made of a metal such as At or metal silicide is used. The reason why polycrystalline silicon is used for the lower layer is that if a metal such as At comes into direct contact with the substrate, it will stick to the substrate during heat treatment.

しかしながら、従来のMOS i )ランノスタによれ
ば、内部配線電極の下層の材料として不純物をドープし
た多結晶シリコンが用いられているため、素子分離領域
等を介して上記電極と基板の間の寄生容量が大きくなる
という欠点を有する。しかるに、寄生容量を低下させる
ことは、近年ICの高集積化に伴って動作スピードを向
上させるために、配線電極の低抵抗化のみならず大きな
技術的な課題となっている。
However, according to the conventional MOS i) runnostar, since polycrystalline silicon doped with impurities is used as the material for the lower layer of the internal wiring electrode, parasitic capacitance between the electrode and the substrate is generated via the element isolation region, etc. It has the disadvantage that it becomes large. However, reducing the parasitic capacitance has become a major technical issue, as well as reducing the resistance of wiring electrodes, in order to improve the operating speed as ICs have become highly integrated in recent years.

このようなことから、寄生容量を低下させる手段として
層間の絶縁膜を厚くすることが考えられるが、かかる場
合、コンタクトホールの加工の場合にみられるようにそ
の加工精度に難点を有するため、絶縁膜を厚くすること
には限界がある。
For this reason, it is conceivable to increase the thickness of the insulating film between the layers as a means of reducing parasitic capacitance, but in such a case, there is a problem with the processing accuracy as seen in the case of contact hole processing, so it is difficult to insulate There is a limit to how thick the film can be.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、コンタクト
電極やダート電極を低抵抗化して高速化を図ることは勿
論のこと、基板上に絶縁膜を介して設けられる内部配線
電極の寄生容量を低下し得る半導体装置を提供すること
を目的とするものである。
The present invention has been made in view of the above circumstances, and it is possible to reduce the resistance of contact electrodes and dirt electrodes to increase speed, as well as reduce the parasitic capacitance of internal wiring electrodes provided on the substrate via an insulating film. It is an object of the present invention to provide a semiconductor device that can be degraded.

〔発明の概要〕[Summary of the invention]

本発明は、コンタクト電極及びゲート電極を下層が不純
物を含む多結晶シリコン層でかつ上層が金属膜又は金属
硅化物層からなる積層構造とし、内部配線電極を下層が
不純物を含まない多結晶シリコン層でかつ上層が金属層
又は金属硅化物層からなる積層構造とすることによって
、前述の目的を達成することを図ったことを骨子とする
ものである。
In the present invention, the contact electrode and the gate electrode have a stacked structure in which the lower layer is a polycrystalline silicon layer containing impurities and the upper layer is a metal film or metal silicide layer, and the internal wiring electrode is formed of a polycrystalline silicon layer containing no impurities as the lower layer. The main idea is to achieve the above-mentioned object by forming a laminated structure in which the upper layer is a metal layer or a metal silicide layer.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例に係るMO8型トランジスタを
、製造方法を併記しつつ第1図〜第3図を参照して説明
する。
Hereinafter, an MO8 type transistor according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3, along with a manufacturing method.

まず、半導体基板としてのP型のSt基板1の所定の表
面に、常法により素子分離領域としてのフィールド酸化
膜2、熱酸化膜(図示せず)を順次形成した。つづいて
、全面に膜厚2000Xの多結晶シリコン層(図示せず
)を形成した後、全面に7オトンジスト膜を塗布、乾燥
し、写真蝕刻法によpc−ト電極形成予定部に対応する
フォトレジスト膜を選択的に除去し、レジストパターン
(図示せず)を形成した。次いで、このレジストパター
ンをマスクとして前記多結晶シリコン層に砒素を加速電
圧40keV、ドーズ 。
First, a field oxide film 2 as an element isolation region and a thermal oxide film (not shown) were sequentially formed on a predetermined surface of a P-type St substrate 1 as a semiconductor substrate by a conventional method. Subsequently, after forming a polycrystalline silicon layer (not shown) with a film thickness of 2000X on the entire surface, a 7-tone resist film was coated on the entire surface, dried, and photolithography was performed to form a photolithography layer corresponding to the area where the PC electrode was to be formed. The resist film was selectively removed to form a resist pattern (not shown). Next, using this resist pattern as a mask, arsenic was dosed onto the polycrystalline silicon layer at an accelerating voltage of 40 keV.

量3X1015/1yn2の条件でイオン注入した。ひ
きつづき、レジストパターンを除去した後、全面に膜厚
3000XのTaSi2層(図示せず)を形成した。更
に、このTaSi2層上に所定の形状のレジストパター
ンを形成し死後、このレジス) Aターンをマスクとし
てTaSi2層、多結晶シリコン層を順次エツチング除
去し、Ta512パターン3と砒素をドーグした多結晶
シリコンパターン41からなるダート電極5、及びこの
ダート電極5に接続したTaSi2パターン3と砒素を
ドーグしない多結晶シリコンパターン42からなる第1
の内部配線電極6を形成した。この後、ダート電極5を
マスクとして前記熱酸化膜を選択的に除去し、ダート絶
縁膜7を形成した。
Ion implantation was carried out under conditions of an amount of 3×1015/1yn2. Subsequently, after removing the resist pattern, a 3000× thick TaSi layer (not shown) was formed on the entire surface. Furthermore, a resist pattern of a predetermined shape was formed on this TaSi2 layer, and after death, the TaSi2 layer and the polycrystalline silicon layer were sequentially etched away using the A turn as a mask, and the Ta512 pattern 3 and the polycrystalline silicon doped with arsenic were removed. A dirt electrode 5 consisting of a pattern 41, and a first electrode consisting of a TaSi2 pattern 3 connected to the dirt electrode 5 and a polycrystalline silicon pattern 42 which does not contain arsenic.
An internal wiring electrode 6 was formed. Thereafter, the thermal oxide film was selectively removed using the dirt electrode 5 as a mask to form a dirt insulating film 7.

次に、前記ダート電極5等をマスクとして基板I K 
n型不純物をイオン注入し、N型のソース、ドレイン領
域8,9を形成した。つづいて、熱酸化処理を施して基
板1上に酸化膜(図示せず)を形成し、全面に厚さ5o
oo1ocvpsio2膜10を被着した後、PEP法
によシソース、ドレイン領域8.9の一部に対応するC
VD S 102 iloを開孔し、コンタクトホール
11.llf診成した。次いで、全面に厚さ1000X
の多結晶シリコン層を堆積した後、前記と同様にしてソ
ース領域8と接続する多結晶シリコン層部分に砒素をイ
オン注入した。更に、全面に厚さ8000XのAt層を
被着後、このAt層及び多結晶シリコン層を適宜ノ母タ
ーニングし、ソース領域8にコンタクトホール1ノを介
して接続するコンタクト電極ノ2、及びこのコンタクト
電極12に接続した第2の内部配線電極13を形成した
Next, using the dirt electrode 5 etc. as a mask, the substrate IK
N type impurities were ion-implanted to form N type source and drain regions 8 and 9. Subsequently, a thermal oxidation treatment is performed to form an oxide film (not shown) on the substrate 1 to a thickness of 50 mm over the entire surface.
After depositing the oo1ocvpsio2 film 10, a C layer corresponding to part of the source and drain regions 8.9 is formed by PEP method.
VD S 102 ilo is opened and contact hole 11. llf was diagnosed. Next, the entire surface is coated with a thickness of 1000X.
After depositing the polycrystalline silicon layer, arsenic ions were implanted into the portion of the polycrystalline silicon layer connected to the source region 8 in the same manner as described above. Furthermore, after depositing an At layer with a thickness of 8000× on the entire surface, this At layer and the polycrystalline silicon layer are properly turned to form a contact electrode 2 which is connected to the source region 8 through the contact hole 1, and this. A second internal wiring electrode 13 connected to the contact electrode 12 was formed.

ここで、コンタクト電極12は砒素をドープし7’c多
結sl+シリコンパターン141 と11パターン15
とからなシ、内部配線電極13は砒素をドープしない多
結晶シリコンパターン142 とAtノやターン15と
からなってMO8型トランジスタが製造された(第1図
〜3図図示)。
Here, the contact electrode 12 is doped with arsenic and has a 7'c multi-connected SL+silicon pattern 141 and an 11 pattern 15.
In other words, the internal wiring electrode 13 was made up of a polycrystalline silicon pattern 142 not doped with arsenic and an At oxide turn 15, and an MO8 type transistor was manufactured (as shown in FIGS. 1 to 3).

本発明に係るMO8型トランジスタは、第1図〜3図に
示す如く、P型のSi基板1表面にN+型のソース、ド
レイン領域8.9を設け、基板1上にソース、ドレイン
領域8,9の一部に夫夫接続した下層が砒素をドーグし
た多結晶シリコンパターン15.で上層カAtz#ター
ン15からなる2層構造のコンタクト電極12を設け、
同基板1上にダート絶縁膜7を介して下層が砒素をドー
グしない多結晶シリコンノやターン51で上層がTaS
 i 2パターン3からなる2層構造のダート電極6を
設け、同基板1上にフィールド酸化膜2、CVD5i0
2膜IQを介して下層が砒素をドープしない多結晶シリ
コンノやターン142で上層がAtパターン15からな
る2層構造の内部配線電極6,13を設けた構造となっ
ている。
As shown in FIGS. 1 to 3, the MO8 type transistor according to the present invention has an N+ type source and drain region 8.9 provided on the surface of a P type Si substrate 1, and a source and drain region 8.9 provided on the substrate 1. A polycrystalline silicon pattern 15 whose lower layer is doped with arsenic is connected to a part of the polycrystalline silicon pattern 15. A contact electrode 12 having a two-layer structure consisting of an upper layer Atz# turn 15 is provided,
On the same substrate 1, the lower layer is made of polycrystalline silicon which does not contain arsenic through the dirt insulating film 7, and the upper layer is made of TaS with a turn 51.
A dirt electrode 6 with a two-layer structure consisting of two patterns 3 is provided, and a field oxide film 2 and a CVD5i0 are formed on the same substrate 1.
The internal wiring electrodes 6 and 13 have a two-layer structure in which the lower layer is a polycrystalline silicon pattern 142 not doped with arsenic and the upper layer is an At pattern 15 via two films IQ.

しかして、本発明によれば、ダート電極5及びコンタク
ト電極12の下層に夫々砒素をドープした多結晶シリコ
ンパターン’1*141 を設けることで前記電極5.
12の低抵抗化を図シ、もって素子の高動速化を達成で
きる。また、第1、第2内部配線電極6,130下層に
夫々砒素をドープしない多結晶シリコンパターン42.
142を設けることによシ、該パターン42.14.を
そのまま誘電体もしくは絶縁体として用いることができ
るため、その比抵抗を従来技術によるそれと同様に保ち
ながら寄生容量を低下できる。
According to the present invention, the electrodes 5.
By lowering the resistance of 12, it is possible to achieve higher operating speed of the element. Furthermore, a polycrystalline silicon pattern 42 which is not doped with arsenic is formed below the first and second internal wiring electrodes 6 and 130, respectively.
142, the patterns 42.14. Since it can be used as a dielectric or an insulator as it is, the parasitic capacitance can be reduced while keeping its specific resistance similar to that of the prior art.

なお、上記実施例では、コンタクト電極及びダート電極
の上層の材暫がTas i 9である場合について述べ
たが、(−の金属硅化 物でもよいし、At等の金属を用いてもよい。
In the above embodiment, the material of the upper layer of the contact electrode and the dirt electrode is Tas i 9, but it may be a negative metal silicide or a metal such as At.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く本発明によれば、コンタクト電極やダ
ート電極を低抵抗化して高速動作化を図るとともに、内
部配線電極の寄生容量を低下し得る半導体装置を提供で
きるものである。
As described in detail above, according to the present invention, it is possible to provide a semiconductor device in which the resistance of contact electrodes and dirt electrodes is reduced to achieve high-speed operation, and the parasitic capacitance of internal wiring electrodes can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に係るMO8型トランジスタ
の平面図、第2図は第1図のX−X線に沿う断面図、第
3図は第1図のY−Y線に沿う断面図である。 1・・・P型のSt基板(半導体基板)、2・・・フィ
ールド酸化膜(素子分離領域)、3・・・TaSi2 
/’ターン、41+141 ・・・砒素をドーグした多
結晶クリコンパターン、42r142・・・砒素をドー
グしない多結晶シリコンパターン、5・・・ダート電極
、6.13・・・内部配線電極、7・・・ダート+十 絶縁膜、8・・・N型のソース領域、9・・・N型のド
レイン領域、10・・・CVD5I021[,11・”
コンタクトホール、12・・・コンタクト電極、15・
・・Atノリーン。
FIG. 1 is a plan view of an MO8 type transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line X-X in FIG. 1, and FIG. 3 is a cross-sectional view taken along line Y-Y in FIG. 1. FIG. 1... P-type St substrate (semiconductor substrate), 2... Field oxide film (element isolation region), 3... TaSi2
/' turn, 41+141...Polycrystalline silicon pattern doped with arsenic, 42r142...Polycrystalline silicon pattern not doped with arsenic, 5...Dart electrode, 6.13...Internal wiring electrode, 7...・Dirt+10 insulating film, 8...N-type source region, 9...N-type drain region, 10...CVD5I021[,11・''
Contact hole, 12... Contact electrode, 15.
...At Noreen.

Claims (1)

【特許請求の範囲】[Claims] 表面に拡散層を有する半導体基板と、この基板上に前記
拡散層と接続するように設けられたコンタクト電極と、
同基板上にダート絶縁膜、素子分離領域を夫々介して設
けられたダート電極及び内部配線電極とを具備する半導
体装置において、コンタクト電極及びダート電極を下層
が不純物を含む多結晶シリコン層でかつ上層が金属層又
は金属硅化物層からなる積層構造とし、内部配線電極を
下層が不純物を含まない多結晶7リコン層でかつ上層が
金属層又は金属硅化物層からなる積層構造とすることを
特徴とする半導体装置。
a semiconductor substrate having a diffusion layer on its surface; a contact electrode provided on the substrate to be connected to the diffusion layer;
In a semiconductor device comprising a dirt insulating film, a dirt electrode and an internal wiring electrode provided on the same substrate through an element isolation region, the contact electrode and the dirt electrode are formed of a polycrystalline silicon layer containing impurities as a lower layer and as an upper layer. has a laminated structure consisting of a metal layer or a metal silicide layer, and the internal wiring electrode has a laminated structure in which the lower layer is a polycrystalline 7-lion layer containing no impurities and the upper layer is a metal layer or a metal silicide layer. semiconductor devices.
JP16785183A 1983-09-12 1983-09-12 Semiconductor device Pending JPS6058644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16785183A JPS6058644A (en) 1983-09-12 1983-09-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16785183A JPS6058644A (en) 1983-09-12 1983-09-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6058644A true JPS6058644A (en) 1985-04-04

Family

ID=15857261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16785183A Pending JPS6058644A (en) 1983-09-12 1983-09-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6058644A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6317544A (en) * 1986-07-10 1988-01-25 Seiko Instr & Electronics Ltd Semiconductor device
JPS6328060A (en) * 1986-07-04 1988-02-05 シ−メンス、アクチエンゲゼルシヤフト Integrated circuit and manufacture of the same
JPH01230320A (en) * 1988-11-04 1989-09-13 Sanyo Electric Co Ltd Cooker

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6328060A (en) * 1986-07-04 1988-02-05 シ−メンス、アクチエンゲゼルシヤフト Integrated circuit and manufacture of the same
JPS6317544A (en) * 1986-07-10 1988-01-25 Seiko Instr & Electronics Ltd Semiconductor device
JPH01230320A (en) * 1988-11-04 1989-09-13 Sanyo Electric Co Ltd Cooker
JPH0380487B2 (en) * 1988-11-04 1991-12-25 Sanyo Electric Co

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