JPH0214561A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify a manufacturing process by a method wherein a source region and a drain region at a comparatively low impurity concentration are formed by using phosphorous or arsenic, ions are implanted by making use of only a gate electrode layer, a gate insulating film and a field insulating film as a mask. CONSTITUTION:The whole surface of a semiconductor substrate is coated with a resist material layer; after that, a patterning operation is executed in such a way that the resist material layer 7 is left in an active region inside an N-type well region and the upper part and the side of a gate electrode layer 6b inside a P-type region; after that, an etching operation is executed to form a mask; phosphorus or arsenic 8 is doped at a high concentration. Then, a source region 9 and one part of a drain region for an N-channel high breakdown-strength MOS transistor are formed. The resist material layer remaining on the surface of the semiconductor substrate is removed; phosphorus or arsenic 12 is doped shallow at a comparatively low concentration by using a mask composed of the following: a gate electrode layer 6a and a gate insulating film 5a inside the N-type well region; the gate electrode layer 6b, a gate insulating film 5b and a field insulating film 3 inside the P-type region. Then, a second region 13 and a drain region 14 for a high breakdown-strength MOS transistor are formed so as to be united with the source region 9 and the drain region 10, at a high concentration, which have been formed previously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device. More specifically, high-voltage MOS used in semiconductor integrated circuits)
The present invention relates to a method for manufacturing Lanlister.

[Summary of the Invention] The present invention provides an LDD (Lightly Doped) device having lightly doped drain and source regions.
In manufacturing a high-voltage N-type MO3) run lister with a drain) structure, when forming source and drain regions with relatively low impurity concentrations using phosphorus or arsenic, the gate electrode layer and gate insulating film are formed without using a mask made of resist material. The manufacturing process was simplified by implanting ions using only the field insulating film as a mask.

[Conventional technology]

An example of a method for manufacturing a high voltage MOS transistor having an LDD structure using a conventional technique will be described with reference to the drawings. Figure 2 (
al to +el are cross-sectional views in the order of steps in a conventional manufacturing method. After forming an N-type well region 22 on the surface of a P-type semiconductor substrate 21, a field insulating film 23 having an opening that becomes an active region is formed, and an active region is formed in each of the P-layer region and the N-type well region. After separating and forming, a gate insulating film 25 is formed on the surface of each active region.
Gate electrode layers 26a and 26 via a and 25b
b.

(FIG. 2(a)) After applying a resist material layer to the entire surface of the semiconductor substrate, a resist material layer 27 is left on the active region in the N-type well region and on the top and side surfaces of the gate electrode layer 26b in the P-layer region. After patterning, an etching process is performed as a mask, and phosphorus or arsenic 28 is deeply doped at a high concentration to form part of the source region 29 and drain region 30 of the high breakdown voltage MO3) run lister. (Figure 2 (bl
) Remove the resist material layer remaining on the surface of the semiconductor substrate, apply the resist material layer again to the entire surface of the semiconductor substrate, perform patterning so that the resist material layer 31 remains in the active region in the N-type well region, and then perform etching treatment. After that, using the resist material layer, the field insulating film 23, and the gate electrode Ji26b in the P-type head region as a mask, phosphorus or arsenic 32
A source region 33 and a drain region 34 of a high-voltage MOS transistor are formed by shallowly doping to a relatively low concentration so as to be integrated with the previously formed highly doped source region 29 and drain region 30.

(Second (C1) Remove the resist material layer remaining on the surface of the semiconductor substrate, apply the resist material layer again to the entire surface of the semiconductor substrate, and pattern it so that the resist material 1i36 remains in the active area in the P layer area. After etching, using the resist material layer 36, the field insulating film 23, and the gate electrode layer 26a in the N-type well region as a mask, boron 37 is doped at a high concentration to form the source region 38 and drain region of the P-type channel transistor. form 39.

(Second (dl) After removing the resist material layer remaining on the surface of the semiconductor substrate and depositing the eyebrow insulation W440, drilling the joint with the metal wiring by niche processing, and depositing the metal wiring material such as aluminum) , buttering and CMOS
I was using it as an IC. (Figure 2(e)) [Problems to be Solved by the Invention] As mentioned above, the conventional method for manufacturing a high-voltage MOS (MOS) run lister uses a resist to form a low-4 degree source region and a drain region. The process involved applying a material layer and patterning using photolithography. Therefore, the process for manufacturing a high-voltage Mos transistor has a disadvantage in that the number of steps is greater than that for manufacturing a normal MOS (MOS) run lister.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention has been developed to form low-concentration source and drain regions of a high-voltage MO3) run lister with an LDD structure without using a mask with a resist material layer. Impurities such as phosphorus and arsenic were doped using only the gate electrode layer, gate insulating film, and field insulating film in the N-type well region as masks.

The amount of phosphorus and arsenic implanted was 1013 or less per square hole.

[Effect]

The present invention provides an LD without using a mask using a cyst material layer.
Since the low-concentration source and drain regions of the high breakdown voltage MO3I-run lister of the D structure are formed, the steps of coating a resist material layer and patterning by photolithography can be omitted. Since the implantation voltage of phosphorus and arsenic is set to be less than 10'' per -square cII, the breakdown voltage of the transistor is 20V or more.

(Example〕 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 (al~(C1) is a cross-sectional view of the process order of the manufacturing method according to the present invention. After forming an N-type well region 2 on the surface of a P-type semiconductor substrate l, an opening that becomes an active region is formed. After forming a field insulating film 3 and forming active regions separately in an N-type well region and a P-type head region, gate electrode layers 6a and 6a are formed on the surface of each active region via gate insulating films 5a and 5b. 6b
will be established. (FIG. 1(a)) After applying a resist material layer to the entire surface of the semiconductor substrate, the resist material layer 7 is left on the active region in the N-type well region and on the top and side surfaces of the gate electrode 1ii6b in the P-type head region. After patterning and etching, the mask is used as a mask and deeply doped with phosphorus or arsenic 8 to form part of the source region 9 and drain region 10 of an N-channel type high breakdown voltage MOS transistor. (FIG. 1(b)), Although not shown in FIG. The source region and drain region of the channel type MO3) run lister are formed at the same time. The resist material layer remaining on the surface of the semiconductor substrate is removed, and the gate electrode layer 6a and gate insulating film 5a in the N-type well region, the gate electrode layer 6b and gate insulating film 5b in the P-type head region, and the field insulating film 3 are removed. As a mask, add 1 phosphorus or arsenic 12
A high breakdown voltage MO is doped to a relatively low level so as to have a concentration of 1O3 or less per square capillary, and is doped to a relatively low level so that it becomes one with the previously formed high concentration source region 9 and drain region 10.
3) Source region 13 and drain region 1 of the runlister
4 (FIG. 1(C)) A resist material layer is applied to the entire surface of the semiconductor substrate, patterned so that the resist material N16 remains in the active region within the P-type head area, and etched. 'i16, field insulating film 3, and gate electrode layer 6a in the N-type well region are used as masks, boron 17 is doped at a higher concentration than low concentration phosphorus or arsenic, and the source region 18 and drain region of the P-type channel transistor are doped. form 19.

In order to sufficiently lower the resistance of the source region 18 and drain region 19, the amount of boron doped is set at IQI per square hole.
It is preferable that it is s or more. (Fig. 1(d)) After removing the resist material layer remaining on the surface of the semiconductor substrate and depositing the glabellar insulating film 20, holes are made by etching at the joints with the metal wiring, and a metal wiring material such as aluminum is formed. After being deposited, it is patterned to form a CMO3IC. (Figure 1 (
e)) [Effects of the Invention] As described above, according to the present invention, a mask made of a resist material layer is not used when forming the low-concentration source region and drain region of the LDD structure high-voltage MOS (Run Lister). Impurities such as phosphorus and arsenic are doped using only the gate electrode layer, gate insulating film, and field insulating film in the P-type head region and N-type well region as masks, so that the coating of the resist material layer and the photo This has the advantage that the process of patterning using lithography can be omitted, and the manufacturing process can be performed in the US.

Furthermore, the amount of phosphorus and arsenic implanted into the low-concentration source and drain regions was set to less than 1 G'' per square cm, so the breakdown voltage of the transistor was 20 V or more.
It can operate safely with voltages required by ICs such as non-volatile memories.

[Brief explanation of the drawing]

FIG. 1 (al to fGl are cross-sectional views of the process order of the manufacturing method according to the present invention, and FIG. 2 (al to +el are cross-sectional views of the process order of the conventional manufacturing method.・ ・ ・ 5a, 5b, 6a, 6b, 7.16, P-type semiconductor substrate N, type well region, field insulating film, gate insulating film, gate electrode layer, resist material layer 812...phosphorus or arsenic9, 13.18... Source region 10, 14.19...Drain region 17...Boron 20...Interlayer insulating film

Claims (1)

What is claimed is: forming a well region having a conductivity type opposite to that of the semiconductor substrate on a surface of a semiconductor substrate of a first conductivity type; and a first active region arrangement portion in the well region and the well region. forming a field insulating film on the surface of the semiconductor substrate having first and second openings corresponding to second active region arrangement portions outside the region; A first gate electrode layer is formed on the active region arrangement part via a first gate insulating film, and a second gate insulating film is formed on the second active region arrangement part in the second opening. forming a second gate electrode layer through the semiconductor substrate; depositing a resist material layer on the upper surface of the semiconductor substrate so as to cover the first and second openings; and the first opening. etching the resist material layer so as to leave the resist material layer on the second gate electrode layer, on the source side and drain side side surfaces of the second gate electrode layer; , by selectively doping the surface of the semiconductor substrate with a first impurity that determines the opposite conductivity type at a high concentration and deeply using the remaining portion of the resist material layer and the field insulating film as a mask; forming opposite conductivity type regions for the source and drain with relatively high impurity concentration; and not masking the first and second openings before or after forming the opposite conductivity type regions for the source and drain. and the semiconductor substrate using the laminated portion of the first gate insulating film and the first gate electrode layer, the laminated portion of the second gate insulating film and the second gate electrode layer, and the field insulating film as a mask. By selectively doping the surface of the second impurity which determines the opposite conductivity type at a lower concentration than the first impurity and shallowly, the second impurity which determines the opposite conductivity type is integrally formed with the opposite conductivity type regions for the source and drain, respectively. forming opposite conductivity type regions for a source and drain with a relatively low impurity concentration on one side and the other side of the second gate electrode layer, respectively; A third impurity that determines the first conductivity type is added to the surface of the semiconductor substrate using the laminated portion of the first gate insulating film, the first gate electrode layer, and the field insulating film as a mask. A method for manufacturing a semiconductor device comprising the step of forming opposite conductivity type regions for a source and a drain on one side and the other side of the first gate electrode layer, respectively, by selectively doping at a high concentration.