KR100209738B1 - Semiconductor device structure and method - Google Patents

Semiconductor device structure and method Download PDF

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KR100209738B1
KR100209738B1 KR1019960048262A KR19960048262A KR100209738B1 KR 100209738 B1 KR100209738 B1 KR 100209738B1 KR 1019960048262 A KR1019960048262 A KR 1019960048262A KR 19960048262 A KR19960048262 A KR 19960048262A KR 100209738 B1 KR100209738 B1 KR 100209738B1
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well
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semiconductor device
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KR19980029028A (en
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백종학
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구본준
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 전력소비를 감소시키고 프로세스 스피드(Process Speed)를 개선할 수 있도록 한 반도체 소자의 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a structure and a manufacturing method of a semiconductor device capable of reducing power consumption and improving process speed.

이와같은 본 발명의 반도체 소자의 구조는 기판; 상기 기판내에 형성되는 제1도전형 웰과 제2도전형 웰; 상기 제1도전형 웰과 제2도전형 웰내에 각각 형성되는 소오스/드레인 불순물 영역; 상기 제1도전형웰 내에 형성되는 제1도전형 가드링 영역; 상기 제2도전형 웰내에 형성되는 제2도전형 불순물 영역을 포함하여 구성됨을 특징으로 한다.The structure of the semiconductor device of the present invention includes a substrate; A first conductivity type well and a second conductivity type well formed in the substrate; Source / drain impurity regions formed in the first conductivity type well and the second conductivity type well, respectively; A first conductive guard ring region formed in the first conductive well; And a second conductivity type impurity region formed in the second conductivity type well.

Description

반도체 소자의 구조 및 제조방법Structure and manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 전력소비를 감소시키고 프로세스 스피드(Process Speed)를 개선할 수 있도록 한 반도체 소자의 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a structure and a manufacturing method of a semiconductor device capable of reducing power consumption and improving process speed.

이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 구조를 설명하면 다음과 같다.Hereinafter, the structure of a conventional semiconductor device will be described with reference to the accompanying drawings.

제1도는 종래의 반도체 소자의 구조를 나타낸 구조단면도이다.FIG. 1 is a structural cross-sectional view showing the structure of a conventional semiconductor device.

제1도에 도시된 바와같이 반도체 기판(11)에 서로 접촉되도록 n-웰(12)과 p-웰(13)이 형성되고, 상기 n-웰(12)과 p-웰(13)내에는 각각 드레인 영역(14)과 소오스 영역(15)이 형성된다. 또한, 상기 p-웰(13)내에 드레인 영역(15)과 접촉되어 가드링(Guirding) 영역(16)이 형성된다.Well 12 and p-well 13 are formed so as to be in contact with each other on semiconductor substrate 11 as shown in FIG. 1, and n-well 12 and p-well 13 A drain region 14 and a source region 15 are formed. In addition, a guard ring region 16 is formed in the p-well 13 in contact with the drain region 15.

그러나 이와같은 종래의 반도체 소자에 있어서 다음과 같은 문제점이 있었다.However, such a conventional semiconductor device has the following problems.

즉, 파괴전압(Breakdown Voltage)의 보호를 위해 n-웰의 도즈(Dose)량을 증가할 수 없기 때문에 드리프트 영역(Drift Region)의 저항을 낮출 수 없고, 고유저항(Specific Resistance)값이 크다. 이로 인하여 소비전력이 높고, 오퍼레팅 스피드(Operating Speed)에 영향을 미친다.That is, since the dose amount of the n-well can not be increased in order to protect the breakdown voltage, the resistance of the drift region can not be lowered and the Specific Resistance value is large. As a result, the power consumption is high and affects the operating speed.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 드리프트 영역에 보다 높은 도핑(Doping)을 실시하여 집속(Concentration)을 증가시키도록 한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device in which concentration is increased by performing a higher doping in a drift region.

제1도는 종래의 반도체 소자의 구조를 나타낸 구조단면도.1 is a structural cross-sectional view showing the structure of a conventional semiconductor device;

제2도는 본 발명의 반도체 소자의 구조를 나타낸 구조단면도.FIG. 2 is a structural cross-sectional view showing the structure of a semiconductor device of the present invention. FIG.

제3a-제3d도는 본 발명의 반도체 소자의 제조방법을 나타낸 공정단면도.3 (a) -3 (d) is a process sectional view showing a method of manufacturing a semiconductor device of the present invention.

* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS

21 : P형 반도체 기판 22 : 제1감광막21: P-type semiconductor substrate 22: first photoresist film

23 : n-웰 24 : 제2감광막23: n-well 24: second photosensitive film

25 : p-웰 26 : 제3감광막25: p-well 26: third photosensitive film

27 : 드레인 불순물 영역 28 : 소오스 불순물 영역27: drain impurity region 28: source impurity region

29 : n+ 불순물 영역 30 : 제4감광막29: n + impurity region 30: fourth photosensitive film

31 : 가드링 영역31: Guard ring area

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 구조는 기판; 상기 기판내에 형성되는 제1도전형 웰과 제2도전형 웰; 상기 제1도전형 웰과 제2도전형 웰내에 각각 형성되는 소오스/드레인 불순물 영역; 상기 제1도전형 웰 내에 형성되는 제1도전형 가드링 영역; 상기 제2도전형 웰내에 형성되는 제2도전형 불순물 영역을 포함하여 구성되며, 상기와 같은 구조를 갖는 본 발명의 반도체 소자의 제조방법은 기판을 준비하는 단계; 상기 기판내에 제1도전형 웰과 제2도전형 웰을 각각 형성하는 단계; 상기 제1도전형 웰과 제2도전형 웰내에 각각 소오스 불순물 영역과 드레인 불순물 영역 및 제2도전형 불순물 영역을 형성하는 단계; 상기 제1도전형 웰에 제1도전형 가드링 영역을 형성하는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate; A first conductivity type well and a second conductivity type well formed in the substrate; Source / drain impurity regions formed in the first conductivity type well and the second conductivity type well, respectively; A first conductive guard ring region formed in the first conductive well; And a second conductivity type impurity region formed in the second conductive type well. The method for fabricating a semiconductor device of the present invention having the above structure includes: preparing a substrate; Forming a first conductive well and a second conductive well in the substrate, respectively; Forming a source impurity region, a drain impurity region, and a second conductive impurity region in the first conductive well and the second conductive well, respectively; And forming a first conductive guard ring region in the first conductive type well.

이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 구조 및 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, the structure and manufacturing method of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

제2도는 본 발명의 반도체 소자의 구조를 나타낸 구조단면도이고, 제3a도-제3d도는 본 발명의 반도체 소자의 제조방법을 나타낸 공정단면도이다.FIG. 2 is a structural cross-sectional view showing a structure of a semiconductor device of the present invention, and FIGS. 3a to 3d are process sectional views showing a method of manufacturing a semiconductor device of the present invention.

제2도에 도시된 바와같이 반도체 기판(21)에 서로 접촉되도록 n-웰(23)과 p-웰(25)이 형성되고, 상기 n-웰(23)과 p-웰(25)내에는 각각 드레인 불순물 영역(28)과 소오스 불순물 영역(27)이 형성된다. 또한, 상기 p-웰(25)내에 소오스 불순물 영역(27)과 접촉되어 가드링(Guirding) 영역(31)이 형성되고, 상기 n-웰(23)에 형성된 상기 드레인 불순물 영역(28)과 일정한 간격을 갖고 복수개의 n+ 불순물 영역(29)이 형성된다.Well 23 and p-well 25 are formed in contact with semiconductor substrate 21 as shown in FIG. 2, and n-well 23 and p-well 25 Drain impurity regions 28 and source impurity regions 27 are formed, respectively. In addition, a guarding region 31 is formed in the p-well 25 in contact with the source impurity region 27, and the drain impurity region 28 formed in the n- A plurality of n + impurity regions 29 are formed with an interval.

상기와 같은 구조를 갖는 반도체 소자의 제조방법은 제3a도에 도시된 바와같이 p형 반도체 기판(21)상에 제1감광막(22)을 도포한 후, 노광 및 현상공정으로 패터닝하고, 상기 패터닝된 제1감광막(22)을 마스크로 하여 전면에 n형 불순물 이온을 주입하고, 드라이브 인 공정을 실시하여 n-웰(23)을 형성한다.As shown in FIG. 3 (a), a method of manufacturing a semiconductor device having the above structure includes the steps of applying a first photoresist 22 on a p-type semiconductor substrate 21, patterning the photoresist 22 by an exposure and development process, N-type impurity ions are implanted into the entire surface using the first photoresist film 22 as a mask, and a drive-in process is performed to form an n-well 23.

제3b도에 도시된 바와같이 상기 제1감광막(22)을 제거하고, 전면에 제2감광막(24)을 도포한 후, 노광 및 현상공정으로 패터닝하고 상기 패터닝된 제2감광막(24)을 마스크로 하여 전면에 p형 불순물 이온을 주입하고, 드라이브 인 공정을 실시하여 p-웰(25)을 형성한다.As shown in FIG. 3b, the first photoresist layer 22 is removed, a second photoresist layer 24 is coated on the entire surface, and the patterned photoresist layer 24 is patterned by an exposure and development process. P-type impurity ions are implanted into the entire surface, and a drive-in process is performed to form the p-well 25.

제3c에 도시된 바와같이 상기 제2감광막(24)을 제거하고, 전면에 제3감광막(26)을 도포한 후, 노광 및 현상공정으로 패터닝한다. 이어, 상기 패터닝된 제3감광막(26)을 마스크로 하여 상기 반도체 기판(21)에 고농도 n형 불순물 이온을 주입하여 상기 n-웰(23)과 p-웰(25)내에 각각 소오스 불순물 영역(27)과 드레인 불순물 영역(28)을 형성한다.The second photoresist layer 24 is removed, the third photoresist layer 26 is coated on the entire surface, and then the photoresist layer is patterned by an exposure and development process. Then, high-concentration n-type impurity ions are implanted into the semiconductor substrate 21 using the patterned third photoresist film 26 as a mask to form source impurity regions (not shown) in the n-well 23 and the p- 27 and a drain impurity region 28 are formed.

이때 상기 n-웰(23)내의 드리프트 영역내에도 n+ 불순물 영역(29)이 형성된다. 여기서 상기 드리프트 영역은 채널이 없어도 전자가 스스로 이동하는 영역을 말한다.At this time, the n + impurity region 29 is also formed in the drift region in the n-well 23. Here, the drift region refers to a region in which electrons move by themselves without a channel.

제3d도에 도시된 바와같이 상기 제3감광막(26)을 제거하고, 전면에 제4감광막(30)을 도포한 후, 노광 및 현상공정으로 패터닝하고, 상기 패터닝된 제4감광막(30)을 마스크로 하여 고농도 p형 불순물 이온을 주입하여 상기 소오스 불순물 영역(27)과 접촉되도록 가드링 영역(31)을 형성한다.As shown in FIG. 3D, the third photoresist layer 26 is removed, and the fourth photoresist layer 30 is coated on the entire surface. Then, the third photoresist layer 30 is patterned by an exposure and development process, High-concentration p-type impurity ions are injected as a mask to form a guard ring region 31 so as to be in contact with the source impurity region 27. [

이후 공정은 도시하지 않았지만 상기 제4감광막을 제거하고, 기판상에 게이트 절연막 및 게이트 전극 그리고 소오스 전극과 드레인 전극을 각각 형성한다.Although not shown, the fourth photoresist film is removed, and a gate insulating film, a gate electrode, and a source electrode and a drain electrode are formed on the substrate, respectively.

이상에서 설명한 바와같이 본 발명의 반도체 소자의 구조 및 제조방법에 있어서 다음과 같은 효과가 있다.As described above, the structure and the manufacturing method of the semiconductor device of the present invention have the following effects.

첫째, 드리프트 영역에 도즈량을 증가시키므로 파괴전압(Breakdown Voltage)을 유지할 수 있고, 고유저항값을 낮출 수 있다.First, since the dose amount is increased in the drift region, breakdown voltage can be maintained and the resistivity value can be lowered.

둘째, 고유저항을 낮춤으로써 소비전력을 줄일 수 있고, 프로세스 스피드도 개선할 수 있다.Second, by lowering the resistivity, the power consumption can be reduced and the process speed can be improved.

Claims (4)

기판; 상기 기판내에 형성되는 제1도전형 웰과 제2도전형 웰; 상기 제1도전형 웰과 제2도전형 웰내에 각각 형성되는 소오스/드레인 불순물 영역; 상기 제1도전형 웰 내에 형성되는 제1도전형 가드링 영역; 상기 제2도전형 웰내에 형성되는 제2도전형 불순물 영역을 포함하여 구성됨을 특징으로 하는 반도체 소자의 구조.Board; A first conductivity type well and a second conductivity type well formed in the substrate; Source / drain impurity regions formed in the first conductivity type well and the second conductivity type well, respectively; A first conductive guard ring region formed in the first conductive well; And a second conductivity type impurity region formed in the second conductivity type well. 제1항에 있어서, 상기 제1도전형 웰과 제2도전형 웰은 서로 접촉되게 형성됨을 특징으로 하는 반도체 소자의 구조.The structure of claim 1, wherein the first conductive well and the second conductive well are in contact with each other. 기판을 준비하는 단계; 상기 기판내에 제1도전형 웰과 제2도전형 웰을 각각 형성하는 단계; 상기 제1도전형 웰과 제2도전형 웰내에 각각 소오스 불순물 영역과 드레인 불순물 영역 및 제2도전형 불순물 영역을 형성하는 단계; 상기 제1도전형 웰에 제1도전형 가드링 영역을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 제조방법.Preparing a substrate; Forming a first conductive well and a second conductive well in the substrate, respectively; Forming a source impurity region, a drain impurity region, and a second conductive impurity region in the first conductive well and the second conductive well, respectively; Forming a first conductive guard ring region in the first conductive well; and forming a first conductive guard ring region in the first conductive well. 제3항에 있어서, 상기 제2도전형 불순물 영역은 소오스 불순물 영역과 드레인 불순물 영역의 형성시 동시에 형성함을 특징으로 하는 반도체 소자의 제조방법.4. The method of claim 3, wherein the second conductive impurity region is formed simultaneously with the formation of the source impurity region and the drain impurity region.
KR1019960048262A 1996-10-25 1996-10-25 Semiconductor device structure and method KR100209738B1 (en)

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