KR100332472B1 - Manufacturing method of semiconductor device equipped with static electricity protection circuit - Google Patents
Manufacturing method of semiconductor device equipped with static electricity protection circuit Download PDFInfo
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- KR100332472B1 KR100332472B1 KR1019980045576A KR19980045576A KR100332472B1 KR 100332472 B1 KR100332472 B1 KR 100332472B1 KR 1019980045576 A KR1019980045576 A KR 1019980045576A KR 19980045576 A KR19980045576 A KR 19980045576A KR 100332472 B1 KR100332472 B1 KR 100332472B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000003068 static effect Effects 0.000 title claims description 5
- 230000005611 electricity Effects 0.000 title claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 정전기 보호회로를 구비한 반도체장치의 제조방법에 관한 것으로서, 패드에 연결되는 동작영역 접합영역의 일부에 P-웰 농도를 낮추기 위해서 N-웰 및 P-웰을 같은 영역에 동시에 주입시에 P웰 농도가 상대적으로 높은 것을 이용하여 웰이 카운터 도핑으로 사용하므로써 동작접합의 캐패시턴스를 줄일 수 있게 되어 입력/출력 패드의 속도 지연을 줄일 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an electrostatic protection circuit, wherein an N-well and a P-well are simultaneously injected into the same region in order to reduce the P-well concentration in a part of an operation region junction region connected to a pad. By using a relatively high P well concentration, the wells can be used as counter doping to reduce the capacitance of the operation junction, thereby reducing the speed delay of the input / output pads.
Description
본 발명은 정전기 보호회로를 구비한 반도체장치의 제조방법에 관한 것으로서, 보다 상세하게는 정전기보호회로에서의 입/출력 패드의 캐패시턴스를 줄여 속도를 개선시킬 수 있도록한 기술에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device having an electrostatic protection circuit, and more particularly, to a technology capable of improving speed by reducing capacitance of input / output pads in an electrostatic protection circuit.
종래의 정전기 보호회로(ESD)의 제조방법에서 ESD의 신뢰성 및 데이타 입/출력전류(IOL/IOH)를 만족하기 위해서는 일정한 크기의 바이폴라 및 트랜지스터 크기가 요구되어지므로 패드의 캐패시터의 용량은 계속해서 커지게 된다.In the conventional manufacturing method of the ESD protection circuit, the capacity of the capacitor of the pad is continuously increased because a certain size of bipolar and transistor size is required to satisfy the reliability of the ESD and the data input / output current (IOL / IOH). You lose.
이는 반도체소자의 고집적화로 인해 웰의 도핑농도가 증가하게 되고, 아울러 패드의 접합 캐패시턴스가 커지게 된다. 이러한 캐패시턴스의 증가로 인해 입/출력 패드의 속도지연을 초래하여 최근 제품의 고속도화에 심각한 문제점으로 대두된다.This increases the doping concentration of the well due to the high integration of the semiconductor device, and also increases the junction capacitance of the pad. This increase in capacitance causes a delay in the input / output pads, which is a serious problem in recent high speed products.
이에 본 발명은 상기 종래의 문제점을 해소하기 위하여 안출한 것으로서, 반도체장치의 정전기 보호회로에 있어서, 동작접합의 캐패시턴스를 줄일 수 있게 되어 입/출력패드의 속도지연을 줄일 수 있도록한 정전기보호회로를 구비한 반도체장치의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, and in the electrostatic protection circuit of a semiconductor device, it is possible to reduce the capacitance of the operation junction electrostatic protection circuit to reduce the speed delay of the input / output pads It is an object of the present invention to provide a method of manufacturing a semiconductor device.
도 1 은 본 발명에 따른 반도체장치의 데이타입출력 패드의 정전기보호회로에 사용하는 NPN 바이폴라 트랜지스터의 레이아웃도이다.1 is a layout diagram of an NPN bipolar transistor used in an electrostatic protection circuit of a data input / output pad of a semiconductor device according to the present invention.
도 2 은 본 발명의 다른 실시예로서, 데이타입출력패드의 정전기보호회로에 사용되는 NMOS 트랜지스터의 레이아웃도이다.2 is a layout diagram of an NMOS transistor used in an electrostatic protection circuit of a data input / output pad as another embodiment of the present invention.
도 3 내지 6 는 도 1의 NPN 바이폴라 트랜지스터의 레이아웃에 따른 정전기 보호회로의 제조공정단면도이다.3 to 6 are cross-sectional views illustrating a process of manufacturing an electrostatic protection circuit according to the layout of the NPN bipolar transistor of FIG. 1.
〈 도면의 주요부분에 대한 부호의 설명 〉<Description of the reference numerals for the main parts of the drawings>
1 : 실리콘 기판 2 : 소자분리절연산화막1: silicon substrate 2: device isolation insulating oxide film
3 : 감광막 4 : N-웰영역3: photosensitive film 4: N-well region
5 : P-웰 영역 6 : 웰 카운터 도핑영역(저농도 P웰영역, R-웰)5: P-well region 6: Well counter doping region (low concentration P well region, R-well)
7 : 고농도이온주입확산영역(소오스/드레인영역)7: High concentration ion implantation diffusion region (source / drain region)
8 : 게이트산화막 9 : 게이트전극8 gate oxide film 9 gate electrode
10 : 게이트측벽산화막 100 : 패드에 연결된 동작영역10: gate side wall oxide film 100: operating area connected to pad
200 : 파워선에 연결된 동작영역 A : 동작층200: operating area A connected to the power line A: operating layer
B : N-웰 주입층 C : 게이트전극층B: N-well injection layer C: Gate electrode layer
상기 목적을 달성하기 위한 본 발명은, 제1 도전형 실리콘기판에 소자분리산화막을 형성하는 공정과, 상기 전체 구조의 상부에 패드와 연결될 동작 영역만 노출시키는 감광막패턴을 형성하되, 상기 감광막패턴은 상기 동작 영역의 가장자리로부터 일정거리 만큼은 노출되지 않도록 하는 공정과, 상기 감광막패턴을 마스크로 상기 노출된 실리콘기판에 제2 도전형 이온주입을 실시하여 제2 도전형 웰을 형성하는 공정과, 상기 감광막패턴을 제거하고, 상기 실리콘 기판 전면에 제1 도전형 이온주입을 실시하되, 제2 도전형 이온주입량보다 고농도로 이온주입 공정을 실시함으로써, 상기 제2 도전형 웰의 상부에는 카운터 도핑층을 형성하고, 나머지 영역에는 제1 도전형웰을 형성하는 공정과, 상기 결과물 상에 게이트 전극 및 불순물 확산영역을 형성하는 공정을 포함하여 구성됨을 특징으로한다.In order to achieve the above object, the present invention provides a process for forming a device isolation oxide film on a first conductive silicon substrate, and forming a photoresist pattern that exposes only an operation region to be connected to a pad on the upper portion of the entire structure, wherein the photoresist pattern is Preventing exposure of the substrate by a predetermined distance from an edge of the operation region; forming a second conductivity type well by implanting a second conductivity type ion into the exposed silicon substrate using the photoresist pattern as a mask; By removing the pattern and implanting a first conductivity type ion implantation on the entire surface of the silicon substrate, an ion implantation process is performed at a higher concentration than the second conductivity type ion implantation amount, thereby forming a counter doping layer on the second conductive well. And forming a first conductivity type well in the remaining region, and forming a gate electrode and an impurity diffusion region on the resultant. Including information characterized by configured.
또한, 본 발명은, 제1 도전형 실리콘기판에 소자분리산화막을 형성하는 공정과, 상기 전체 구조의 상부에 패드와 연결될 동작 영역만 노출시키는 감광막패턴을 형성하되, 상기 감광막패턴은 상기 동작 영역의 가장자리로부터 일정거리 만큼은 노출되지 않도록 하는 공정과, 상기 감광막패턴을 마스크로 상기 노출된 실리콘기판에 제2 도전형 이온주입을 실시하여 제2 도전형 웰을 형성하는 공정과, 상기 감광막패턴을 제거하고, 상기 실리콘 기판 전면에 제1 도전형 이온주입을 실시하되, 제2 도전형 이온주입량보다 고농도로 이온주입 공정을 실시함으로써, 상기 제2 도전형 웰의 상부에는 카운터 도핑층을 형성하고, 나머지 영역에는 제1 도전형웰을 형성하는 공정과, 상기 실리콘기판의 상부에 게이트산화막과, 게이트전극 및 게이트측벽산화막을 순차적으로 형성하는 공정과, 상기 전체 구조의 상부에 제2 도전형 고농도 이온주입을 실시하고, 열공정에 의해 고농도 이온주입확산 영역을 형성하는 공정을 포함하여 구성됨을 특징으로한다.The present invention also provides a process for forming a device isolation oxide film on a first conductivity type silicon substrate, and forming a photoresist pattern that exposes only an operation region to be connected to a pad on the upper portion of the entire structure, wherein the photoresist pattern is formed of the operation region. Removing the photosensitive film pattern; forming a second conductive well by performing a second conductivity type ion implantation on the exposed silicon substrate using the photoresist pattern as a mask; and removing the photoresist pattern. The first conductive ion implantation is performed on the entire surface of the silicon substrate, and the ion doping process is performed at a higher concentration than the second conductive ion implantation, thereby forming a counter doping layer on the second conductive well, and remaining regions. In the step of forming a first conductivity type well, a gate oxide film, a gate electrode and a gate side wall oxide film on top of the silicon substrate in order Performing step, the second conductivity type high-concentration ion implantation on top of the entire structure formed by, and is characterized by configured by comprising a step of forming a high-concentration ion implantation diffusion regions by a thermal process.
한편, 본 발명의 목적을 달성하기 위해서는, 반도체장치의 정전기 보호를 위해 패드에 연결되는 동작영역의 가장자리 부분은 정전기 보호 및 데이타입/출력패드(IOH/IOL) 전류를 만족하기 위해 일반적인 P-웰를 일정한 크기로 사용하여 신뢰성을 확보할 수 있도록 되어 있다.On the other hand, in order to achieve the object of the present invention, the edge portion of the operating region connected to the pad for the electrostatic protection of the semiconductor device is a general P-well to satisfy the static protection and data input / output pad (IOH / IOL) current It is used to ensure the reliability by using a certain size.
여기서, 정전기 보호에 사용되는 것은 NPN 바이폴라 및 동작 NMOS 트랜지스터로 N+ -P웰 접합의 P-웰농도 및 영역에 영향을 받으므로 이부분은 최대한 전류가 감소되는 범위에서 일반적인 P웰 및 카운터도핑된 낮은 농도의 P-웰(카운터도핑)면적을 잘 조절하여야 한다.Here, the NPN bipolar and operating NMOS transistors used for electrostatic protection are affected by the P-well concentration and area of the N + -P well junction, so that this part is a typical P well and counter-doped low The P-well (counter doping) area of the concentration should be well controlled.
이하, 본 발명에 따른 정전기 보호회로를 구비한 반도체장치를 첨부된 도면을 참조하여 설명한다.Hereinafter, a semiconductor device having an electrostatic protection circuit according to the present invention will be described with reference to the accompanying drawings.
도 1 은 본 발명에 따른 반도체장치의 데이타입출력 패드의 정전기보호회로에 사용하는 NPN 바이폴라 트랜지스터의 레이아웃도이다.1 is a layout diagram of an NPN bipolar transistor used in an electrostatic protection circuit of a data input / output pad of a semiconductor device according to the present invention.
도 2 은 본 발명의 다른 실시예로서, 데이타입출력패드의 정전기보호회로에 사용되는 NMOS 트랜지스터의 레이아웃도이다.2 is a layout diagram of an NMOS transistor used in an electrostatic protection circuit of a data input / output pad as another embodiment of the present invention.
도 3 내지 5 는 도 1의 NPN 바이폴라 트랜지스터의 레이아웃에 따른 정전기 보호회로의 제조공정단면도이다.3 to 5 are cross-sectional views illustrating a process of manufacturing an electrostatic protection circuit according to the layout of the NPN bipolar transistor of FIG. 1.
도 1 에 도시된 바와같이, 패드에 연결된 동작영역(100)에서 동작층(A)의 가장자리부분에서 안으로 일정한 거리만큼 오버랩되어 N-웰 주입층(B)으로 구성되어 있다.As shown in FIG. 1, the N-well injection layer B is overlapped by a predetermined distance from the edge of the operation layer A in the operation region 100 connected to the pad.
또한, 도 2 에 도시된 바와같이, 패드에 연결된 동작영역(100)에서 동작층 (A)의 가장자리부분 및 게이트전극층(C)에서 안으로 일정한 거리만큼 오버랩되어N-웰 주입층(B)으로 구성되어 있다.In addition, as shown in FIG. 2, in the operation region 100 connected to the pad, the edge portion of the operation layer A and the gate electrode layer C overlap each other by a predetermined distance to constitute the N-well injection layer B. It is.
도 3 내지 6 를 참조하여 도 1의 NPN 바이폴라 트랜지스터의 레이아웃에 따른 정전기 보호회로를 구비한 반도체장치의 제조방법을 설명하면 다음과 같다.A method of manufacturing a semiconductor device having an electrostatic protection circuit according to the layout of the NPN bipolar transistor of FIG. 1 will be described with reference to FIGS. 3 to 6 as follows.
도 3 에 도시된 바와같이, P-타입 실리콘기판(1)에 소자분리산화막(2)을 형성하고, 감광막(3)을 이용하여 패드에 연결된 동작영역에서 동작영역 가장자리부분에서 안으로 일정한 거리만큼 떨어져 N-웰(4)을 형성한다.As shown in FIG. 3, the device isolation oxide film 2 is formed on the P-type silicon substrate 1, and the photosensitive film 3 is used to separate a predetermined distance inward from the edge of the operation region in the operation region connected to the pad. N-wells 4 are formed.
이때, 인(P) 이온주입을 고에너지 이온주입방법으로 다단계 이온주입을 하여 리트로그레이드(retrograde) N-웰(4)을 형성한다.At this time, the phosphorus (P) ion implantation is performed in a multi-step ion implantation method using a high energy ion implantation method to form a retrograde N-well 4.
여기서, 패드에서 연결된 동작영역에서 동작영역 가장자리부분에서 안으로 일정한 거리만큼 떨어져 N-웰(4)을 형성한다.Here, the N-well 4 is formed at a predetermined distance away from the edge of the operating region in the operating region connected to the pad.
그다음, 도 4 에 도시된 바와같이, 전체 구조의 상부에 P-웰 이온주입을 실시하여 P-웰(5)을 형성한다.Then, as shown in Fig. 4, P-well ion implantation is performed on top of the entire structure to form the P-well 5.
여기서 상기 N-웰(4) 및 P-웰(5) 농도는 1E16/cm3∼1E19/cm3이고, P-웰(5) 농도가 N-웰(4)농도보다 더 높다.Wherein the N-well 4 and P-well 5 concentrations are between 1E16 / cm 3 and 1E19 / cm 3 and the P-well 5 concentration is higher than the N-well 4 concentration.
이어서, 도 5 에 도시된 바와같이, 후속 열공정에 의해 웰이 형성되고, 그 상부에 N+ 고농도 이온주입을 실시하고, 이후 열공정에 의해 N+ 고농도이온주입확산영역(7)을 형성한다.Subsequently, as shown in FIG. 5, a well is formed by a subsequent thermal process, and an N + high concentration ion implantation diffusion region is formed thereon, and the N + high concentration ion implantation diffusion region 7 is then formed by a thermal process.
이때, 동작영역의 중앙부위가 N-웰 및 P-웰을 같은 영역에 동시에 주입하면, P-웰 농도가 상대적으로 높으므로 이것은 이 부분의 웰이 카운터도핑이 되고, 저농도의 P-타입 웰(6)이 형성된다.At this time, if the center portion of the operating region simultaneously injects the N-well and the P-well into the same region, since the P-well concentration is relatively high, this means that the well of this portion is counter-doped, and the low concentration of the P-type well ( 6) is formed.
또한, N+ 접합과 접촉부위의 P-웰의 농도를 낮게 조절하므로써 접합 디플리션(junction depletion) 폭이 크게 되고, 접합 캐패시턴스를 줄일 수 있다.In addition, by controlling the concentration of the P + well at the N + junction and the contact region low, the junction depletion width is increased, and the junction capacitance can be reduced.
그리고, 패드에 연결되는 N+ 고농도이온주입확산영역(7)의 중앙부위의 N+ 접합깊이가 가장자리보다 더 깊다.Then, the N + junction depth of the central portion of the N + high concentration ion implantation diffusion region 7 connected to the pad is deeper than the edge.
한편, 도 6 는 도 2의 동작 NMOS 트랜지스터의 레이아웃에 따른 정전기 보호회로의 제조공정단면도이다.6 is a cross-sectional view illustrating a process of manufacturing an electrostatic protection circuit according to the layout of the operating NMOS transistor of FIG. 2.
도 6 에 도시된 바와같이, P-타입 실리콘기판(1)에 소자분리산화막(2)을 형성하고, 감광막(3)을 이용하여 패드에 연결된 동작영역에서 동작영역의 가장자리부분에서 안으로 일정한 거리만큼 떨어져 N-웰(4)을 형성한다.As shown in FIG. 6, the device isolation oxide film 2 is formed on the P-type silicon substrate 1, and the photosensitive film 3 is used to form a predetermined distance inward from the edge of the operation area in the operation area connected to the pad. To form an N-well 4.
이때, 인(P) 이온주입을 고에너지 이온주입방법으로 다단계 이온주입을 하여 리트로그레이드(retrograde) N-웰(4)을 형성한 후, 그 상부에 P-웰이온을 주입하여 P-웰(5)을 형성하고, 후속 열공정을 받아 웰이 형성된다.At this time, the phosphorus (P) ion implantation is performed by a multi-step ion implantation method to form a retrograde N-well (4), and then P-well ions are injected into the upper portion of the P-well ( 5) is formed and the well is formed by a subsequent thermal process.
여기서, 상기 N-웰(4) 및 P-웰(5) 농도는 1E16/cm3∼1E19/cm3이고, P-웰(5) 농도가 N-웰(4)농도보다 더 높다.Here, the N-well 4 and P-well 5 concentrations are 1E16 / cm 3 to 1E19 / cm 3, and the P-well 5 concentration is higher than the N-well 4 concentration.
이어서, 전체 구조의 상부에 게이트산화막(8)과, 게이트전극(9) 및 게이트측벽산화막(10)을 형성한 후 N+ 고농도이온주입을 실시한 다음 후속 열공정에 의해 고농도이온주입확산영역(7)을 형성한다.Subsequently, the gate oxide film 8, the gate electrode 9, and the gate side wall oxide film 10 are formed on the entire structure, followed by N + high concentration ion implantation, followed by a high concentration ion implantation diffusion region 7 by a subsequent thermal process. To form.
이때, 패드에서 연결된 고농도 이온주입확산영역에서 동작영역 가장자리부분 및 게이트전극에서 안으로 일정한 거리만큼 떨어져 중앙부위의 N+ 접합과 접촉하고 있는 일정한 위치에서 N-웰 및 P-웰을 같은 영역에 동시에 주입하면 P-웰농도가 상대적으로 높아지게 된다. 따라서, 이 부분의 웰이 카운터 도핑이 되고 저농도의 P타입웰 (6)이 형성된다.In this case, when the N-well and P-well are simultaneously injected into the same region at a constant position in contact with the N + junction at the center of the high concentration ion implantation diffusion region connected from the pad by a predetermined distance from the edge of the operating region and the gate electrode. P-well concentration is relatively high. Thus, the wells of this portion are counter-doped and low concentration P-type wells 6 are formed.
그리고, 패드에 연결되는 N+ 고농도이온주입확산영역(7)의 중앙부위의 N+ 접합깊이가 가장자리보다 더 깊다.Then, the N + junction depth of the central portion of the N + high concentration ion implantation diffusion region 7 connected to the pad is deeper than the edge.
상기에서 설명한 바와같이, 본 발명에 따른 정전기 보호회로를 구비한 반도체장치의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the manufacturing method of the semiconductor device having the static electricity protection circuit according to the present invention has the following effects.
패드에서 연결된 고농도 이온주입확산영역에서 동작영역 가장자리부분 및 게이트전극에서 안으로 일정한 거리만큼 떨어져 중앙부위의 N+ 접합과 접촉하고 있는 일정한 위치에서 N-웰 및 P-웰을 같은 영역에 동시에 주입하면 P-웰농도가 상대적으로 높아지게 된다. 따라서, 이 부분의 웰이 카운터 도핑이 되고 저농도의 P타입웰이 형성된다.In the high concentration ion implantation diffusion region connected from the pad, if N-well and P-well are injected into the same region at the same position at a constant position away from the edge of the operating region and the gate electrode in contact with the N + junction at the center, P- Well concentrations are relatively high. Thus, the wells of this portion are counter-doped and low concentration P-type wells are formed.
그로므로, N+ 접합과 접촉부위의 P-웰의 농도를 낮게 조절하므로써 접합 디플리션 (depletion)폭을 크게 할 수 있고, 접합 캐패시턴스도 줄일 수 있다.Therefore, the depth of junction depletion can be increased and the junction capacitance can be reduced by controlling the concentration of the P + well at the N + junction and the contact region low.
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| KR950007092A (en) * | 1993-08-24 | 1995-03-21 | 김광호 | Electrostatic protection element of semiconductor device and formation method thereof |
| KR950012705A (en) * | 1993-10-21 | 1995-05-16 | 김주용 | Transistor of electrostatic discharge protection circuit and its manufacturing method |
| KR19980065222A (en) * | 1997-01-06 | 1998-10-15 | 김광호 | Electrostatic protection device |
| KR19980067430A (en) * | 1997-02-05 | 1998-10-15 | 김광호 | Static electricity protection device of semiconductor device |
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| KR950007092A (en) * | 1993-08-24 | 1995-03-21 | 김광호 | Electrostatic protection element of semiconductor device and formation method thereof |
| KR950012705A (en) * | 1993-10-21 | 1995-05-16 | 김주용 | Transistor of electrostatic discharge protection circuit and its manufacturing method |
| KR19980065222A (en) * | 1997-01-06 | 1998-10-15 | 김광호 | Electrostatic protection device |
| KR19980067430A (en) * | 1997-02-05 | 1998-10-15 | 김광호 | Static electricity protection device of semiconductor device |
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