CN100428443C - Method for reducing wafer charge damage - Google Patents

Abstract

The invention discloses a method for reducing wafer charge damage. The integrated circuit die comprises a first element area, a second element area and a shallow trench insulation dummy area, wherein the first element area occupies a larger area proportion in the integrated circuit die, and the second element area occupies a smaller area proportion; forming a first ion implantation mask on the semiconductor substrate to cover the second element region and the shallow trench insulation dummy region, but expose the surface of the semiconductor substrate in the first element region; implanting a dopant into the exposed surface of the semiconductor substrate in the first element region to form a first doped region; removing the first ion implantation mask; forming a second ion implantation mask on the semiconductor substrate, wherein the second ion implantation mask covers the first element region but exposes the surface of the semiconductor substrate in the second element region and the shallow trench insulation dummy structure in the shallow trench insulation dummy region; and implanting a dopant into the exposed surface of the semiconductor substrate in the second element region to form a second doped region.

Description

A Method for Reducing Chip Charge Damage

technical field

The invention relates to a semiconductor process, in particular to a method capable of reducing chip charge damage generated in the integrated circuit process.

Background technique

In the semiconductor device industry, it is often necessary to add dopant to the semiconductor substrate to control the number of charged carriers. This method of adding dopant is called implanting dopant or ion implantation process. Basically, an ion implanter can be broken down into several sub-systems: ion source, ion beam delivery subsystem, end station system, gas or vapor supply system, vacuum system, and power supply system. According to the size and energy of the ion beam provided, ion implantation equipment can be classified into high-current and medium-current ion implanters, and high (million electron volts), medium ( Between 5,000 and 250,000 electron volts), low (less than 5,000 electron volts) energy ion implanters. Usually, the high-current ion implanter is equipped with a plasma flood system or an electron shower to neutralize the charged dopant.

The main disadvantage of ion implantation is that it causes some degree of structural damage within the silicon chip. This damage may be caused by a large amount of charge accumulated on the surface of the wafer when the wafer is in the plasma environment or during the ion implantation process.

In the above-mentioned plasma environment or during the ion implantation process, a large amount of accumulated charges on the wafer surface may pass through the capacitive structures that have been fabricated on the wafer surface, such as the gate of the metal oxide semiconductor transistor and the underlying semiconductor substrate, in the form of current. , and cause damage to the gate oxide layer between the gate and the semiconductor substrate, and more seriously, the gate structure may burst and be permanently damaged due to the passage of instantaneous high current. In the aforementioned plasma environment, the reason for a large amount of charge accumulation on the wafer surface may be due to the uneven distribution of plasma density or electron temperature; be completely neutralized.

In the related prior art, U.S. Patent No. 5,998,282 discloses a method that can reduce the charge damage to the wafer caused in the plasma environment or during the ion implantation process, which is mainly used in the manufacturing process of integrated circuits , on the dicing lines around each integrated circuit die, a path that can drain current is formed, so that the possibility of current passing through the internal components of the integrated circuit die is reduced, thereby reducing damage. However, it is also pointed out in the US patent that it is very difficult to form another path similar to the leakage current in the integrated circuit die due to the limitation of the configuration of the circuit elements.

Contents of the invention

The main purpose of the present invention is to provide a method capable of reducing the chip charge damage generated in the integrated circuit process.

According to a preferred embodiment of the present invention, the present invention discloses a method for reducing wafer charge damage in a semiconductor process, including providing a semiconductor substrate with a plurality of integrated circuit dies, each of which is composed of The cutting lines are separated from each other, wherein each of the integrated circuit dies includes at least a first element region, a second element region and a shallow trench isolation dummy region, and wherein the area occupied by the first element region in the integrated circuit die The proportion of the area occupied by the second element region in the integrated circuit die is relatively small; a first ion implantation mask is formed on the semiconductor substrate, and the first ion implantation mask covers the second element region and the shallow trench insulation dummy region, but exposing the surface of the semiconductor substrate of the first element region; injecting dopant into the surface of the semiconductor substrate exposed by the first element region to form a first doping region; remove the first ion implantation mask; form a second ion implantation mask on the semiconductor substrate, the second ion implantation mask covers the first element region, but exposes the second element region The surface of the semiconductor substrate and the plurality of shallow trench isolation dummy structures in the shallow trench isolation dummy region; and injecting dopant into the surface of the semiconductor substrate exposed by the second element region to form a second doped area.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings related to the present invention. However, the drawings are only for reference and auxiliary description, and are not intended to limit the present invention.

Description of drawings

FIG. 1 is a schematic diagram of the layout of an ion-implanted photoresist mask for forming a lightly doped drain or source of a high-voltage device in a semiconductor substrate.

FIG. 2 is a schematic layout diagram of an ion-implanted photoresist mask for forming a lightly doped drain or source of a high-voltage device in a semiconductor substrate according to a preferred embodiment of the present invention.

FIG. 3 to FIG. 6 are cross-sectional schematic diagrams of a method for reducing charge damage to a wafer during the fabrication of integrated circuits according to a preferred embodiment of the present invention.

FIG. 7 to FIG. 10 are schematic cross-sectional views of another preferred embodiment of the present invention for reducing the charge damage of the wafer during the integrated circuit manufacturing process.

Explanation of reference signs

1 chip 10 integrated circuit dies

12 scribes 20 ion implantation photoresist mask

20a ion implantation photoresist mask 22 openings

24 dummy openings 100 semiconductor substrates

101 High voltage component area 102 Low voltage component area

103 Medium voltage component area 104 Trench insulation dummy area

110 shallow trench insulation structure 1 21 grid

122 Grid 123 Grid

124 shallow trench insulation dummy structure 131 gate oxide layer

132 Gate Oxide 133 Gate Oxide

141 Lightly doped drain/source region 142 Lightly doped drain/source region

143 Lightly doped drain/source regions 210 Ion implantation photoresist mask

220 Ion Implantation Photoresist Mask 230 Ion Implantation Photoresist Mask

304 passive area

310 Ion Implantation Photoresist Mask 320 Ion Implantation Photoresist Mask

320a opening 324 substrate

330 ion implantation photoresist mask 330a opening

Detailed ways

As mentioned earlier, the high current ion implanter used in the ion implantation process is usually equipped with a plasma flood system (plasma flood system) or electron shower equipment (electron shower) to neutralize the charged dopant to suppress the amount of positive charges on the wafer surface. However, in some cases, the ion implanter used in the ion implantation process is not equipped with or does not use such plasma flooding system or electron rinse equipment. For example, a medium current ion implanter is not equipped with such a plasma flooding system or an electronic shower device for ion implantation dose considerations. The ion implantation dose provided by this medium-current ion implanter is usually between 1E11~1E14 atoms/cm ² , and the ion implantation energy is usually between 10KeV~500KeV, and is often used to form lightly doped drains or sources in semiconductor substrates ( lightly doped drain/source) area.

Please refer to FIG. 1 , which is a schematic layout diagram of an ion-implanted photoresist mask 20 for forming a lightly doped drain or source of a high voltage device in a semiconductor substrate. As shown in FIG. 1 , an integrated circuit die 10 is separated from other adjacent integrated circuit dies on a wafer by surrounding scribe lines 12 . A number of test keys are typically formed on the scribe line 12 to monitor the integrity of the integrated circuit die 10 . Within the integrated circuit die 10, ion traps, gate oxide layers, polysilicon gates, and shallow trench isolation regions for components have been fabricated on a semiconductor substrate, such as a silicon substrate.

In the process of forming the lightly doped drain or source of the high voltage element in the semiconductor substrate, the ion-implanted photoresist mask 20 covers most of the area of the integrated circuit die 10, only shown in the figure There is a small opening 22 near the lower left corner, which exposes the position of the high-voltage metal-oxygen-semiconductor transistor in the semiconductor substrate. It is ready to use the aforementioned medium-current ion implanter to form the lightly doped drain or the high-voltage metal-oxygen-semiconductor transistor in the semiconductor substrate. source.

Since the aforementioned high-voltage metal-oxygen-semiconductor transistors only account for a small portion of the integrated circuit die 10, the opening 22 of the ion-implanted photoresist mask 20 is usually very small, often accounting for only 0.2 of the area of a single integrated circuit die 10. %~2%. In the process of forming the lightly doped drain or source of the high-voltage metal-oxygen-semiconductor transistor, due to the use of a medium-current ion implanter that is not equipped with a plasma flooding system or an electron rinsing device, there will be damage to the internal components of the integrated circuit die 10. Destruction, such as bursting of the gate structure.

It can be seen from this how to reduce the above-mentioned process of forming the lightly doped drain or source of the high-voltage metal-oxygen-semiconductor transistor by using a medium-current ion implanter that is not equipped with a plasma flooding system or electronic rinsing equipment to produce an integrated circuit die. 10 The destruction of internal components has become a priority.

Please refer to FIG. 2 , which is a schematic layout diagram of an ion-implanted photoresist mask 20 a for forming a lightly doped drain or source of a high voltage device in a semiconductor substrate according to a preferred embodiment of the present invention. As shown in FIG. 2 , a wafer 1 has a plurality of integrated circuit dies 10 separated from other adjacent integrated circuit dies by scribe lines 12 around them. A number of test keys are typically formed on the scribe line 12 to monitor the integrity of the integrated circuit die 10 . Within the integrated circuit die 10, ion traps, gate oxide layers, polysilicon gates, and shallow trench isolation regions for components have been fabricated on a semiconductor substrate, such as a silicon substrate.

The ion-implantation photoresist mask 20a includes a small-area opening 22 that exposes the underlying substrate surface to be formed with a lightly doped drain or source of a high-voltage MOS device by a medium-current ion implanter. The substrate surface of these high-voltage MOS elements exposed through the small-area opening 22 (hereinafter referred to as "element exposed area") is usually the drain-source region of the high-voltage MOS element isolated by the shallow trench isolation region. In addition, the ion-implanted photoresist mask 20 a further includes a plurality of dummy openings 24 distributed in other positions within the integrated circuit die 10 . At this point, the dicing streets 12 around the integrated circuit die 10 may be partially masked, or the dicing streets 12 may be completely unmasked.

According to a preferred embodiment of the present invention, the dummy opening 24 of the ion-implanted photoresist mask 20a is used to deliberately form the lightly doped drain or source of the high-voltage MOS device in the aforementioned medium-current ion implanter. increase the exposed substrate surface. The dummy opening 24 needs to expose a non-component area (hereinafter referred to as "non-component exposed area"). In other words, no active circuit components will be formed on the surface of the substrate exposed by the dummy opening 24 . According to a preferred embodiment of the present invention, the dummy opening 24 may be a dummy pattern used to reduce the loading effect when forming the STI region. According to a preferred embodiment of the present invention, the area of the element exposed area of the aforementioned opening 22 and the area of the non-element exposed area of the dummy opening 24 are added, and the area ratio thereof can preferably exceed 5% of the area of each integrated circuit die 10 above.

The main advantage of the present invention is that the exposed substrate surface is deliberately increased by using the dummy opening 24, and the elements (non-element exposed regions) of the active circuit will not be formed on the substrate surface exposed by the dummy opening 24, so that Effectively increase the current leakage path inside the integrated circuit die 10, and greatly reduce the chip charge damage that may be generated during the ion implantation process of the lightly doped drain or source of the high-voltage element.

To illustrate the present invention more clearly, please refer to FIG. 3 to FIG. 6 , which are schematic cross-sectional views of a method for reducing charge damage to a wafer during the fabrication of integrated circuits according to a preferred embodiment of the present invention. First, as shown in FIG. 3 , the semiconductor substrate 100 includes a high-voltage element region 101, a low-voltage element region 102, a medium-voltage element region 103, and a shallow trench isolation dummy region 104. The shallow trench isolation structure 110 has been formed on the surface of the semiconductor substrate 100. To electrically isolate components in different areas. For simplicity of illustration, the ion traps formed in the semiconductor substrate 100 are not shown.

In the high voltage device region 101 , a high voltage metal oxide semiconductor transistor device, for example, a 5 volt metal oxide semiconductor transistor device is formed. For example, the gate 121 of the high voltage NMOS transistor device in the high voltage device region 101 is used for illustration. The gate 121 is formed on the thick gate oxide layer 131 and is electrically isolated from the underlying semiconductor substrate 100 . In the low voltage device region 102 , a low voltage MOS transistor device, for example, a 1.8 volt MOS transistor device is formed. For example, the gate 122 of the low voltage NMOS transistor device in the low voltage device region 102 is used for illustration. The gate 122 is formed on the gate oxide layer 132 and is electrically isolated from the underlying semiconductor substrate 100 , wherein the thickness of the gate oxide layer 132 is smaller than that of the gate oxide layer 131 . In the medium voltage device region 103, medium voltage MOS transistor devices, for example, 3.3 volt MOS transistor devices are formed. For example, the gate 123 of the medium-voltage N-type MOS transistor device in the medium-voltage device region 103 is used for illustration. The gate 123 is formed on the gate oxide layer 133 and is electrically isolated from the underlying semiconductor substrate 100 , wherein the thickness of the gate oxide layer 133 is smaller than that of the gate oxide layer 131 . In the STI dummy region 104 , a plurality of STI dummy structures 124 have been formed. The plurality of STI structures 124 have exposed surfaces of the semiconductor substrate 100 on which no active circuit components are formed.

As shown in FIG. 4 , a lightly doped drain (LDD) ion-implanted photoresist mask 210 is then formed on the surface of the semiconductor substrate 100, covering the high-voltage device region 101, the low-voltage device region 102 and the shallow trench isolation. The dummy area 104, but exposes the medium voltage component area 103. Since the area occupied by the medium-voltage device region 103 is larger in the integrated circuit die 10 , the exposed surface area of the semiconductor substrate 100 is also relatively larger.

Next, the semiconductor substrate 100 covered with the photoresist mask 210 for LDD ion implantation is placed in an ion implantation machine, such as a medium-current ion implantation machine, and the LDD ion implantation process is performed to expose arsenic and other dopants. In this way, a lightly doped drain/source region 143 is formed in the medium voltage device region 103 on the surface of the semiconductor substrate 100 . According to a preferred embodiment of the present invention, the ion implanter performing the LDD ion implantation process is a medium-current ion implanter, and the plasma flooding system or electronic shower equipment is not used in consideration of the dose issue. Next, the LDD ions are implanted into the photoresist mask 210 and removed.

As shown in FIG. 5 , another LDD ion implantation photoresist mask 220 is then formed on the surface of the semiconductor substrate 100, which covers the medium voltage component region 103 and the low voltage component region 102, but exposes the high voltage component region 101 and the low voltage component region 102. The shallow trench isolation dummy region 104 . Because in the integrated circuit die 10, the proportion of the area occupied by the high-voltage element region 101 is relatively small, at this time, the exposed surface area of the semiconductor substrate 100 is also relatively small. About 0.2% to 2% of the area of the die 10 . Therefore, in order to increase the surface area of the semiconductor substrate 100 exposed inside the integrated circuit die 10 during the LDD ion implantation process, the present invention deliberately implants the shallow trench isolation dummy region 104 and A plurality of SDI structures 124 in the SDI region 104 are exposed.

By exposing the shallow trench isolation dummy region 104 and a plurality of shallow trench isolation dummy structures 124 in the shallow trench isolation dummy region 104 in the LDD ion implantation photoresist mask 220, the LDD ion implantation process of the high voltage element can be made The semiconductor substrate surface area exposed in the process increases to more than 5% of the area of a single integrated circuit die 10 . Next, the semiconductor substrate 100 covered with the photoresist mask 220 for LDD ion implantation is placed in an ion implantation machine, such as a medium-current ion implanter, to perform the LDD ion implantation process to expose arsenic and other dopants. In the surface of the semiconductor substrate 100 , a lightly doped drain/source region 141 is formed in the high voltage device region 101 in this way. Similarly, the ion implanter performing the LDD ion implantation process is a medium-current ion implanter, and the plasma flooding system or electronic shower equipment is not used in consideration of the dose. Next, the LDD ions are implanted into the photoresist mask 220 and removed.

As shown in Figure 6, another LDD ion implantation photoresist mask 230 is then formed on the surface of the semiconductor substrate 100, which covers the medium voltage element region 103 and the high voltage element region 101, but exposes the low voltage element region 102 and The shallow trench isolation dummy region 104 . Because in the integrated circuit die 10, if the proportion of the area occupied by the low-voltage element region 102 is also small, the exposed surface area of the semiconductor substrate 100 is also relatively small, for example, less than 5% of the area of a single integrated circuit die 10 . Therefore, in order to increase the surface area of the semiconductor substrate 100 exposed inside the integrated circuit die 10 during the LDD ion implantation process, the present invention uses the shallow trench isolation dummy region 104 and the shallow trench isolation dummy region 104 in the photoresist mask 230 for LDD ion implantation. A plurality of shallow trench isolation dummy structures 124 in the trench isolation dummy region 104 are exposed.

Next, the semiconductor substrate 100 covered with the photoresist mask 230 for LDD ion implantation is placed in an ion implantation machine, such as a medium-current ion implanter, to perform an LDD ion implantation process to expose arsenic and other dopants. In the surface of the semiconductor substrate 100 , a lightly doped drain/source region 142 is formed in the low voltage device region 102 . Similarly, the ion implanter performing the LDD ion implantation process is a medium-current ion implanter, and the plasma flooding system or electronic shower equipment is not used in consideration of the dose. Next, the LDD ion-implanted photoresist mask 230 is removed. Subsequent semiconductor process steps include formation of sidewalls of the gate, heavy doping of the drain/source, metal silicide process, etc., which are well known to those skilled in the art, and thus will not be repeated here. It is worth mentioning that the subsequent heavy doping process of the drain/source is usually performed in a high-current ion implanter.

Please refer to FIG. 7 to FIG. 10 , which are schematic cross-sectional views of another preferred embodiment of the present invention for reducing the charge damage of the wafer during the fabrication of integrated circuits. First, as shown in FIG. 7, the semiconductor substrate 100 includes a high-voltage element region 101, a low-voltage element region 102, a medium-voltage element region 103, and an inactive region 304. A shallow trench isolation structure 110 has been formed on the surface of the semiconductor substrate 100 to electrically Sexually isolate components in different regions. For simplicity of illustration, the ion traps formed in the semiconductor substrate 100 are not shown.

In the high voltage device region 101 , a high voltage metal oxide semiconductor transistor device, for example, a 5 volt metal oxide semiconductor transistor device is formed. For example, the gate 121 of the high voltage NMOS transistor device in the high voltage device region 101 is used for illustration. The gate 121 is formed on the thick gate oxide layer 131 and is electrically isolated from the underlying semiconductor substrate 100 . In the low voltage device region 102 , a low voltage MOS transistor device, for example, a 1.8 volt MOS transistor device is formed. For example, the gate 122 of the low voltage NMOS transistor device in the low voltage device region 102 is used for illustration. The gate 122 is formed on the gate oxide layer 132 and is electrically isolated from the underlying semiconductor substrate 100 , wherein the thickness of the gate oxide layer 132 is smaller than that of the gate oxide layer 131 . In the medium voltage device region 103, medium voltage MOS transistor devices, for example, 3.3 volt MOS transistor devices are formed. For example, the gate 123 of the medium-voltage N-type MOS transistor device in the medium-voltage device region 103 is used for illustration. The gate 123 is formed on the gate oxide layer 133 and is electrically isolated from the underlying semiconductor substrate 100 , wherein the thickness of the gate oxide layer 133 is smaller than that of the gate oxide layer 131 . The so-called passive area 304 refers to the exposed substrate surface 324, but no active circuit elements are formed thereon.

As shown in FIG. 8 , a lightly doped drain (LDD) ion-implanted photoresist mask 310 is then formed on the surface of the semiconductor substrate 100, covering the high-voltage element region 101, the low-voltage element region 102 and the passive region. 304, but the medium voltage component area 103 is exposed. Since the area occupied by the medium-voltage device region 103 is larger in the integrated circuit die 10 , the exposed surface area of the semiconductor substrate 100 is also relatively larger.

Next, the semiconductor substrate 100 covered with the photoresist mask 310 for LDD ion implantation is placed in an ion implantation machine, such as a medium-current ion implantation machine, and the LDD ion implantation process is performed to expose arsenic and other dopants. In this way, a lightly doped drain/source region 143 is formed in the medium voltage device region 103 on the surface of the semiconductor substrate 100 . The ion implanter performing the LDD ion implantation process is a medium-current ion implanter, and considering the dose issue, no plasma flooding system or electronic shower equipment is used. Next, the LDD ions are implanted into the photoresist mask 310 and removed.

As shown in FIG. 9 , another LDD ion-implanted photoresist mask 320 is then formed on the surface of the semiconductor substrate 100 , covering the medium voltage device region 103 and the low voltage device region 102 . The LDD ion implantation photoresist mask 320 exposes the high voltage device region 101, and the LDD ion implantation photoresist mask 320 has an opening 320a, so as to expose a part of the substrate surface 324 in the passive area 304 . According to the present invention, the opening 320a of the LDD ion-implanted photoresist mask 320 may be the same as the STI dummy pattern for etching back the trench-fill insulating layer.

The aforementioned STI dummy pattern is used to avoid the loading effect or residual problem that may be generated above the large passive area when polishing the STI trench filling insulating layer. Therefore, before polishing, use The STI dummy pattern etches back the STI trench-fill insulating layer above the passive area to a predetermined thickness.

Next, the semiconductor substrate 100 covered with the photoresist mask 320 for LDD ion implantation is placed in an ion implantation machine, such as a medium-current ion implanter, to perform an LDD ion implantation process to expose arsenic and other dopants. In the surface of the semiconductor substrate 100 , a lightly doped drain/source region 141 is formed in the high voltage device region 101 in this way. Similarly, the ion implanter performing the LDD ion implantation process is a medium-current ion implanter, and the plasma flooding system or electronic shower equipment is not used in consideration of the dose. Next, the LDD ion-implanted photoresist mask 320 is removed.

As shown in FIG. 10 , another LDD ion implantation photoresist mask 330 is then formed on the surface of the semiconductor substrate 100, which covers the medium voltage element region 103 and the high voltage element region 101, but exposes the low voltage element region 102, And the LDD ion implantation photoresist mask 330 has an opening 330a exposing a portion of the substrate surface 324 in the passive region 304 .

Next, the semiconductor substrate 100 covered with the LDD ion implantation photoresist mask 330 is placed in an ion implantation machine, such as a medium-current ion implanter, to perform an LDD ion implantation process to expose arsenic and other dopant implants. In the surface of the semiconductor substrate 100 , a lightly doped drain/source region 142 is formed in the low voltage device region 102 . Similarly, the ion implanter performing the LDD ion implantation process is a medium-current ion implanter, and the plasma flooding system or electronic shower equipment is not used in consideration of the dose. Next, the LDD ion-implanted photoresist mask 330 is removed.

Although the preferred embodiment of the present invention is described by taking the formation of the lightly doped drain source region in the high voltage element region in the semiconductor substrate as an example, the present invention should not be limited only to the ion implantation process, and those skilled in the art Those skilled in the art should be able to understand the spirit of the present invention and apply it to other similar applications, such as plasma etching machines or plasma processes that also cause wafer charge damage. In addition, in the above-mentioned preferred embodiments of the present invention, the order of ion implantation in the high-voltage element area, low-voltage element area, and medium-voltage element area can be adjusted and interchanged, for example, the LDD implantation of the low-voltage element is performed first or the LDD implantation of the high-voltage element is performed first can be.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

1, a kind of method that reduces wafer charge injury in semiconductor technology includes:

Semi-conductive substrate is provided, have a plurality of integrated circuit leads on it, each described integrated circuit lead is separated from each other by Cutting Road, wherein each described integrated circuit lead includes at least one first element area, second element area and shallow-channel insulation nominal region, and wherein said first element area shared area ratio in described integrated circuit lead is bigger, and described second element area shared area ratio in described integrated circuit lead is less;

Form the first ion injecting mask on described Semiconductor substrate, the described first ion injecting mask covers described second element area and described shallow-channel insulation nominal region, but exposes the surface of the described Semiconductor substrate of described first element area;

Dopant is injected the surface of the described Semiconductor substrate that described first element area comes out, to form first doped region;

Remove the described first ion injecting mask;

On described Semiconductor substrate, form the second ion injecting mask, the described second ion injecting mask covers described first element area, but exposes the surface and the interior a plurality of shallow-channel insulation dummy structures of described shallow-channel insulation nominal region of the described Semiconductor substrate of described second element area; And

Dopant is injected the surface of the described Semiconductor substrate that described second element area comes out, to form second doped region.

2, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 1 wherein is formed with first grid in described first element area and the first grid oxide layer is formed between described first grid and the described Semiconductor substrate.

3, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 1 wherein is formed with second grid in described second element area and the second grid oxide layer is formed between described second grid and the described Semiconductor substrate.

4, the method that in semiconductor technology, reduces wafer charge injury as claimed in claim 1, wherein said second element area is the high voltage device zone, and described second doped region is the lightly doped drain zone that is about to be formed on the metal-oxide-semiconductor transistor element in the described high voltage device zone.

5, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 4, wherein said metal-oxide-semiconductor transistor element is the nmos pass transistor element.

6, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 1, wherein said a plurality of shallow-channel insulation dummy structures expose the surface of the described Semiconductor substrate of part in each described integrated circuit lead.

7, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 1, the step of wherein dopant being injected the surface of the described Semiconductor substrate that described second element area comes out is to carry out at a medium current ion implanter.

8, a kind of method of making integrated circuit includes:

Provide semi-conductive substrate, the Cutting Road that has at least one integrated circuit lead zone on it and center on described integrated circuit lead zone;

In described integrated circuit lead zone, form first shallow-channel insulation zone and the second shallow-channel insulation zone simultaneously, the wherein said first shallow-channel insulation zone is formed between first element area and second element area to produce electrical isolation, and have a plurality of shallow-channel insulation dummy structures in the described second shallow-channel insulation zone, and wherein said first element area shared area ratio in described integrated circuit lead is bigger, and described second element area shared area ratio in described integrated circuit lead is less;

In described first element area and in described second element area, form first grid and second grid respectively;

Cover described first element area, but expose the described a plurality of shallow-channel insulation dummy structures in described second element area and the described second shallow-channel insulation zone; And

Carry out an ion implantation technology, dopant is injected the surface of the described Semiconductor substrate of described second element area that exposes.

9, the method for making integrated circuit as claimed in claim 8, wherein said ion implantation technology are to carry out in a medium current ion implanter.

10, a kind of method that reduces wafer charge injury in semiconductor technology includes:

Semi-conductive substrate is provided, have a plurality of integrated circuit leads on it, each described integrated circuit lead is separated from each other by Cutting Road, wherein each described integrated circuit lead includes at least one first element area, second element area and inactive regions, and wherein said first element area shared area ratio in described integrated circuit lead is bigger, and described second element area shared area ratio in described integrated circuit lead is less;

Form the first ion injecting mask on described Semiconductor substrate, the described first ion injecting mask covers described second element area and described inactive regions, but exposes the surface of the described Semiconductor substrate of described first element area;

Dopant is injected the surface of the described Semiconductor substrate that described first element area comes out, to form first doped region;

Remove the described first ion injecting mask;

On described Semiconductor substrate, form the second ion injecting mask, the described second ion injecting mask covers described first element area, but exposes the surface and the interior described Semiconductor substrate of described inactive regions of the described Semiconductor substrate of described second element area; And

Dopant is injected the surface of the described Semiconductor substrate that described second element area comes out, to form second doped region.

Images