CN100428443C - Method for reducing wafer charge injury - Google Patents
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- CN100428443C CN100428443C CNB2005100897361A CN200510089736A CN100428443C CN 100428443 C CN100428443 C CN 100428443C CN B2005100897361 A CNB2005100897361 A CN B2005100897361A CN 200510089736 A CN200510089736 A CN 200510089736A CN 100428443 C CN100428443 C CN 100428443C
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Abstract
The invention relates to a method for reducing crystal chip charge damage, wherein the integrated circuit tube corn comprises the first element region, the second element region and a shallow groove insulated virtual region; the first ion pour mask is formed on the semi-conductor substrate, to cover the second element region and the shallow groove insulated virtual region, but expose the semi-conductor substrate surface of first element region; pouring the doping agent into the exposed semi-conductor substrate of first element region, to form the first doping region; removing the first ion pouring mark; forming the second ion pour mask on the semi-conductor substrate; the second ion pour mask covers the first element region, but expose the semi-conductor substrate of first element region, and the shallow groove insulated virtual structure inside the virtual region; pouring the doping agent into the exposed semi-substrate of second element region, to form the second doping region.
Description
Technical field
The present invention relates to a kind of semiconductor technology, particularly a kind of method that can reduce the wafer charge injury that produces in the integrated circuit technology process.
Background technology
In semiconductor element industry, often must in Semiconductor substrate, add the number of dopant (dopant) with the control charged carriers, the method for this adding dopant is called injects dopant or ion implantation technology.Basically, ion implantor can generally be divided into several subsystems: ion source, beam transmission subsystem, terminal station system, gas or steam supply system, vacuum system and power system.And according to ion beam current size and energy that it provided, ion implantation device can be categorized as again high electric current (high-current) and middle electric current (medium-current) ion implantor, and height (million electron volt), in (between 5,000 and 250,000 electron-volts), low (being lower than five kilo electron volts) energetic ion implanter.Usually, high current ion implanter is equipped with plasma flooded system (plasma floodsystem) or electronics drip washing equipment (electron shower) to be used for charged dopant electric neutralityization in addition.
The major defect that ion injects is the structural damage that can cause in silicon to a certain degree.This infringement may be wafer in plasma environment or in the ion implantation technology process, because a large amount of stored charge of wafer surface is caused.
In above-mentioned plasma environment or in the ion implantation technology process, the a large amount of stored charges of wafer surface may be by being produced on the capacitance structure on the wafer surface, the Semiconductor substrate of the grid of MOS (metal-oxide-semiconductor) transistor and below for example, pass through with current forms, and cause the injury of the grid oxic horizon between grid and Semiconductor substrate, more seriously, may since moment high electric current pass through to cause the grid structure explosion and permanent damage.Aforementioned in plasma environment, the reason that makes a large amount of stored charges of wafer surface might be because the skewness of plasma density or electron temperature; Perhaps in the ion implantation technology process, may be since the beam of charged ions that projects wafer surface not by due to the electric neutralityization fully.
In relevant prior art, United States Patent (USP) the 5th, 998, disclose for No. 282 and a kind ofly can be reduced in the plasma environment or the method for the wafer charge injury that is caused in the ion implantation technology process, it mainly is to utilize in the manufacture process of integrated circuit, forms on the Cutting Road around each integrated circuit lead and can lead path of current off, so, the possibility that makes electric current pass through the integrated circuit lead inner member reduces, thereby reduces injury.Yet, point out also simultaneously in this United States Patent (USP) that because the restriction of circuit element configuration will constituting similar this in integrated circuit lead in addition, to lead path of current off very difficult.
Summary of the invention
Main purpose of the present invention is to provide a kind of method that can reduce the wafer charge injury that produces in the integrated circuit technology process.
According to a preferred embodiment of the invention, the invention discloses a kind of method that in semiconductor technology, reduces wafer charge injury, including provides semi-conductive substrate, have a plurality of integrated circuit leads on it, respectively this integrated circuit lead is separated from each other by Cutting Road, wherein respectively this integrated circuit lead includes at least one first element area, second element area and shallow-channel insulation nominal region, and wherein this first element area shared area ratio in this integrated circuit lead is bigger, and this second element area shared area ratio in this integrated circuit lead is less; Form the first ion injecting mask on this Semiconductor substrate, this first ion injecting mask covers this second element area and this shallow-channel insulation nominal region, but exposes the surface of this Semiconductor substrate of this first element area; Dopant is injected the surface of this Semiconductor substrate that this first element area comes out, to form first doped region; Remove this first ion injecting mask; On this Semiconductor substrate, form the second ion injecting mask, this second ion injecting mask covers this first element area, but exposes the surface and the interior a plurality of shallow-channel insulation dummy structures of this shallow-channel insulation nominal region of this Semiconductor substrate of this second element area; And dopant injected the surface of this Semiconductor substrate that this second element area comes out, to form second doped region.
For feature of the present invention and technology contents are further understood, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 illustrates is the schematic layout pattern that the ion that forms the lightly doped drain of high voltage devices or source electrode in Semiconductor substrate injects photoresist mask.
Fig. 2 illustrates is the schematic layout pattern that the preferred embodiment of the present invention forms the lightly doped drain of high voltage devices or source electrode in Semiconductor substrate ion injects photoresist mask.
What Fig. 3 to Fig. 6 illustrated is the preferred embodiment of the present invention reduces the method for wafer charge injury in integrated circuit fabrication process generalized section.
What Fig. 7 to Figure 10 illustrated is another preferred embodiment of the present invention reduces the method for wafer charge injury in integrated circuit fabrication process generalized section.
Description of reference numerals
1 wafer, 10 integrated circuit leads
12 cut 20 ions injects photoresist mask
The 20a ion injects photoresist mask 22 openings
24 illusory opening 100 Semiconductor substrate
102 low voltage component zones, 101 high voltage devices zone
103 medium pressure elements zone, 104 ditches insulation nominal region
110 shallow groove insulation configuration, 1 21 grids
122 grids, 123 grids
124 shallow-channel insulation dummy structures, 131 grid oxic horizons
132 grid oxic horizons, 133 grid oxic horizons
141 lightly doped drains/source region 142 lightly doped drains/source region
143 lightly doped drains/source region 210 ions inject photoresist mask
220 ions inject photoresist mask 230 ions and inject photoresist mask
304 inactive regions
310 ions inject photoresist mask 320 ions and inject photoresist mask
320a opening 324 substrates
330 ions inject photoresist mask 330a opening
Embodiment
As previously mentioned, employed high current ion implanter is equipped with plasma flooded system (plasma flood system) or electronics drip washing equipment (electron shower) usually in the ion implantation technology, be used for charged dopant electric neutralityization, to suppress the amount of charge of wafer surface positively charged.Yet in some cases, employed ion implantor is not equipped with or does not use this plasma flooded system or electronics drip washing equipment in the ion implantation technology.For instance, medium current ion implanter is promptly for the Consideration of ion implantation dosage, and is not equipped with this plasma flooded system or electronics drip washing equipment.The ion implantation dosage that this medium current ion implanter provided is usually between 1E11～1E14atoms/cm
2, ion implantation energy is commonly used to form lightly doped drain or source electrode (lightly doped drain/source) zone usually between 10KeV～500KeV in Semiconductor substrate.
See also Fig. 1, it illustrates is the schematic layout pattern that the ion that forms the lightly doped drain of high voltage devices or source electrode in Semiconductor substrate injects photoresist mask 20.As shown in Figure 1, integrated circuit lead 10 by around Cutting Road 12 and wafer on other integrated circuit lead that is close to separate.On Cutting Road 12, can form many feeler switchs usually, in order to the integrality of monitoring integrated circuit tube core 10.In integrated circuit lead 10, the ion trap of element, grid oxic horizon, polysilicon gate and shallow-channel insulation zone have been produced on the Semiconductor substrate as silicon substrate etc.
In Semiconductor substrate, form in the technology of the lightly doped drain of high voltage devices or source electrode, ion injects the overwhelming majority zone that photoresist mask 20 has hidden integrated circuit lead 10, little opening 22 is only arranged near the lower left corner in as figure, expose the transistorized position of high-pressure metal-oxide-semiconductor in the Semiconductor substrate, prepare to use aforesaid medium current ion implanter in Semiconductor substrate, to form transistorized lightly doped drain of high-pressure metal-oxide-semiconductor or source electrode.
Because aforesaid high-pressure metal-oxide-semiconductor transistor only accounts for the sub-fraction of integrated circuit lead 10,, often only account for about 0.2%～2% of single IC for both tube core 10 areas so the opening 22 of ion injection photoresist mask 20 is very little usually.In forming transistorized lightly doped drain of high-pressure metal-oxide-semiconductor or source electrode process, owing to use the medium current ion implanter that is not equipped with plasma flooded system or electronics drip washing equipment, so the destruction that can produce integrated circuit lead 10 inner members, for example grid structure explosion.
Hence one can see that, how to reduce above-mentioned in forming transistorized lightly doped drain of high-pressure metal-oxide-semiconductor or source electrode process, use the medium current ion implanter that is not equipped with plasma flooded system or electronics drip washing equipment, the destruction that produces integrated circuit lead 10 inner members has become the task of top priority.
See also Fig. 2, it illustrates is the schematic layout pattern that the preferred embodiment of the present invention forms the lightly doped drain of high voltage devices or source electrode in Semiconductor substrate ion injects photoresist mask 20a.As shown in Figure 2, have a plurality of integrated circuit leads 10 on the wafer 1, and separate by the Cutting Road 12 around it and other contiguous integrated circuit lead.On Cutting Road 12, can form many feeler switchs usually, in order to the integrality of monitoring integrated circuit tube core 10.In integrated circuit lead 10, the ion trap of element, grid oxic horizon, polysilicon gate and shallow-channel insulation zone have been produced on the Semiconductor substrate as silicon substrate etc.
Ion injects the opening 22 that photoresist mask 20a includes small size, and it exposes the below and is about to form the lightly doped drain of high voltage MOS element or the substrate surface of source electrode with medium current ion implanter.The substrate surface (calling " component exposure zone " in the following text) of the high voltage MOS element that these are come out via the opening 22 of small size is generally the drain-source zone of the high voltage MOS element that the shallow-channel insulation zone isolated.In addition, ion injects photoresist mask 20a and includes many illusory openings 24 in addition, and it is distributed in other position in the integrated circuit lead 10.At this moment, the Cutting Road 12 around the integrated circuit lead 10 can the part crested, and perhaps Cutting Road 12 can not cover fully.
According to a preferred embodiment of the invention, the illusory opening 24 of ion injection photoresist mask 20a is to be used for painstakingly increasing the substrate surface that is come out at the lightly doped drain of aforementioned medium current ion implanter formation high voltage MOS element or the technology of source electrode.Illusory opening 24 need expose not element zone (calling " not element exposed region " in the following text), in other words, can not be formed with the element of source circuit on the substrate surface that illusory opening 24 is come out.According to a preferred embodiment of the invention, illusory opening 24 can be in order to reduce the dummy pattern that load effect (loading effect) is used when forming the shallow-channel insulation zone.According to a preferred embodiment of the invention, with the area addition of the not element exposed region of the component exposure of aforementioned opening 22 zone and illusory opening 24, its area occupied ratio preferably can surpass more than 5% of each integrated circuit lead 10 area.
Major advantage of the present invention is to utilize illusory opening 24 painstakingly to increase the substrate surface that is come out, and can not be formed with the element (not element exposed region) of source circuit on the substrate surface that illusory opening 24 is come out, so the electric current that can increase integrated circuit lead 10 inside is effectively led the path off, reduces issuable wafer charge injury in the ion implantation technology of the lightly doped drain carry out high voltage device or source electrode widely.
For more clearly demonstrating the present invention, see also Fig. 3 to Fig. 6, what it illustrated is the preferred embodiment of the present invention reduces the method for wafer charge injury in integrated circuit fabrication process generalized section.At first, as shown in Figure 3, Semiconductor substrate 100 includes high voltage device zone 101, low voltage component zone 102, medium pressure element zone 103 and shallow-channel insulation nominal region 104, and shallow groove insulation configuration 110 has been formed on Semiconductor substrate 100 surfaces with the element in the electrically isolated zones of different.Be simplified illustration, the ion trap that is formed in the Semiconductor substrate 100 is not drawn.
In high voltage device zone 101, form the high-pressure metal-oxide-semiconductor transistor unit, for example, 5 volts of metal-oxide-semiconductor transistor elements.For instance, do explanation with the grid 121 of the high-pressure N-shaped metal-oxide-semiconductor transistor element in the high voltage device zone 101.Grid 121 is formed on the thick grid oxic horizon 131, and with Semiconductor substrate 100 electrical isolation of below.In low voltage component zone 102, form the low pressure metal-oxide-semiconductor transistor element, for example, 1.8 volts of metal-oxide-semiconductor transistor elements.For instance, do explanation with the grid 122 of the low pressure N type metal-oxide-semiconductor transistor element in the low voltage component zone 102.Grid 122 is formed on the grid oxic horizon 132, and with Semiconductor substrate 100 electrical isolation of below, wherein the thickness of grid oxic horizon 132 is less than grid oxic horizon 131.In medium pressure element zone 103, press metal-oxide-semiconductor transistor element in the formation, for example, 3.3 volts of metal-oxide-semiconductor transistor elements.For instance, do explanation with the grid 123 of the middle pressure N type metal-oxide-semiconductor transistor element in the medium pressure element zone 103.Grid 123 is formed on the grid oxic horizon 133, and with Semiconductor substrate 100 electrical isolation of below, wherein the thickness of grid oxic horizon 133 is less than grid oxic horizon 131.In shallow-channel insulation nominal region 104, a plurality of shallow-channel insulation dummy structures 124 have been formed with.These a plurality of shallow-channel insulation dummy structures 124 have Semiconductor substrate 100 surfaces of coming out, and can not be formed with the element of any active circuit on it.
As shown in Figure 4, then on Semiconductor substrate 100 surfaces, form a lightly doped drain (LDD) ion and inject photoresist mask 210, it covers high voltage device zone 101, low voltage component zone 102 and shallow-channel insulation nominal region 104, but exposes medium pressure element zone 103.Because in integrated circuit lead 10, the shared area ratio in medium pressure element zone 103 is bigger, and at this moment, Semiconductor substrate 100 surface areas that come out are also relatively bigger.
Then, the Semiconductor substrate 100 that is covered with LDD ion injection photoresist mask 210 is placed in the ion implantor platform, medium current ion implanter platform for example, carry out the LDD ion implantation technology, dopants such as arsenic are injected Semiconductor substrate 100 surfaces of coming out, so in medium pressure element zone 103, form lightly doped drain/source region 143.According to a preferred embodiment of the invention, the ion implantor of carrying out the LDD ion implantation technology is a medium current ion implanter, and the consideration Dose Problem is not used plasma flooded system or electronics drip washing equipment.Next, the LDD ion being injected photoresist mask 210 removes.
As shown in Figure 5, then on Semiconductor substrate 100 surfaces, form another LDD ion and inject photoresist mask 220, it covers medium pressure element zone 103 and low voltage component zone 102, but exposes high voltage device zone 101 and shallow-channel insulation nominal region 104.Because in integrated circuit lead 10, the shared area ratio in high voltage device zone 101 is less, and at this moment, Semiconductor substrate 100 surface areas that come out are also relatively less, as previously mentioned, only account for about 0.2%～2% of single IC for both tube core 10 areas approximately.Therefore, in order to increase Semiconductor substrate 100 surface areas that in the LDD ion implantation technology process come out in integrated circuit lead 10 inside, the present invention painstakingly injects photoresist mask 220 at the LDD ion a plurality of shallow-channel insulation dummy structures 124 in shallow-channel insulation nominal region 104 and the shallow-channel insulation nominal region 104 is come out.
By injecting photoresist mask 220 a plurality of shallow-channel insulation dummy structures 124 in shallow-channel insulation nominal region 104 and the shallow-channel insulation nominal region 104 are come out at the LDD ion, can be so that long-pending more than 5% of single IC for both tube core 10 areas that is increased to of the semiconductor substrate surface that is come out in the LDD ion implantation technology process of high voltage device.Then, the Semiconductor substrate 100 that is covered with LDD ion injection photoresist mask 220 is placed in the ion implantor platform, medium current ion implanter for example, carry out the LDD ion implantation technology, dopants such as arsenic are injected Semiconductor substrate 100 surfaces of coming out, so in high voltage device zone 101, form lightly doped drain/source region 141.Similarly, the ion implantor of carrying out the LDD ion implantation technology is a medium current ion implanter, and the consideration Dose Problem is not used plasma flooded system or electronics drip washing equipment.Next, the LDD ion being injected photoresist mask 220 removes.
As shown in Figure 6, then on Semiconductor substrate 100 surfaces, form another LDD ion and inject photoresist mask 230, it covers medium pressure element zone 103 and high voltage device zone 101, but exposes low voltage component zone 102 and shallow-channel insulation nominal region 104.Because in integrated circuit lead 10, if the shared area ratio in low voltage component zone 102 is same hour, Semiconductor substrate 100 surface areas that come out are also relatively less, for example less than 5% of single IC for both tube core 10 areas.Therefore, in order to increase Semiconductor substrate 100 surface areas that in the LDD ion implantation technology process come out in integrated circuit lead 10 inside, the present invention injects photoresist mask 230 at the LDD ion a plurality of shallow-channel insulation dummy structures 124 in shallow-channel insulation nominal region 104 and the shallow-channel insulation nominal region 104 is come out.
Then, the Semiconductor substrate 100 that is covered with LDD ion injection photoresist mask 230 is placed in the ion implantor platform, medium current ion implanter for example, carry out the LDD ion implantation technology, dopants such as arsenic are injected Semiconductor substrate 100 surfaces of coming out, so in low voltage component zone 102, form lightly doped drain/source region 142.Similarly, the ion implantor of carrying out the LDD ion implantation technology is a medium current ion implanter, and the consideration Dose Problem is not used plasma flooded system or electronics drip washing equipment.Next, the LDD ion being injected photoresist mask 230 removes.Ensuing semiconductor technology step then comprises the heavy doping of formation, drain/source of gate lateral wall and metal silicide technology or the like, and it is all the person skilled in art knows, and therefore repeats no more.What deserves to be mentioned is that the heavy doping technology of follow-up drain/source is normally carried out in high current ion implanter.
See also Fig. 7 to Figure 10, what it illustrated is another preferred embodiment of the present invention reduces the method for wafer charge injury in integrated circuit fabrication process generalized section.At first, as shown in Figure 7, Semiconductor substrate 100 includes high voltage device zone 101, low voltage component zone 102, medium pressure element zone 103 and inactive regions 304, and shallow groove insulation configuration 110 has been formed on Semiconductor substrate 100 surfaces with the element in the electrically isolated zones of different.Be simplified illustration, the ion trap that is formed in the Semiconductor substrate 100 is not drawn.
In high voltage device zone 101, form the high-pressure metal-oxide-semiconductor transistor unit, for example, 5 volts of metal-oxide-semiconductor transistor elements.For instance, do explanation with the grid 121 of the high-pressure N-shaped metal-oxide-semiconductor transistor element in the high voltage device zone 101.Grid 121 is formed on the thick grid oxic horizon 131, and with Semiconductor substrate 100 electrical isolation of below.In low voltage component zone 102, be used for forming the low pressure metal-oxide-semiconductor transistor element, for example, 1.8 volts of metal-oxide-semiconductor transistor elements.For instance, do explanation with the grid 122 of the low pressure N type metal-oxide-semiconductor transistor element in the low voltage component zone 102.Grid 122 is formed on the grid oxic horizon 132, and with Semiconductor substrate 100 electrical isolation of below, wherein the thickness of grid oxic horizon 132 is less than grid oxic horizon 131.In medium pressure element zone 103, press metal-oxide-semiconductor transistor element in the formation, for example, 3.3 volts of metal-oxide-semiconductor transistor elements.For instance, do explanation with the grid 123 of the middle pressure N type metal-oxide-semiconductor transistor element in the medium pressure element zone 103.Grid 123 is formed on the grid oxic horizon 133, and with Semiconductor substrate 100 electrical isolation of below, wherein the thickness of grid oxic horizon 133 is less than grid oxic horizon 131.So-called inactive regions 304, that is have the substrate surface 324 that comes out, but can not be formed with the element of any active circuit on it.
As shown in Figure 8, then on Semiconductor substrate 100 surfaces, form a lightly doped drain (LDD) ion and inject photoresist mask 310, it covers high voltage device zone 101, low voltage component zone 102 and inactive regions 304, but exposes medium pressure element zone 103.Because in integrated circuit lead 10, the shared area ratio in medium pressure element zone 103 is bigger, and at this moment, Semiconductor substrate 100 surface areas that come out are also relatively bigger.
Then, the Semiconductor substrate 100 that is covered with LDD ion injection photoresist mask 310 is placed in the ion implantor platform, medium current ion implanter platform for example, carry out the LDD ion implantation technology, dopants such as arsenic are injected Semiconductor substrate 100 surfaces of coming out, so in medium pressure element zone 103, form lightly doped drain/source region 143.The ion implantor of carrying out the LDD ion implantation technology is a medium current ion implanter, and the consideration Dose Problem is not used plasma flooded system or electronics drip washing equipment.Next, the LDD ion being injected photoresist mask 310 removes.
As shown in Figure 9, then form another LDD ion and inject photoresist mask 320 on Semiconductor substrate 100 surfaces, it covers medium pressure element zone 103 and low voltage component zone 102.The LDD ion injects photoresist mask 320 and exposes high voltage device zone 101, and the LDD ion injects photoresist mask 320 and have an opening 320a, uses the substrate surface 324 in the inactive regions 304 that exposes part.According to the present invention, the opening 320a of LDD ion injection photoresist mask 320 can be identical with the STI dummy pattern of etch-back irrigation canals and ditches filling insulating barrier.
Aforesaid STI dummy pattern promptly is when being used for avoiding carrying out the grinding of sti trench canal filling insulating barrier, issuable load effect above the larger area inactive regions (loading effect) or residue problem, therefore, before grinding, utilize the STI dummy pattern that the sti trench canal filling insulating barrier of this inactive regions top is etched back to predetermined thickness earlier.
Then, the Semiconductor substrate 100 that is covered with LDD ion injection photoresist mask 320 is placed in the ion implantor platform, medium current ion implanter for example, carry out the LDD ion implantation technology, dopants such as arsenic are injected Semiconductor substrate 100 surfaces of coming out, so in high voltage device zone 101, form lightly doped drain/source region 141.Similarly, the ion implantor of carrying out the LDD ion implantation technology is a medium current ion implanter, and the consideration Dose Problem is not used plasma flooded system or electronics drip washing equipment.Next, the LDD ion being injected photoresist mask 320 removes.
As shown in figure 10, then on Semiconductor substrate 100 surfaces, form another LDD ion and inject photoresist mask 330, it covers medium pressure element zone 103 and high voltage device zone 101, but expose low voltage component zone 102, and the LDD ion injects photoresist mask 330 and has opening 330a and expose substrate surface 324 in the part inactive regions 304.
Then, the Semiconductor substrate 100 that is covered with LDD ion injection photoresist mask 330 is placed in the ion implantor platform, medium current ion implanter for example, carry out the LDD ion implantation technology, dopants such as arsenic are injected Semiconductor substrate 100 surfaces of coming out, so in low voltage component zone 102, form lightly doped drain/source region 142.Similarly, the ion implantor of carrying out the LDD ion implantation technology is a medium current ion implanter, and the consideration Dose Problem is not used plasma flooded system or electronics drip washing equipment.Next, the LDD ion being injected photoresist mask 330 removes.
Though preferred embodiment disclosed by the invention is that example is done explanation with the lightly doped drain source region that forms in the high voltage device zone in Semiconductor substrate, but the present invention should only not be limited in the ion implantation technology, after one of ordinary skill in the art should be understood spirit of the present invention, be applied in other similar application, for example can cause equally in the plasma etching machine or plasma process of wafer charge injury effect.In addition, in aforementioned the preferred embodiments of the present invention, the ion in high voltage device zone, low voltage component zone and medium pressure element zone injects sequencing can adjust exchange, for example, carries out the LDD injection of low voltage component or the LDD injection of advanced horizontal high voltage element earlier and all can.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (10)
1, a kind of method that reduces wafer charge injury in semiconductor technology includes:
Semi-conductive substrate is provided, have a plurality of integrated circuit leads on it, each described integrated circuit lead is separated from each other by Cutting Road, wherein each described integrated circuit lead includes at least one first element area, second element area and shallow-channel insulation nominal region, and wherein said first element area shared area ratio in described integrated circuit lead is bigger, and described second element area shared area ratio in described integrated circuit lead is less;
Form the first ion injecting mask on described Semiconductor substrate, the described first ion injecting mask covers described second element area and described shallow-channel insulation nominal region, but exposes the surface of the described Semiconductor substrate of described first element area;
Dopant is injected the surface of the described Semiconductor substrate that described first element area comes out, to form first doped region;
Remove the described first ion injecting mask;
On described Semiconductor substrate, form the second ion injecting mask, the described second ion injecting mask covers described first element area, but exposes the surface and the interior a plurality of shallow-channel insulation dummy structures of described shallow-channel insulation nominal region of the described Semiconductor substrate of described second element area; And
Dopant is injected the surface of the described Semiconductor substrate that described second element area comes out, to form second doped region.
2, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 1 wherein is formed with first grid in described first element area and the first grid oxide layer is formed between described first grid and the described Semiconductor substrate.
3, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 1 wherein is formed with second grid in described second element area and the second grid oxide layer is formed between described second grid and the described Semiconductor substrate.
4, the method that in semiconductor technology, reduces wafer charge injury as claimed in claim 1, wherein said second element area is the high voltage device zone, and described second doped region is the lightly doped drain zone that is about to be formed on the metal-oxide-semiconductor transistor element in the described high voltage device zone.
5, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 4, wherein said metal-oxide-semiconductor transistor element is the nmos pass transistor element.
6, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 1, wherein said a plurality of shallow-channel insulation dummy structures expose the surface of the described Semiconductor substrate of part in each described integrated circuit lead.
7, the method that reduces wafer charge injury in semiconductor technology as claimed in claim 1, the step of wherein dopant being injected the surface of the described Semiconductor substrate that described second element area comes out is to carry out at a medium current ion implanter.
8, a kind of method of making integrated circuit includes:
Provide semi-conductive substrate, the Cutting Road that has at least one integrated circuit lead zone on it and center on described integrated circuit lead zone;
In described integrated circuit lead zone, form first shallow-channel insulation zone and the second shallow-channel insulation zone simultaneously, the wherein said first shallow-channel insulation zone is formed between first element area and second element area to produce electrical isolation, and have a plurality of shallow-channel insulation dummy structures in the described second shallow-channel insulation zone, and wherein said first element area shared area ratio in described integrated circuit lead is bigger, and described second element area shared area ratio in described integrated circuit lead is less;
In described first element area and in described second element area, form first grid and second grid respectively;
Cover described first element area, but expose the described a plurality of shallow-channel insulation dummy structures in described second element area and the described second shallow-channel insulation zone; And
Carry out an ion implantation technology, dopant is injected the surface of the described Semiconductor substrate of described second element area that exposes.
9, the method for making integrated circuit as claimed in claim 8, wherein said ion implantation technology are to carry out in a medium current ion implanter.
10, a kind of method that reduces wafer charge injury in semiconductor technology includes:
Semi-conductive substrate is provided, have a plurality of integrated circuit leads on it, each described integrated circuit lead is separated from each other by Cutting Road, wherein each described integrated circuit lead includes at least one first element area, second element area and inactive regions, and wherein said first element area shared area ratio in described integrated circuit lead is bigger, and described second element area shared area ratio in described integrated circuit lead is less;
Form the first ion injecting mask on described Semiconductor substrate, the described first ion injecting mask covers described second element area and described inactive regions, but exposes the surface of the described Semiconductor substrate of described first element area;
Dopant is injected the surface of the described Semiconductor substrate that described first element area comes out, to form first doped region;
Remove the described first ion injecting mask;
On described Semiconductor substrate, form the second ion injecting mask, the described second ion injecting mask covers described first element area, but exposes the surface and the interior described Semiconductor substrate of described inactive regions of the described Semiconductor substrate of described second element area; And
Dopant is injected the surface of the described Semiconductor substrate that described second element area comes out, to form second doped region.
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| US6013927A (en) * | 1998-03-31 | 2000-01-11 | Vlsi Technology, Inc. | Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same |
| US6235642B1 (en) * | 2000-01-14 | 2001-05-22 | United Microelectronics Corporation | Method for reducing plasma charging damages |
| US20040171197A1 (en) * | 2003-02-27 | 2004-09-02 | Park Seong-Hee | Method for fabricating a high voltage dual gate device |
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