CN1227407A - Method for producing double voltage MOS transistor - Google Patents

Method for producing double voltage MOS transistor Download PDF

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CN1227407A
CN1227407A CN 98105351 CN98105351A CN1227407A CN 1227407 A CN1227407 A CN 1227407A CN 98105351 CN98105351 CN 98105351 CN 98105351 A CN98105351 A CN 98105351A CN 1227407 A CN1227407 A CN 1227407A
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metal oxide
oxide semiconductor
ion implantation
high voltage
voltage
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CN 98105351
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CN1123917C (en
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林志光
柯宗义
洪允锭
张崇德
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联诚积体电路股份有限公司
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Abstract

The production of double-voltage MOS transistor include the following steps; the first ion implantation to form several lightly doped areas outside the first and the second polysilicon grids in the substrate; the formation of one photoresist layer to expose predetermined high-voltage transistor; the second ion implantation through large inclination angle technological process to form several buffering layers overlapping with the lightly doped areas of high-voltage transistors; the elimination of the photoresist layer; the formation of the first and the second interval walls; and the third ionimplantation to form several heavily doped source and drain areas.

Description

制作双电压金属氧化物半导体晶体管的方法 The method of manufacturing a dual voltage metal oxide semiconductor transistor

本发明涉及一种金属氧化物半导体(Metal Oxide Semiconductor;MOS)晶体管的制作,特别是涉及一种双电压金属氧化物半导体晶体管的制作。 The present invention relates to a metal-oxide semiconductor (Metal Oxide Semiconductor; MOS) transistor production, particularly to produce a dual voltage metal oxide semiconductor transistor.

目前在深次微米的应用上有朝向于双操作电压的倾向。 Currently there is a tendency toward a dual operating voltage on the application of the deep sub-micron. 由于通道长度的刻度缩小,使得核心元件的操作电压低于输出与输入元件的操作电压。 Since the scale of the channel length is reduced, so that the core of the operating voltage lower than the operating voltage of the output member and the input member. 然而,目前的制作工艺所面临的主要障碍来自于元件在高电压与低电压下的运行结果无法同时令人满意。 However, the main obstacle faced by the production process from the operating results element at high voltage and low voltage is not satisfactory at the same time. 尤其是高电压元件常无法符合可靠性的要求。 In particular a high-voltage element often can not meet the reliability requirements.

图1A至图1E是传统双电压金属氧化物半导体晶体管的制作流程图。 1A to 1E is a flowchart illustrating a conventional dual voltage produced metal-oxide semiconductor transistor. 请参照图1A,起始材料为具有轻掺杂(约5×1014到1×1016原子/立方厘米)的<100>硅基底100。 Referring to Figure 1A, the starting material is a lightly doped (about 5 × 1014 to 1 × 1016 atoms / cm3) of & lt; 100 & gt; silicon substrate 100. 在硅基底100上欲形成有源区与场区。 On the silicon substrate 100 is formed to be the active region and field region. 可在硅基底100上覆盖一层厚的氧化物,利用区域氧化(Local Oxidation)工艺选择性地氧化场区102。 It may cover a thick layer of oxide on the silicon substrate 100, using the oxide region (Local Oxidation) process of selectively oxidizing the field region 102. 或选择另一种方法,以浅沟渠隔离(shallowtrenchisolation)的技术限定有源区。 Or selecting another method, a shallow trench isolation (shallowtrenchisolation) technology defines an active region. n井可以利用光掩模覆盖于p型基底100而露出预定n井的区域,再将n型掺杂物注入p型基底100而制得。 n-well it can be covered using a photomask to expose the p-type substrate 100 and the n-well region of a predetermined, then n-type dopants into p-type substrate 100 is prepared.

请参照图1B,在基底100上成长第一个栅极氧化层。 Referring to Figure 1B, a first gate oxide layer is grown on the substrate 100. 再经由部分蚀刻该栅极氧化层,只在欲形成高电压n型金属氧化物半导体(High Voltage n-typeMetal Oxide Semiconductor;HV NMOS)的基底表面上留下栅极氧化层。 Leaving a gate oxide layer on the substrate surface; and then partially etched through the gate oxide layer, to be formed only in the high-voltage n-type metal oxide semiconductor (HV NMOS High Voltage n-typeMetal Oxide Semiconductor). 此栅极氧化层为104a。 This gate oxide layer 104a. 接着进行另一个栅极氧化层的形成工艺,以生成一栅极氧化层106。 Followed by another forming process of gate oxide layer, to form a gate oxide layer 106. 其覆盖第一个栅极氧化层104a以及欲形成低电压n型金属氧化物半导体(Low Voltage n-type Metal Oxide Semiconductor;LV NMOS)的部分硅基底100表面。 Covering the first gate oxide layer 104a to be formed and the low-voltage n-type metal oxide semiconductor (Low Voltage n-type Metal Oxide Semiconductor; LV NMOS) part of the surface of the silicon substrate 100. 因此,高电压NMOS的栅极氧化层是由第一个栅极氧化层104a与覆盖其上的栅极氧化层106共同组成的。 Thus, high voltage NMOS gate oxide layer is composed of a first gate oxide layer 104a and the cover on the gate oxide layer 106 which is composed of. 所以,其厚度大于低电压NMOS栅极氧化层的厚度。 Therefore, a thickness greater than the thickness of the low-voltage NMOS gate oxide layer.

请参照图1C,以化学气相沉积法(CVD)将厚度约为0.1-0.3μm的多晶硅沉积于整个基底100之上。 Referring to 1C, the chemical vapor deposition (CVD) to a thickness of about 0.1-0.3μm polysilicon 100 is deposited over the entire substrate. 基于均一性、纯度与经济的考虑,选择以低压化学气相沉积(LPCVD)的方法作为沉积多晶硅的主要技术。 Based uniformity, purity, and economic considerations, the method selected low pressure chemical vapor deposition (LPCVD) technique as a main polysilicon deposition. 接着,以光掩模保护要形成栅极的区域,在光致抗蚀剂曝光与显影之后,将多晶硅层蚀刻,例如利用干式蚀刻。 Subsequently, a photomask to protect the gate region to be formed, after the photoresist exposure and development, etching the polysilicon layer, for example by dry etching. 于是在HV NMOS形成一栅极108,LV NMOS形成一栅极110。 Thus forming a gate electrode in the HV NMOS 108, LV NMOS gate electrode 110 is formed a. 通常HV NMOS的栅极108的长度比LV NMOS的栅极110的长度宽。 HV NMOS gate length is typically wider than the length 108 of the LV NMOS gate electrode 110.

由于目前漏极结构MOS的通道长度趋于越来越小,严重的热载子效应将会造成无法接受的性能变坏。 As the current drain structure of the MOS channel length tends to become smaller, serious hot carrier effect would cause unacceptable deterioration of the performance. 为了克服这一问题,另一个替代的漏极结构---轻掺杂漏极(LDD)为较好的选择。 To overcome this problem, other alternative structures --- drain lightly doped drain (LDD) is a better choice. 由于图1D只绘示出NMOS,因此只叙述NMOS LDD的制作工艺。 Since FIG. 1D shows only an NMOS, and therefore only the NMOS LDD described production process.

请参照图1D,绘示NMOS LDD结构的形成图。 Referring to 1D, a schematic diagram of FIG NMOS LDD structure is formed. 首先利用光致抗蚀剂掩模覆盖PMOS,再藉由至少二次的离子注入方式以形成HV MOS与LVMOS的漏极。 Firstly, a photoresist mask covers the PMOS, then at least twice by the ion implantation to form a drain of the HV MOS and LVMOS. 而该二次离子注入的方法在栅极侧壁的间隙壁形成前与形成后进行。 And the secondary ion implantation method after forming the gate sidewall spacer before forming. 请参照图1D,绘示第一次离子注入自动对准栅极108与110,其渗透栅极氧化层106与第一个栅极氧化层104a,而分别形成HV MOS与LVMOS的轻掺杂区112与114。 Referring to 1D, a schematic illustrating the first ion implantation 108 self-aligned with the gate electrode 110, which penetrate gate oxide layer 106 and a first gate oxide layer 104a, and are formed with LVMOS HV MOS lightly doped region 112 and 114. 对NMOS器件优选的是剂量约为1-5×1014原子/立方厘米的磷元素或砷元素。 NMOS devices is preferred dosage is about 1-5 × 1014 phosphorus or arsenic atoms / cc.

请参照图1E,绘示厚度约为0.08-0.10μm的栅极侧壁间隙壁120。 Referring to 1E, the thickness of approximately 0.08-0.10μm illustrates the gate sidewall spacers 120. 形成间隙壁120的优选制作工艺包括:在基底100之上沉积一层硅化物并回蚀刻,然后在HV MOS与LV MOS的漏极区注入重掺杂以低电阻区域122。 Preferably spacer 120 is formed fabrication process comprises: depositing a layer of silicide over the substrate 100 and etched back, and then the heavily doped implanted region 122 to the low-resistance drain region of HV MOS and LV MOS. 而此低电阻区域122则与低掺杂区122合并。 And this low-resistance region 122 and the low-doped region 122 merge. 对NMOS器件而言,此注入的剂量约为1×1015原子/立方厘米的磷元素或砷元素。 For NMOS devices, the injection of this dose of about 1 × 1015 phosphorus or arsenic atoms / cc.

因此,本发明的主要目的在于提供一种双电压金属氧化物半导体晶体管的制作方法,使得能满足HV MOS与LV MOS晶体管的性能要求。 Therefore, a primary object of the present invention to provide a manufacturing method of a dual voltage metal oxide semiconductor transistor, so that can meet the performance requirements of HV MOS LV MOS transistor.

为实现上述目的,本发明提出一种形成双电压金属氧化物半导体晶体管的方法,其中,具有轻微掺杂漏极结构的HV MOS与LV MOS已形成在一硅基底的有源区上。 To achieve the above object, the present invention provides a method of dual voltage MOS transistor is formed, wherein the lightly doped drain structure having a HV MOS and LV MOS formed on the active region of a silicon substrate. 此方法的步骤包括:在高电压金属氧化物半导体晶体管之外形成一光致抗蚀剂层,其后进行一大角度倾斜离子注入以形成缓冲层,并且使其重叠于高电压金属氧化物半导体晶体管的轻掺杂区之上,最后再除去光致抗蚀剂。 This method comprises the step of: forming in addition to high voltage metal oxide semiconductor transistor a photoresist layer, thereafter a large tilt angle ion implantation to form a buffer layer, and so as to overlap the high voltage metal oxide semiconductor over the lightly doped region of the transistor, and finally the photoresist is removed.

为使本发明的上述目的、特征、和优点能更明显易懂,下面特举一优选实施例,并配合附图作详细说明。 For the present invention the above object, features, and advantages will become apparent from the following a preferred embodiment cited Patent, with the drawings and detailed description. 附图中:图1A至图1E绘示一传统的双电压金属氧化物半体导晶体管的制造流程的剖面图;以及图2A至图2F绘示依照本发明的优选实施例的双电压金属氧化物半导体晶体管制造流程的剖面图。 In the drawings: Figures 1A to 1E illustrate a conventional process for producing a metal oxide cross-sectional view of half of a dual voltage transistor conductive; and FIGS. 2A to 2F illustrate an example of a metal oxide dual voltage according to a preferred embodiment of the present invention. the semiconductor manufacturing process cross-sectional view of the transistor thereof.

请参照图2A,优选的起始材料为具有轻掺杂(约5×1014至1×1016原子/立方厘米)的<100>硅基底200。 Referring to Figure 2A, the preferred starting material is a lightly doped (about 5 × 1014 to 1 × 1016 atoms / cm3) of & lt; 100 & gt; silicon substrate 200. 在硅基底200上欲形成有源区与场区。 On the silicon substrate 200 is formed to be the active region and field region. 可在硅基底200上覆盖一层厚的氧化物,利用区域氧化(Local Oxidation)工艺选择性地氧化场区202。 It may cover a thick layer of oxide on the silicon substrate 200, using the oxide region (Local Oxidation) process of selectively oxidizing the field region 202. 另一种方法是以浅沟渠隔离(shallow trench isolation)的技术限定有源区。 Another method is based on a shallow trench isolation (shallow trench isolation) defining an active region in the art. 互补式金属氧化物半导体的技术不论是对n通道或是p通道晶体管而言,均需在相同的基底上制作,而相对应的井区也在此基底上形成。 CMOS technology both for the n-channel or p-channel transistor, on the same substrate required in the production, but also the corresponding well region is formed on this substrate. 由于本发明以p型浅掺杂基底为优选的实施例,在此,至少应制作一n井(未显示)。 Since the present invention is to lightly doped p-type substrate is the preferred embodiment, in this case, should at least produce an n-well (not shown). 以光致抗蚀剂掩模覆盖p基底200而露出预定的n井区域,再利用离子注入的方式将高浓度的n型掺杂注入于基底200,而其掺杂的浓度必须足以补偿相对应的基底掺杂。 In the photoresist mask covering the p-substrate 200 to expose a predetermined region of n-well, then manner by ion implantation of high concentration n-type dopant implanted in the substrate 200, and doping concentration must be sufficient to compensate for the corresponding doped substrate. 所以,n井掺杂的最佳浓度约高于p型基底200的5-10倍。 Therefore, the optimum doping concentration of the n-well is about 5-10 times higher than the p-type substrate 200. 双电压n型金属氧化物半导体晶体管的结构与制作为此双电压金属氧化物半导体晶体管的优选实施例。 Structure and production of dual-voltage n-type metal oxide semiconductor transistor for this dual voltage MOS transistor in the preferred embodiment. 而双电压n型金属氧化物半导体晶体管则可在p型基底、n型基底的p井或双井基底的p井上形成。 And dual-voltage n-type metal oxide semiconductor transistor may be a p-type substrate, the p-type substrate n well or p-substrate forming the twin uphole.

请参照图2B,在p井注入的光致抗蚀剂掩模剥除之后,在基底200成长第一个栅极氧化层。 Referring to Figure 2B, after the photoresist mask is stripped of the p-well implantation, the growth substrate 200 is a first gate oxide layer. 此氧化层的形成通常是通过干式氧化法在氯气的环境下进行。 Forming the oxide layer is usually carried out in a chlorine gas environment through a dry oxidation method. 其后,进行临限电压调整注入。 Thereafter, the threshold voltage adjustment implant. 优选的实施例是以能量约为50-100KeV,注入剂量约为1×1012-1×1013原子/立方厘米下的含硼离子,例如,BF2+,而此条件下硼可穿透第一个栅极氧化层,但由于硼离子无法得到足够的能量,所以无法渗透至场氧化层202。 Preferred embodiments are described about the energy of 50-100, an implantation dose of about 1 × 1012-1 × 1013 ions containing boron in atoms / cm, e.g., BF2 +, and under this condition a first gate boron penetrable gate oxide layer, but boron ions sufficient energy can not be obtained, it is impossible to penetrate field oxide 202. 在许多制作工艺中,也有在基底上先形成一先驱栅极氧化层,再透过该先驱栅极氧化层进行一注入后,将该先驱栅极氧化层剥除,并再成长一栅极氧化层。 In many fabrication process, but also to form a gate oxide layer pioneer on a substrate, the latter then implanted through the gate oxide layer pioneer, pioneer of the gate oxide layer is stripped and a gate oxide regrowth Floor. 此优选实施例是将第一个栅极氧化物经由部分蚀刻,只在欲形成HV NMOS的基底表面上留下栅极氧化层。 The preferred embodiment is a gate oxide via the first partially etched to leave only the gate oxide layer to be formed on the substrate surface of the HV NMOS. 此栅极氧化层为204a。 This gate oxide layer 204a. 接着进行另一个栅极氧化层的形成工艺,以生产一栅极氧化层206,覆盖第一个栅极氧化层204a以及欲形成LV NMOS的部分硅基底200表面。 Followed by another forming process of gate oxide layer to produce a gate oxide layer 206, covering the first gate oxide layer 204a and the surface of the silicon substrate 200 is formed to be part of the LV NMOS. 因此,HV NMOS的栅极氧化层是由第一个栅极氧化层204a与重叠其上的栅极氧化物206共同组成的。 Thus, HV NMOS gate oxide layer is composed of a first gate oxide layer 204a which overlaps with the gate oxide 206 composed of. 故其厚度高于LV NMOS的栅极氧化层的厚度。 Therefore, the thickness thereof is higher than the thickness of the gate oxide layer of the LV NMOS.

请参照图2C,以化学气相沉积法(CVD)将厚度约为0.1-0.3μm的多晶硅层沉积于整个基底200之上。 Referring to Figure 2C, in a chemical vapor deposition (CVD) polysilicon layer is deposited to a thickness of about 0.1-0.3μm 200 over the entire substrate. 多晶硅沉积的优选实施例是将硅烷在温度范围约为580-650℃条件下裂解。 Preferred embodiments silane polysilicon deposition is cleaved under conditions of a temperature range of about 580-650 ℃. 基于均一性、纯度与经济的考虑,选择以低压气相沉积法(LPCVD)作为沉积多晶硅的主要技术。 Based uniformity, purity, and economic considerations, to select a low pressure vapor deposition (LPCVD) deposited polysilicon as a main technique. 传统LPCVD系统的制作工艺通常包括三个程序。 Traditional production process LPCVD system generally includes three procedures. 首先在总压为0.3-1乇(torr)下通入100%的硅烷(SiH4),其次在相近的压力下以氮气输入25%的硅烷,最后在垂直流动的等温反应器中在压力约为1乇下通入以氢气稀释的25%的硅烷。 First, at a total pressure of 0.3-1 torr (Torr or) into the 100% silane (of SiH4), followed by nitrogen input of 25% of silane at a pressure close, the pressure in the last vertical flow isothermal reactors is about 1 Torr diluted into 25% hydrogen silane. 以低压气相沉积法沉积多晶硅后,在后续的制作工艺中,再以离子注入将杂质掺杂其中。 After deposition of the polysilicon to a low pressure vapor deposition process, in a subsequent fabrication process, and then the impurity is doped by ion implantation therein. 接着限定该栅极结构的图形。 Pattern the gate structure is then defined. 将光致抗蚀剂曝光、显影后以光致抗蚀剂掩模保护待形成栅极的区域后,再将多晶硅层进行蚀刻(干式蚀刻为优选的实施例),于是在HV NMOS形成一栅极208,LV NMOS处形成一栅极210。 Exposing the photoresist, the photoresist mask to protect the gate region to be formed after development, and then the polysilicon layer is etched (dry etching for the preferred embodiment), then formed in a HV NMOS gate 208, LV NMOS gate electrode 210 is formed at a. 通常HV NMOS的栅极208的栅极长度比LV NMOS的栅极的长度210宽。 Typically HV NMOS gate length of the gate 208 is wider than the length of the gate 210 of the LV NMOS.

由于目前漏极结构MOS所具有的通道长度越作越小,严重的热载子效应将会造成无法接受的性能恶化。 As the current drain of the MOS structure having a channel length smaller as more severe hot carrier effect would cause unacceptable performance degradation. 为了克服这一个问题,另一个替代的漏极结构-轻掺杂漏极(LDD)是优选的方式。 To overcome this problem, another alternate configuration of the drain - a lightly doped drain (LDD) is preferred. 由于图2D只绘示出NMOS,因此只叙述NMOS LDD的制作工艺。 Since only FIG. 2D illustrates an NMOS, and therefore only the NMOS LDD described production process. 请参照图2D,绘示NMOS LDD结构的形成图。 Referring to Figure 2D, shown in FIG NMOS LDD structure is formed. 首先,利用光致抗蚀剂掩模覆盖PMOS,再藉由至少二次的离子注入方式以形成HV MOS与LVMOS的漏极。 First, a photoresist mask covers the PMOS, then at least twice by the ion implantation to form a drain of the HV MOS and LVMOS. 而此两次离子注入的方法分别在侧壁间隙壁形成前与形成后进行。 This two ion implantation and a method respectively formed on the front and the rear sidewall spacers are formed. 此外,HV NMOS的漏极更进一步通过另一个注入的制作工艺,以形成一缓冲层。 Further, the drain of the HV NMOS further injected through another production process, to form a buffer layer.

请参照图2D,进行自动对准栅极208与210的第一次离子注入制作工艺,渗透栅极氧化层206与第一个栅极氧化层204a,而分别形成HV MOS与LV MOS的轻掺杂区212与214。 Referring to Figure 2D, the automatic alignment of the first gate electrode 208 and the ion implantation 210 of a production process, a gate oxide 206 and the first gate oxide layer permeable layer 204a, and are formed with lightly doped HV MOS the LV MOS heteroaryl area 212 and 214. 与NMOS器件的优选实施例是剂量约为1-5×1014原子/立方厘米的磷元素或砷元素。 NMOS device with the preferred embodiment is a dosage of about 1-5 × 1014 phosphorus or arsenic atoms / cc.

请参照图2E,以光致抗蚀剂掩模覆盖基底200,但裸露出已形成的HVNMOS。 Referring to FIG 2E, the photoresist mask to cover the substrate 200, but the formed bare HVNMOS. 光致抗蚀剂掩模216的制作方法依照传统的步骤:包括涂底、涂布、软烤、曝光、显影和剥除。 The photoresist mask 216 according to a conventional method for manufacturing the step of: including priming, coating, soft baking, exposure, development and stripping. 而后,再以大角度倾斜离子注入的技术,在次微米的金属氧化物半导体场效应晶体管上形成漏极。 Then, again at a large angle oblique ion implantation technique, a drain is formed on the metal oxide semiconductor field effect transistor sub-micron. 此技术较为简单,且提供结构的控制与器件在执行上的改善。 This relatively simple technique, and provides improved control device structure in implementation. 大角度倾斜离子注入是使用一大的倾斜角度与目标晶圆在一个位置上旋转,无需将晶圆移开于旋转盘的技术。 Large angle oblique ion implantation using a large inclination angle in a certain rotational position of the wafer, the wafer is removed in the art without rotating disk. 其注入的优选实施例是以约为15-60。 Preferred embodiments thereof are approximately 15-60 injection. 的角度,1×1012-1×1015原子/立方厘米的剂量。 Angle, dose 1 × 1012-1 × 1015 atoms / cc. 在二次植进之间将晶圆旋转,可使得在栅极208之下的缓冲层的渗透掺杂的结果相对称。 The implanted wafer rotation between the secondary inlet and the result may be that the permeation of the buffer layer 208 under the gate of said opposite doping. 形成HV NMOS的缓冲层218的掺杂可为磷,注入的能量范围约在30-100KeV,或为砷,注入的能量范围约在100-300KeV。 HV NMOS doped buffer layer 218 may be a phosphorus implantation energy in the range of about 30-100KeV, or arsenic, implantation energy in the range of about 100-300KeV. 大角度倾斜离子注入的技术可在栅极208之下,任意控制欲形成的缓冲层深度与其掺杂的浓度而无需使用扩散的步骤。 Large angle oblique ion implantation technique may be under the gate 208, to be formed arbitrarily controlled without using a diffusion depth of the step of concentration of the buffer layer is doped thereto. 由于HV NMOS的缓冲层218使电场的效应降低,因此改善热电子效应所造成的退化。 Since HV NMOS buffer layer 218 decreases so that the effect of the electric field, thus improving the thermal degradation caused by electronic effects.

请参照图2F,绘示在光致抗蚀剂掩模216移除之后,栅极侧壁间隙壁220的形成图。 Referring to FIG. 2F, shows, after the photoresist mask 216 is removed, the gate sidewall spacers 220 formed of FIG. 优选的侧壁间隙壁厚度约为0.08-0.15μm。 The preferred wall thickness of the side wall a gap of approximately 0.08-0.15μm. 其优选的制作工艺包括:在基底200之上沉积硅化层后进行回蚀刻,再以高剂量的掺杂分别注入于HV NMOS与LV NMOS的漏极区以形成低电阻区222。 The preferred production process comprises: etching back the deposited silicide layer over a substrate 200, and then to a high dose of doping are implanted in the drain region of HV NMOS and LV NMOS region 222 to form a low resistance. 而此低电阻区222也与轻掺杂区合并。 This low-resistance region 222 and also merged with the lightly doped region. 对NMOS而言以约为1×1015原子/立方厘米剂量的砷或磷进行注入较好。 Of an NMOS to about 1 × 1015 atoms / cc dose of arsenic or phosphorus are implanted preferred.

根据以上的简述,HV MOS器件上的缓冲层218在间隙壁220与深掺杂区222形成之前形成。 The above briefly, the buffer layer 218 HV MOS devices formed in the gap before the deep wall 220 and doped regions 222 are formed. 然而,由于缓冲层218是以大角度倾斜离子注入的技术制得,因此只要增加注入的能量,此注入制作工艺也可在间隙壁形成之后进行。 However, since the buffer layer 218 is large angle oblique ion implantation technique made, so long as the increase of the implantation energy, implantation of this manufacturing process may be performed after the spacer is formed. 所以,这些程序在执行时顺序可以相反。 Therefore, when the execution sequence of these procedures may be reversed. 亦即,可先形成间隙壁220与深掺杂区222之后再形成缓冲层218。 That is, the buffer layer 218 may be formed first and then a gap 222 is formed after the wall 220 and the deep dopant regions.

另外,由于HV NMOS的缓冲层218重叠轻掺杂区212,因此可将形成轻掺杂区212的步骤省去以简化制作工艺。 Further, since the HV NMOS buffer layer 218 overlaps the lightly doped region 212, thus the step of forming a lightly doped region 212 is omitted to simplify the manufacturing process.

虽然已结合一优选实施例揭露了本发明,但是其并非用以限定本发明,本领域的技术人员在不脱离本发明的精神和范围内,可作出各种更动与润饰,因此本发明的保护范围应当由后附的权利要求限定。 While there has been disclosed in conjunction with a preferred embodiment of the present invention, but not intended to limit the present invention, those skilled in the art without departing from the spirit and scope of the present invention, various changes or modifications may be made, thus the present invention the scope of protection should be made to the appended claims.

Claims (12)

1. 1. 一种制作双金属氧化物半导体晶体管的方法,其中,一预定高电压金属氧化物半导体晶体管的一第一多晶硅栅极与一预定低电压金属氧化物半导体晶体管的一第二多晶硅栅极已形成于一基底的一有源区上,该方法包括下列步骤:进行一第一离子注入,以在该基底中、该第一多晶硅栅极与该第二多晶硅栅极之外形成多个轻掺杂区;形成一光致抗蚀剂层,暴露出该预定的高电压金属氧化物半导体晶体管;进行一第二离子注入,以形成多个缓冲层与该高电压金属氧化物半导体晶体管的这些轻掺杂区重叠,其中该第二离子注入是采用一大角度倾斜技术;去除该光致抗蚀剂层;在该第一多晶硅栅极的侧壁形成一第一间隙壁与在该第二多晶硅栅极的侧壁形成一第二间隙壁;以及进行一第三离子注入,以在该第一间隙壁与该第二间隙壁之外的该基底中形成多个重 A method of making a double metal oxide semiconductor transistor, wherein a first polysilicon gate a predetermined high voltage metal oxide semiconductor transistor and a predetermined low voltage metal oxide semiconductor transistor and a second polysilicon gate electrode has an active region formed on a substrate, the method comprising the steps of: performing a first ion implantation to the substrate, the first polysilicon gate and the second polysilicon gate of forming a plurality of lightly doped outer region; forming a photoresist layer, exposing the predetermined high voltage metal oxide semiconductor transistor; a plurality of buffer layers and a metal oxide of the high voltage for a second ion implantation to form the lightly doped semiconductor region of the transistor overlap, wherein the second ion implantation is the use of a large angle tilt technique; removing the photoresist layer; forming a first side wall of the first polysilicon gate spacer formed on a sidewall of the second gate of a second polysilicon spacer; and performing a third ion implantation to the substrate outside the first spacer and the second spacer is formed more weight 杂的源极与漏极区域。 Heteroaryl source and drain regions.
2. 2. 如权利要求1所述的方法,其中该大角度倾斜技术所用的角度范围约为15-60度,所用的剂量约为1×1012-1×1015原子/立方厘米。 The method according to claim 1, wherein the inclination angle technique used large angular range of about 15-60 degrees, at a dose of about 1 × 1012-1 × 1015 atoms / cc.
3. 3. 如权利要求2所述的方法,其中该高电压金属氧化物半导体晶体管上的这些缓冲层的掺杂包括砷,注入的能量约为100-300KeV。 The method according to claim 2, wherein the doped buffer layer on the high-voltage MOS transistor comprising arsenic, implantation energy is about 100-300KeV.
4. 4. 如权利要求2所述的方法,其中该高电压金属氧化物半导体晶体管上的这些缓冲层的掺杂包括磷,注入的能量约为30-100KeV。 The method according to claim 2, wherein the doped buffer layer on the high-voltage MOS transistor include phosphorus, implantation energy is about 30-100KeV.
5. 5. 一种形成双金属氧化物半导体晶体管的方法,其中具有多个轻掺杂漏极结构的一高电压金属氧化物半导体晶体管与一低电压金属氧化物半导体晶体管已形成于一基底的有源区上,该方法包括下列步骤:形成一光致抗蚀剂层,暴露出该高电压金属氧化物半导体晶体管;进行一大角度倾斜离子注入,以形成多个缓冲层,与该高电压金属氧化物半导体的这些轻掺杂区重叠;以及去除该光致抗蚀剂层。 A method of double metal oxide semiconductor transistor is formed, having a plurality of lightly doped drain structure of a high voltage metal oxide semiconductor transistor and the active region of a low voltage MOS transistor formed on a substrate the method comprising the steps of: forming a photoresist layer, exposing the high voltage metal oxide semiconductor transistor; performing a large angle oblique ion implantation, to form a plurality of buffer layers, and the high-voltage semiconductor metal oxide these lightly doped regions overlap; and removing the photoresist layer.
6. 6. 如权利要求5所述的方法,其中该大角度倾斜离子所用的角度范围约为15-60度,剂量约为1×1012-1×1015原子/立方厘米。 The method as claimed in claim 5, wherein the inclination angle of a large angle range of the ion used is about 15-60 degrees, the dose is about 1 × 1012-1 × 1015 atoms / cc.
7. 7. 如权利要求6所述的方法,其中该高电压金属氧化物半导体晶体管上的这些缓冲层的掺杂包括砷,注入的能量约为100-300KeV。 The method according to claim 6, wherein the doped buffer layer on the high-voltage MOS transistor comprising arsenic, implantation energy is about 100-300KeV.
8. 8. 如权利要求6所述的方法,其中该高电压金属氧化物半导体晶体管上的这些缓冲层的掺杂包括磷,注入的能量约为30-100KeV。 The method according to claim 6, wherein the doped buffer layer on the high-voltage MOS transistor include phosphorus, implantation energy is about 30-100KeV.
9. 9. 一种形成多金属氧化物半导体晶体管的方法,其中具有多个轻掺杂漏极结构的一第一高电压金属氧化物半导体晶体管、一第二高电压金属氧化物半导体晶体管与一低电压金属氧化物半导体晶体管已形成于一基底的一有源区之上,该方法包括下列步骤:形成一第一光致抗蚀剂层,暴露出该第一高电压金属氧化物半导体晶体管;进行一第一大角度倾斜离子注入,以形成多个第一缓冲层,其与该第一高电压金属氧化物半导体晶体管的多个轻掺杂区重叠;去除该第一光致抗蚀剂层;形成一第二光致抗蚀剂层,暴露出该第二高电压金属氧化物半导体晶体管;进行一第二大角度倾斜离子注入,以形成多个第二缓冲层,其与该第二高电压金属氧化物半导体晶体管的多个轻掺杂区重叠;以及去除该第二光致抗蚀剂层。 A method of forming a multi-metal oxide semiconductor transistor, wherein a high voltage having a first plurality of MOS transistors of the LDD structure, a second high voltage MOS transistor and a low voltage metal oxide semiconductor transistor has an active region formed on a substrate, the method comprising the steps of: forming a first photoresist layer to expose the first high voltage metal oxide semiconductor transistor; a first be large angle oblique ion implantation, to form a plurality of first buffer layer, which overlaps with the plurality of lightly doped regions of the first high voltage metal oxide semiconductor transistor; removing the first photoresist layer; forming a second two photoresist layer, exposing the second high voltage metal oxide semiconductor transistor; performing a second large angle oblique ion implantation, to form a plurality of second buffer layer and the second high voltage metal oxide a plurality of lightly doped regions of the semiconductor transistor overlaps; and removing the second photoresist layer.
10. 10. 如权利要求9的述的方法,其中该第一高电压的操作电压高于该第二高电压的操作电压;以及该第一大角度倾斜离子注入的剂量高于该第二大角度倾斜离子注入的剂量。 The method as described in claim 9, wherein the operating voltage of the first high voltage higher than the operating voltage of the second high voltage; and a first large angle oblique ion implantation dose is higher than the second large-angle oblique ion implantation dose.
11. 11. 如权利要求9的述的方法,其中该第一高电压的操作电压低于该第二高电压的操作电压;以及该第二大角度倾斜离子注入的剂量高于该第一大角度倾斜离子注入的剂量。 The method as described in claim 9, wherein the first operating voltage lower than the operating voltage of the high voltage to the second high voltage; and a second large angle oblique ion implantation dose is higher than the first large-angle oblique ion implantation dose.
12. 12. 一种形成双层金属氧化物半导体晶体管的方法,该方法包括下列步骤:提供一基底,其中至少已限定一有源区;形成一第一栅极氧化层,覆盖于该有源区所欲形成的区域上,以形成一高电压金属氧化物半导体晶体管;形成一第二栅极氧化层,覆盖于该第一栅极氧化层与该有源区所欲形成的区域上,以形成一低电压金属氧化物半导体晶体管;在该所欲形成的区域之上形成一第一多晶硅栅极,以形成该高电压金属氧化物半导体;在该所欲形成的区域之上形成一第二多晶硅栅极,以形成该低电压金属氧化物半导体;进行一第一离子注入,渗透该第一栅极氧化层与该第二栅极氧化层,以在该基底的该第一多晶硅栅极与该第二多晶硅栅极之外形成多个轻掺杂区;形成一光致抗蚀剂层,暴露出该预定的高电压金属氧化物半导体晶体管;进行一第二离子注入以形 A method for double-MOS transistor is formed, the method comprising the steps of: providing a substrate, wherein the at least one active region has been defined; forming a first gate oxide layer, is formed covering the active region desired on the region, to form a high voltage metal oxide semiconductor transistor; forming a second gate oxide layer covering a first region of the gate oxide layer formed in the active region desired to form a low voltage a metal oxide semiconductor transistor; forming a polysilicon gate over a first region of the desired form to form the high-voltage metal oxide semiconductor; forming a second polycrystalline region over the desired formation silicon gate to form the low voltage metal oxide semiconductor; performing a first ion implantation, the first gate oxide layer and the second gate oxide layer permeable to the polysilicon gate of the first substrate a plurality of electrodes are formed outside the lightly doped region and a second polysilicon gate; forming a photoresist layer, exposing the predetermined high voltage metal oxide semiconductor transistor; performing a second ion implantation to form 多个缓冲层与该高电压金属氧化物半导体晶体管的这些轻掺杂区重叠,其中该第二离子注入采用一大角度倾斜离子注入技术;去除该光致抗蚀剂层;在该第一多晶硅栅极的一侧壁形成一第一间隙壁,在该第二多晶硅栅极的一侧壁形成一第二间隙壁;以及进行一第三离子注入,以在该第一间隙壁与该第二间隙壁之外的基底中形成多个重掺杂源极与漏极区域。 A plurality of buffer layers overlapping with the high-voltage metal oxide semiconductor transistor These lightly doped regions, wherein the second ion implantation using a large angle oblique ion implantation technique; removing the photoresist layer; the first plurality a polysilicon gate sidewall forming a first spacer, a second spacer formed on a sidewall of the second gate polysilicon; and performing a third ion implantation to the first gap in the wall outside of the second substrate and the spacer are formed a plurality of heavily doped source and drain regions.
CN 98105351 1998-02-27 1998-02-27 Method for prodn. of double voltage MOS transistor CN1123917C (en)

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