JPS6135564A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS6135564A JPS6135564A JP15701484A JP15701484A JPS6135564A JP S6135564 A JPS6135564 A JP S6135564A JP 15701484 A JP15701484 A JP 15701484A JP 15701484 A JP15701484 A JP 15701484A JP S6135564 A JPS6135564 A JP S6135564A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon film
- wiring
- layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 11
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 29
- 238000000034 method Methods 0.000 abstract description 7
- 239000011521 glass Substances 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000000873 masking effect Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract 1
- 230000008719 thickening Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 30
- 239000010410 layer Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical group N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
Abstract
Description
【発明の詳細な説明】
本発明は、石英ガラスあるいはソーダガラス等の絶縁基
板上に形成される薄膜トランジスタの特性向上に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the characteristics of thin film transistors formed on insulating substrates such as quartz glass or soda glass.
本発明は半導体止して多結晶シリコンを用い一〇説明す
るが、他の半導体材看にも同様に適用される。Although the present invention will be described using polycrystalline silicon as a semiconductor material, it is equally applicable to other semiconductor materials.
薄膜トラシジス、りは、高価なシリコン基板−１：に形
成する半導体素子に比べ、安価なガラス基板上に形成で
きると共に、工程数も少なく、プロセスコストも安価に
できる利点をもっている。Compared to semiconductor devices formed on expensive silicon substrates, thin film transistors have the advantage of being able to be formed on inexpensive glass substrates, requiring fewer steps, and reducing process costs.
第１図（ロ）（６）を用いて従来の薄膜トランジスタの
構造を示し、その欠点を述べる。The structure of a conventional thin film transistor will be shown using FIG. 1(b)(6), and its drawbacks will be described.
ガラス基板１上に多結晶シリコン膜の島２を形成したの
ち、表面を酸化し、ゲート電極となる多結晶シリコン膜
４を形成する。次にイオン打込秒法により、ソース・ド
レイン拡散層５を形成し、眉間絶縁膜６を形成したのち
に、コンタクトホールを開口したものを第１図（α）Ｋ
示す。After forming an island 2 of a polycrystalline silicon film on a glass substrate 1, the surface is oxidized to form a polycrystalline silicon film 4 that will become a gate electrode. Next, a source/drain diffusion layer 5 is formed by the second ion implantation method, and a glabella insulating film 6 is formed, after which a contact hole is opened.
show.
次にアルミ°ニウムあるいはアルミニウム合金（以下Ａ
Ｊと略記する）配線７を第１図（６）の様に形成する。Next, aluminum or aluminum alloy (hereinafter referred to as A)
A wiring 7 (abbreviated as J) is formed as shown in FIG. 1 (6).
第１図（ロ）からも判る様に、従来の方式では、コンタ
クトホール開口時に弗化アンモニウムと弗酸の混合液で
レジスト膜をマスクに層間絶縁膜である酸化シリコン膜
をエツチング除去するので、エツチング液の中のアンモ
ニア基が、多結晶シリコン膜をエツチングしてしまう。As can be seen from Figure 1 (B), in the conventional method, when opening a contact hole, the silicon oxide film, which is an interlayer insulating film, is etched away using a mixed solution of ammonium fluoride and hydrofluoric acid using a resist film as a mask. Ammonia groups in the etching solution end up etching the polycrystalline silicon film.
この為コンタクト開口部の多結晶シリコン膜が簿くなり
、第１図（ｂ）の様に配線材料であるへ！膜を形成して
−も、多結晶シリコン膜とのコンタクトが充分とれない
。As a result, the polycrystalline silicon film in the contact opening becomes bulky and becomes a wiring material as shown in Figure 1(b)! Even if a film is formed, sufficient contact with the polycrystalline silicon film cannot be made.
これは、薄膜トランジスタのオンネフ特性を向上する為
には、能動素子となる多結晶シリコン膜を薄くする必要
があり、この時、コンタクト部の多結晶シリコン膜の膜
厚が問題となって来るものであり、従来のプロセス設計
値は、このコンタクト部の多結晶シリコン膜の膜厚が大
きく影響していた。This is because in order to improve the on-nef characteristics of a thin film transistor, it is necessary to make the polycrystalline silicon film that becomes the active element thinner, and at this time, the thickness of the polycrystalline silicon film in the contact area becomes a problem. However, the conventional process design values were largely influenced by the thickness of the polycrystalline silicon film in the contact area.
改善策としては、能動素子部の多結晶シリコン膜を薄く
し、コンタクト部の多結晶シリコン膜を厚くする方法が
考えられるが、少なくともホトエッチ工程を１工程多く
行なう必要があり、コストアップになり効果が少ない。A possible improvement measure would be to thin the polycrystalline silicon film in the active element area and thicken the polycrystalline silicon film in the contact area, but this would require at least one additional photoetching process, which would increase costs and make it less effective. Less is.
本発明は、この様な従来の欠点を除去したものであり、
その目的とするところは、薄い能動素子部の多結晶シリ
コン膜と配線材料とのコンタクトが充分取れる構造の薄
膜トランジスタを提供す２゜ことである。The present invention eliminates these conventional drawbacks,
The purpose is to provide a thin film transistor having a structure in which sufficient contact can be made between the thin polycrystalline silicon film of the active element portion and the wiring material.
以下第２図（α）（ｂ）を用いて本発明の詳細な説明す
る。The present invention will be described in detail below using FIGS. 2(α) and (b).
ガラス基板ｌｌ上に多結晶シ゛リコン膜の島：１２を形
成したのち、表面を酸化したのち、ゲート電極となる多
結晶シリコン膜１４を形成する。次にイオン打込み法に
より、ソースｅドレイン拡散層１５を形成し、層間絶縁
膜１６を形成したのちに、コンタクトホールを開口する
。引続き全面に第１層目となる多結晶シリコン膜１８を
形成するとともに、連続゛して第２層目となるＡＪを全
面に形成したものを第１図ＣｃＬ）に示す。After forming an island 12 of a polycrystalline silicon film on a glass substrate 11, the surface is oxidized, and then a polycrystalline silicon film 14 that will become a gate electrode is formed. Next, a source/drain diffusion layer 15 is formed by ion implantation, an interlayer insulating film 16 is formed, and then a contact hole is opened. Subsequently, a polycrystalline silicon film 18 as a first layer is formed on the entire surface, and AJ as a second layer is continuously formed on the entire surface as shown in FIG. 1 (CcL).
次にホトリングラフイー技術により従来方法と同様に八
！の配線１７ｔ−形成すると同時に％へ！をマスキング
材にして、第１層目となる多結晶シバコン膜をエツチン
グ除去する；
この様に、第２層目となるＡＪ配線の下に多結晶シリコ
ン膜を第１層目として形成することによりコンタクト部
の多結晶シリコン膜の厚みを厚くする事と同等の効果が
ある。Next, using Photolingraphie technology, 8! % at the same time as wiring 17t- is formed! Using as a masking material, remove the first layer of polycrystalline silicon film by etching; In this way, by forming the first layer of polycrystalline silicon film under the AJ wiring, which will become the second layer. This has the same effect as increasing the thickness of the polycrystalline silicon film in the contact area.
又、この場合にはＡ！既配線パターニングが完了後、Ａ
ｌｌ、配線をマスキング材に第１層目の多結晶シリコン
膜をエツチング除去するので、新たにホトマスクを用意
する必要がなく、コストアップにはならない。Also, in this case A! After the patterning of the existing wiring is completed, A
Since the first layer polycrystalline silicon film is removed by etching using the wiring as a masking material, there is no need to prepare a new photomask, and the cost does not increase.
さらに、第１層目の多−結晶シリコン膜は通常不純物を
ドーピングしであるので、能動素子部との′コンタクト
抵抗は、通常の約１０分の工程度に下がる。これは通常
能動素子部へはイオン打込み法で不純物を注入するので
あまり濃度が高くできない為である。Furthermore, since the first layer polycrystalline silicon film is usually doped with impurities, the contact resistance with the active element portion is reduced to the normal process time of about 10 minutes. This is because impurities are usually implanted into the active element portion by ion implantation, so the concentration cannot be very high.
これに対して、本発明によれば、コンタクト部の多結晶
シリコン膜は、不純物濃度が高く厚みも充分厚いので、
能動素子部とのコンタクトはなんら問題にならない。In contrast, according to the present invention, the polycrystalline silicon film in the contact portion has a high impurity concentration and is sufficiently thick.
Contact with the active element part poses no problem.
以上説明した如く、本発明によれば、能動素子部の半導
体材料を薄くする事が可能であり、特性向上可能な薄膜
トランジスタを提供できるものである。As described above, according to the present invention, it is possible to make the semiconductor material of the active element portion thinner, and it is possible to provide a thin film transistor whose characteristics can be improved.
第１図（ロ））（６）は従来の薄膜トランジスタの断面
１′；ηである。
第２図（Ｇ） （６）は本発明による実施例を示す断面
図である。
図中１．１１はガラス基板、２．１２はトランジスタと
なる多結晶シリコン膜の島、８．１３はゲート酸化膜、
４，１４はゲート電極、５，１５はソースおるいはドレ
イン、６．１６は層間絶ｉ＆膜、７．１７はＡＪ配線、
１８は第１層目となる多結晶シリコン膜である。
以 上FIG. 1(b))(6) shows a cross section 1'; η of a conventional thin film transistor. FIG. 2(G) (6) is a sectional view showing an embodiment according to the present invention. In the figure, 1.11 is a glass substrate, 2.12 is an island of polycrystalline silicon film that becomes a transistor, 8.13 is a gate oxide film,
4 and 14 are gate electrodes, 5 and 15 are sources or drains, 6.16 is interlayer insulation film, 7.17 is AJ wiring,
18 is a polycrystalline silicon film serving as the first layer. that's all
Claims (2)
、前記薄膜トランジスタは、ソース配線、ドレイン配線
およびゲート配線に接続され、該ソース配線及びドレイ
ン配線は２層構造になっている事を特徴とする薄膜トラ
ンジスタ。(1) A thin film transistor formed on an insulating substrate, wherein the thin film transistor is connected to a source wiring, a drain wiring, and a gate wiring, and the source wiring and drain wiring have a two-layer structure.
ール開口後に、第１層目の配線材料を形成し引続き、第
２層目の配線材料を形成した事を特徴とする特許請求の
範囲第１項記載の薄膜トランジスタ。(2) A first layer of wiring material is formed after opening contact holes for connecting source wiring and drain wiring, and then a second layer of wiring material is formed. thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59157014A JPH0783126B2 (en) | 1984-07-27 | 1984-07-27 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59157014A JPH0783126B2 (en) | 1984-07-27 | 1984-07-27 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6135564A true JPS6135564A (en) | 1986-02-20 |
| JPH0783126B2 JPH0783126B2 (en) | 1995-09-06 |
Family
ID=15640292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59157014A Expired - Lifetime JPH0783126B2 (en) | 1984-07-27 | 1984-07-27 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783126B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58127321A (en) * | 1982-01-23 | 1983-07-29 | Canon Inc | Preparation of semiconductor device |
| JPS5940582A (en) * | 1982-08-30 | 1984-03-06 | Seiko Epson Corp | Semiconductor device |
-
1984
- 1984-07-27 JP JP59157014A patent/JPH0783126B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58127321A (en) * | 1982-01-23 | 1983-07-29 | Canon Inc | Preparation of semiconductor device |
| JPS5940582A (en) * | 1982-08-30 | 1984-03-06 | Seiko Epson Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0783126B2 (en) | 1995-09-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |