JPH0783126B2 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistorInfo
- Publication number
- JPH0783126B2 JPH0783126B2 JP59157014A JP15701484A JPH0783126B2 JP H0783126 B2 JPH0783126 B2 JP H0783126B2 JP 59157014 A JP59157014 A JP 59157014A JP 15701484 A JP15701484 A JP 15701484A JP H0783126 B2 JPH0783126 B2 JP H0783126B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- thin film
- polycrystalline silicon
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 239000010408 film Substances 0.000 claims description 44
- 239000010410 layer Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 2
- 239000011810 insulating material Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 23
- 238000000034 method Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical group N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 本発明は、石英ガラスあるいはソーダガラス等の絶縁基
板上に形成される薄膜トランジスタの特性向上に関す
る。The present invention relates to improvement of characteristics of a thin film transistor formed on an insulating substrate such as quartz glass or soda glass.
本発明は半導体として多結晶シリコンを用いて説明する
が、他の半導体材料にも同様に適用される。Although the present invention is described using polycrystalline silicon as a semiconductor, it applies to other semiconductor materials as well.
薄膜トランジスタは、高価なシリコン基板上に形成する
半導体素子に比べ、安価なガラス基板上に形成できると
共に、工程数も少なく、プロセスコストも安価にできる
利点をもっている。The thin film transistor has an advantage that it can be formed on an inexpensive glass substrate as compared with a semiconductor element formed on an expensive silicon substrate, the number of steps is small, and the process cost can be reduced.
第１図（ａ）（ｂ）を用いて従来の薄膜トランジスタの
構造を示し、その欠点を述べる。The structure of a conventional thin film transistor will be shown with reference to FIGS. 1 (a) and 1 (b), and its drawbacks will be described.
ガラス基板１上に多結晶シリコン膜の島２を形成したの
ち、表面を酸化し、ゲート電極となる多結晶シリコン膜
４を形成する。次にイオン打込み法により、ソース・ド
レイン拡散層５を形成し、層間絶縁膜６を形成したのち
に、コンタクトホールを開口したものを第１図（ａ）に
示す。After forming the islands 2 of the polycrystalline silicon film on the glass substrate 1, the surface is oxidized to form the polycrystalline silicon film 4 to be the gate electrode. Next, a source / drain diffusion layer 5 is formed by an ion implantation method, an interlayer insulating film 6 is formed, and then a contact hole is opened, which is shown in FIG.
次にアルミニウムあるいはアルミニウム合金（以下Alと
略記する）配線７を第１図（ｂ）の様に形成する。Next, aluminum or aluminum alloy (hereinafter abbreviated as Al) wiring 7 is formed as shown in FIG. 1 (b).
第１図（ａ）からも判る様に、従来の方式では、コンタ
クトホール開口時に弗化アンモニウムと弗酸の混合液で
レジスト膜をマスクに層間絶縁膜である酸化シリコン膜
をエツチング除去するので、エツチング液の中のアンモ
ニア基が、多結晶シリコン膜をエツチングしてしまう。
この為コンタクト開口部の多結晶シリコン膜が薄くな
り、第１図（ｂ）の様に配線材料であるAl膜を形成して
も、多結晶シリコン膜とのコンタクトが充分とれない。As can be seen from FIG. 1 (a), in the conventional method, when the contact hole is opened, the silicon oxide film as the interlayer insulating film is etched and removed by using the mixed solution of ammonium fluoride and hydrofluoric acid with the resist film as a mask. Ammonia groups in the etching liquid etch the polycrystalline silicon film.
Therefore, the polycrystalline silicon film in the contact opening becomes thin, and even if the Al film which is the wiring material is formed as shown in FIG. 1B, the polycrystalline silicon film cannot be sufficiently contacted.
これは、薄膜トランジスタのオンオフ特性を向上する為
には、能動素子となる多結晶シリコン膜を薄くする必要
があり、この時、コンタクト部の多結晶シリコン膜の膜
厚が問題となって来るものであり、従来のプロセス設計
値は、このコンタクト部の多結晶シリコン膜の膜厚が大
きく影響していた。This is because in order to improve the on / off characteristics of the thin film transistor, it is necessary to thin the polycrystalline silicon film that becomes the active element, and at this time, the film thickness of the polycrystalline silicon film in the contact part becomes a problem. Therefore, the film thickness of the polycrystalline silicon film in the contact portion has a great influence on the conventional process design value.
改善策としては、能動素子部の多結晶シリコン膜を薄く
し、コンタクト部の多結晶シリコン膜を厚くする方法が
考えられるが、少なくともホトエツチ工程を１工程多く
行なう必要があり、コストアツプになり効果が少ない。As a remedy, a method of thinning the polycrystalline silicon film of the active element portion and thickening the polycrystalline silicon film of the contact portion can be considered, but at least one photoetching step needs to be performed one more step, which results in cost up. Few.
本発明は、この様な従来の欠点を除去したものであり、
その目的とするところは、薄い能動素子部の多結晶シリ
コン膜と配線材料とのコンタクトが充分取れる構造の薄
膜トランジスタを提供することである。The present invention eliminates such conventional drawbacks,
An object of the invention is to provide a thin film transistor having a structure in which a contact between the polycrystalline silicon film of the thin active element portion and the wiring material can be sufficiently made.
以下第２図（ａ）（ｂ）を用いて本発明の実施例を説明
する。An embodiment of the present invention will be described below with reference to FIGS.
カラス基板11上に多結晶シリコン膜の島12を形成したの
ち、表面を酸化したのち、ゲート電極となる多結晶シリ
コン膜14を形成する。次にイオン打込み法により、ソー
ス・ドレイン拡散層15を形成し、層間絶縁膜16を形成し
たのちに、コンタクトホールを開口する。引続き全面に
第１層目となる多結晶シリコン膜18を形成するととも
に、連続して第２層目となるAlを全面に形成したものを
第２図（ａ）に示す。After forming islands 12 of a polycrystalline silicon film on a glass substrate 11, the surface is oxidized and then a polycrystalline silicon film 14 to be a gate electrode is formed. Next, a source / drain diffusion layer 15 is formed by an ion implantation method, an interlayer insulating film 16 is formed, and then a contact hole is opened. FIG. 2A shows that the first-layer polycrystalline silicon film 18 is continuously formed on the entire surface, and the second-layer Al is continuously formed on the entire surface.
次にホトリソグラフイー技術により従来方法と同様にAl
の配線17を形成すると同時に、Alをマスキング材にし
て、第１層目となる多結晶シリコン膜をエツチング除去
する。Next, using photolithography technology, Al
At the same time that the wiring 17 is formed, the first layer of polycrystalline silicon film is removed by etching using Al as a masking material.
この様に、第２層目となるAl配線の下に多結晶シリコン
膜を第１層目として形成することによりコンタクト部の
多結晶シリコン膜の厚みを厚くする事と同等の効果があ
る。In this way, the same effect as increasing the thickness of the polycrystalline silicon film in the contact portion by forming the polycrystalline silicon film as the first layer under the second-layer Al wiring is obtained.
又、この場合にはAl配線のパターニングが完了後、Al配
線をマスキング材に第１層目の多結晶シリコン膜をエツ
チング除去するので、新たにホトマスクを用意する必要
がなく、コストアツプにはならない。Also, in this case, after the patterning of the Al wiring is completed, the first-layer polycrystalline silicon film is removed by etching using the Al wiring as a masking material, so that it is not necessary to prepare a new photomask and the cost does not increase.
さらに、第１層目の多結晶シリコン膜は通常不純物をド
ーピングしてあるので、能動素子部とのコンタクト抵抗
は、通常の約10分の１程度に下がる。これは通常能動素
子部へはイオン打込み法で不純物を注入するのであまり
濃度が高くできない為である。Further, since the first-layer polycrystalline silicon film is usually doped with impurities, the contact resistance with the active element portion is reduced to about one-tenth of the usual value. This is because the impurity is usually injected into the active element portion by the ion implantation method, so that the concentration cannot be increased so much.
これに対して、本発明によれば、コンタクト部の多結晶
シリコン膜は、不純物濃度が高く厚みも充分厚いので、
能動素子部とのコンタクトはなんら問題にならない。On the other hand, according to the present invention, since the polycrystalline silicon film of the contact portion has a high impurity concentration and a sufficiently thick thickness,
Contact with the active element does not pose any problem.
以上のような構成とすることにより以下の様な効果が得
られる。With the above configuration, the following effects can be obtained.
薄膜トランジスタにおいては、そのソース・チャネル・
ドレイン領域を形成する能動素子部の膜厚を薄くするこ
とによりトランジスタ特性が向上することが知られてい
る。しかしながら、能動素子部の膜厚が一定の薄膜トラ
ンジスタにおいては、能動素子部の膜厚を薄くしていく
とソース電極またはドレイン電極を形成するために絶縁
膜を開口する際、絶縁膜のみならず能動素子部である半
導体膜迄もエッチングしてしまう、いわゆるコンタクト
ホール抜けが発生し接触不良を起こしてしまう。In a thin film transistor, its source channel
It is known that the transistor characteristics are improved by reducing the film thickness of the active element portion forming the drain region. However, in a thin film transistor in which the film thickness of the active element part is constant, when the film thickness of the active element part is reduced, when the insulating film is opened to form the source electrode or the drain electrode, not only the insulating film but also the active film is opened. The so-called contact hole omission occurs, which also etches the semiconductor film that is the element portion, resulting in poor contact.
そこで、本発明はソース・ドレイン電極を２層構造と
し、下側配線層を能動素子部と同一の半導体膜とするこ
とにより、コンタクトホール抜けを能動素子部と同一材
料の下層配線で埋めることにより、電極部とソース・ド
レイン領域との接触不良を無くすものである。そしてそ
の結果、コンタクトホール抜けを考慮することなくトラ
ンジスタの特性優先で能動素子部の膜厚を決める事が可
能となり、結果的に高性能の薄膜トランジスタを歩留り
よく提供する事ができる。Therefore, according to the present invention, the source / drain electrodes have a two-layer structure and the lower wiring layer is formed of the same semiconductor film as that of the active element portion, so that the contact hole omission is filled with the lower layer wiring of the same material as the active element portion. The purpose is to eliminate contact failure between the electrode portion and the source / drain region. As a result, the film thickness of the active element portion can be determined by giving priority to the characteristics of the transistor without considering contact hole omission, and as a result, a high-performance thin film transistor can be provided with high yield.
それから、２層構造にすることにより、断線を低減する
ことができると共に、上層配線をマスクとして下層配線
をエッチング除去するため、下層配線を形成するための
マスクが不要となり、１層構造と比べてもほとんどコス
トアップなく２層の電極及び配線構造を達成することが
できる。Then, by using the two-layer structure, disconnection can be reduced, and since the lower-layer wiring is removed by etching using the upper-layer wiring as a mask, a mask for forming the lower-layer wiring becomes unnecessary, which is more than that of the single-layer structure. However, a two-layer electrode and wiring structure can be achieved with almost no increase in cost.
第１図（ａ）（ｂ）は従来の薄膜トランジスタの断面図
である。 第２図（ａ）（ｂ）は本発明による実施例を示す断面図
である。 図中1,11はガラス基板、2,12はトランジスタとなる多結
晶シリコン膜の島、3,13はゲート酸化膜、4,14はゲート
電極、5,15はソースあるいはドレイン、6,16は層間絶縁
膜、7,17はAl配線、18は第１層目となる多結晶シリコン
膜である。1A and 1B are cross-sectional views of a conventional thin film transistor. 2 (a) and 2 (b) are sectional views showing an embodiment according to the present invention. In the figure, 1 and 11 are glass substrates, 2 and 12 are islands of a polycrystalline silicon film which becomes a transistor, 3 and 13 are gate oxide films, 4 and 14 are gate electrodes, 5 and 15 are source or drain, and 6 and 16 are An interlayer insulating film, 7 and 17 are Al wirings, and 18 is a first layer polycrystalline silicon film.
Claims (1)
成する第１の工程と、 該薄膜半導体層を覆うゲート絶縁層を形成する第２の工
程と、 該ゲート絶縁層上にゲート電極を形成する第３の工程
と、 該ゲート電極をマスクとして該半導体層に不純物を注入
しソース、ドレイン領域を形成する第４の工程と、 薄膜トランジスタ上に層間絶縁膜を形成する第５の工程
と、 該ソース領域上及び該ドレイン領域上の該層間絶縁膜に
コンタクトホールを開口する第６の工程と、 該薄膜半導体層と同一の材料で第１層目の配線となる半
導体層を堆積する第７の工程と、 該半導体層上に第２層目の配線となる導電膜を堆積する
第８の工程と、 該第２層目の配線をパターニングして上層配線を形成す
る第９の工程と、 該上層配線をマスクとして該第１層目の配線をパターニ
ングして下層配線を形成する第10の工程とを有すること
を特徴とする薄膜トランジスタの製造方法。1. A first step of forming a thin film semiconductor layer having a constant thickness on an insulating material, a second step of forming a gate insulating layer covering the thin film semiconductor layer, and a gate on the gate insulating layer. Third step of forming electrodes, fourth step of implanting impurities into the semiconductor layer to form source and drain regions using the gate electrode as a mask, and fifth step of forming an interlayer insulating film on the thin film transistor And a sixth step of opening a contact hole in the interlayer insulating film on the source region and the drain region, and depositing a semiconductor layer to be a first wiring layer with the same material as the thin film semiconductor layer. A seventh step, an eighth step of depositing a conductive film to be a second-layer wiring on the semiconductor layer, and a ninth step of patterning the second-layer wiring to form an upper-layer wiring And the first layer using the upper layer wiring as a mask A method of manufacturing the thin film transistor and having a tenth step of forming a lower wiring by patterning the wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59157014A JPH0783126B2 (en) | 1984-07-27 | 1984-07-27 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59157014A JPH0783126B2 (en) | 1984-07-27 | 1984-07-27 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6135564A JPS6135564A (en) | 1986-02-20 |
| JPH0783126B2 true JPH0783126B2 (en) | 1995-09-06 |
Family
ID=15640292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59157014A Expired - Lifetime JPH0783126B2 (en) | 1984-07-27 | 1984-07-27 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783126B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58127321A (en) * | 1982-01-23 | 1983-07-29 | Canon Inc | Preparation of semiconductor device |
| JPS5940582A (en) * | 1982-08-30 | 1984-03-06 | Seiko Epson Corp | Semiconductor device |
-
1984
- 1984-07-27 JP JP59157014A patent/JPH0783126B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6135564A (en) | 1986-02-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |