JPH06252169A - Semiconductor device and its manufacturing thereof - Google Patents

Abstract

PURPOSE:To make it possible to form a channel region, a source region, and a drain region with self-alignment without using a host mask by depositing a semiconductor layer on a gate electrode and on a main surface through an insulation film and etching back the semiconductor layer until the gate insulation film is exposed. CONSTITUTION:In a semiconductor device of a lower section gate structure where a gate electrode 13 is formed on the insulating main surface 12, the gate electrode 13 is formed on the insulating main surface 12 of a substrate 11, and the gate electrode 13 is covered with a gate insulation film 14 to form first semiconductor layer 15 on the upper gate electrode 13 and on the upper section of the main surface 12 through the insulation film 14. Further, the first semiconductor layer 15 on the gate insulation film 14 positioned on the upper section of the gate electrode 13 is removed to form a source region 15a and a drain 15b are formed on both ends of the gate electrode 13. Furthermore, a second semiconductor layer 16 to serve as an opposite conductivity type channel region with respect to the first semiconductor layer 15 is formed on the insulation film 14 on the upper section of the gate electrode 14 and on the first semiconductor layer 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a TFT (thin film transistor: Thi) having a lower gate structure.
n Film Transistor) The present invention relates to a technique effectively applied to a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a TFT semiconductor device having a lower gate structure is composed of an insulating film of silicon oxide or the like by a CVD method or the like and a semiconductor layer of polycrystalline silicon or the like, and by selective ion implantation using a photomask, A method of forming a channel region, a source region, and a drain region in the same semiconductor layer has been performed.

FIG. 1 is a cross-sectional view of essential parts showing an example of a conventional TFT semiconductor device having a lower gate structure. Taking the case of a P-type TFT semiconductor device as an example, the formation of the TFT semiconductor device by the above-mentioned method is such that a conductive material such as polycrystalline silicon is formed on the insulating main surface where the insulating film 2 is formed on the surface of the silicon substrate 1. Layer is deposited, a gate electrode 3 is formed by selectively etching using a photomask, and an insulating gate insulating film 4 such as silicon oxide is formed to cover the gate electrode 3 by a CVD method or the like. A semiconductor layer 5 doped with an N-type impurity such as phosphorus is formed on the gate electrode 3 and the insulating film 2 on the main surface.
Is deposited, and then a P-type impurity such as boron is selectively implanted into the semiconductor layer 5 in the region other than the region above the gate electrode 3 to be the channel region 5a using a photomask,
A P-type layer region serving as the source region 5b and the drain region 5c is formed.

[0004]

SUMMARY OF THE INVENTION In the above prior art,
Since the N-type channel region 5a and the P-type source regions and drain regions 5b and 5c are formed in the same semiconductor layer 5 by ion implantation using a photomask, a misalignment of the photomask causes a broken line in FIG. As shown, the positions of the channel region 5a, the source region 5b, and the drain region 5c may be displaced from the gate electrode 3. The semiconductor device in which the position of each region is displaced in this way has a problem that the characteristics are deteriorated even when the displacement is small, and becomes defective when the displacement is large. Further, since the cost required for manufacturing the photomask is high, there is a problem that the production cost of the semiconductor device becomes high.

An object of the present invention is to use a photomask without using
It is an object of the present invention to provide a technique capable of forming a channel region, a source region and a drain region of a semiconductor device by self-alignment.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, a gate electrode covered with an insulating film is formed on an insulating main surface, and a first semiconductor layer is deposited on the insulating film on the gate electrode and the insulating film on the other main surface. After that, the semiconductor layer on the gate electrode is etched back until the gate insulating film is exposed to form a source region and a drain region on both sides of the gate electrode. Next, a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer is deposited on the first semiconductor layer and the insulating film on the gate electrode to form a channel region above the gate electrode. is there.

[0009]

According to the above-mentioned means, in the step of forming the channel region, the source region and the drain region, the ion implantation using the photomask is not performed, but the region located above the gate electrode from the P-type semiconductor layer is removed. Removed,
The remaining P-type regions on both sides of the gate electrode are used as a source region and a drain region, and an N-type semiconductor layer serving as a channel region is newly formed on the gate electrode, the source region, and the drain region to form each region. TFT without self-alignment in photolithography process
Forming a semiconductor device is accomplished.

Therefore, by forming the source region and the drain region by self-alignment, an incomplete TFT is not formed due to misalignment of the photomask, and a high-performance TFT semiconductor device with uniform characteristics is produced. To do. Further, the production cost can be reduced by not using an expensive photomask for forming the source region and the drain region.

The structure of the present invention will be described below together with embodiments.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals and their repeated description will be omitted.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the sectional views of the essential parts shown in FIGS.

In FIG. 2, reference numeral 11 denotes a silicon substrate, which is insulated by a silicon oxide insulating film 12 and constitutes an insulating main surface. Polycrystalline silicon is deposited on the insulating film 12 and selectively etched using a photomask to form a gate electrode 13. Next, a gate insulating film 14 of silicon oxide is formed by plasma CVD so as to cover the gate electrode 13. This state is shown in FIG.

After the gate insulating film 14 is formed, the gate electrode 1
A first semiconductor layer 15 made of polycrystalline silicon doped with P-type impurities is deposited on the insulating film 14 on 3 and the insulating film 12 on the other main surface. This state is shown in FIG. Next, the semiconductor layer 15 located on the gate electrode 13 is etched back until the gate insulating film 14 is exposed, and the remaining first semiconductor layer 15 causes the source region 15a and the drain region to be formed on both sides of the gate electrode 13. 15b is formed. In order to leave the first semiconductor layer 15 in the regions to be the source region 15a and the drain region 15b, the etch back is performed by anisotropic etching.
It is desirable to deposit 5 thickly to make the surface flat. This state is shown in FIG.

Next, a second semiconductor layer 16 made of polycrystalline silicon doped with N-type impurities is deposited on the first semiconductor layer 15 and the gate insulating film 14. A region of the second semiconductor layer 16 located above the gate electrode 13 forms a channel region 16a. This state is shown in FIG.

The connection between the source region 15a and the drain region 15b and the wiring layer (not shown) in the TFT semiconductor device of this embodiment is performed by using the insulating layer 12 of the silicon substrate 11 located below the source region 15a and the drain region 15b. It may be partially removed and provided in the lower silicon substrate 11. Further, a P-type impurity is ion-implanted into the N-type region of the second semiconductor layer 16 deposited on the upper part to form a P-type region that is electrically connected to the first semiconductor layer 15, and is connected to the P-type region. May be. When the second semiconductor layer 16 is partially converted to P type, the implantation region is restricted by the diameter of the ion beam, and the implantation precision is higher than when the source region 5b and the drain region 5c are formed. Therefore, it is possible to perform ion implantation by controlling the ion beam without using a photomask.

In this embodiment, the case of forming a P-type TFT semiconductor device has been described, but as the first semiconductor layer 15, N-type is used.
By depositing type polycrystalline silicon and depositing P type polycrystalline silicon as the second semiconductor layer 16, an N type TFT semiconductor device can be similarly formed. Further, in this embodiment, the N-type and P-type semiconductor layers 15 and 16 are formed by doping, but the semiconductor layer 1
An ion implantation method may be used to form the layers 5 and 16.

Although it is possible to form the silicon oxide of the gate insulating film 14 by a thermal oxidation method, it is preferable to form it by the CVD method because the surface of the insulating film 14 becomes rough. Further, in order to make the surface flatter when etching back the first semiconductor layer 15, a resin (not shown) or the like having the same etching rate is applied to the surface of the first semiconductor layer 15. It is also possible to adopt the spin-on method.

In this embodiment, the silicon substrate 11 covered with the insulating film 12 is used as the insulating base, but other insulating materials such as glass and ceramic may be used. Also,
Although silicon oxide is used as the insulating film 12, other insulating materials such as calcium fluoride, aluminum oxide, and zinc sulfide may be used. Although polycrystalline silicon is used for the gate electrode 13, other conductive materials such as aluminum and tungsten may be used.

In this embodiment, the structure of the TFT semiconductor device alone is shown. However, the TFT semiconductor device may be a switching element of a liquid crystal display or an SRAM (Static).
It is generally used as a load element of a cRandom Access Memory) and is configured as a semiconductor integrated circuit in which a large number of elements of the same kind and different kinds are combined, and the present invention is also applied to such a case. .

As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0023]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, the source region and the drain region of the TFT semiconductor device having the lower gate structure can be formed by self-alignment, and an expensive photomask is not required. This has the effect of reducing production costs.

(2) According to the present invention, since the source region and the drain region are formed by self-alignment and the characteristic change caused by the misalignment of the photomask is small, it is possible to produce a TFT semiconductor device having uniform characteristics and high performance. The effect is that it can be done.

(3) According to the present invention, since the source region and the drain region are formed by self-alignment and no defective product is generated due to misalignment of the photomask, the product yield is improved, and the effect of the above (1). In addition to this, there is an effect that the production cost of the TFT semiconductor device can be further reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a conventional TFT semiconductor device,

FIG. 2 is a cross-sectional view of an essential part showing a manufacturing process of a TFT semiconductor device which is an embodiment of the present invention,

FIG. 3 is a cross-sectional view of an essential part showing a manufacturing process of a TFT semiconductor device which is an embodiment of the present invention,

FIG. 4 is a cross-sectional view of an essential part showing a manufacturing process of a TFT semiconductor device which is an embodiment of the present invention,

FIG. 5 is a cross-sectional view of an essential part showing a manufacturing process of a TFT semiconductor device which is an embodiment of the present invention,

FIG. 6 is a cross-sectional view of an essential part showing a manufacturing process of a TFT semiconductor device which is an embodiment of the present invention.

[Explanation of symbols]

1, 11 ... Semiconductor substrate, 2, 12 ... Insulating film, 3, 13 ...
Gate electrodes, 4, 14 ... Gate insulating film, 5 ... Semiconductor layer,
5a, 16a ... Channel region, 5b, 15a ... Source region, 5c, 15b ... Drain region, 15 ... First semiconductor layer, 16 ... Second semiconductor layer.

Front Page Continuation (72) Inventor Shigeya Toyokawa 5-20-1, Josui Honcho, Kodaira-shi, Tokyo Hiratsuru SLS Engineering Co., Ltd. (72) Inventor Nozomu Matsuda, Kodaira, Tokyo 5-20-1 Mizumotocho Hiritsu Super L.S.I. Engineering Co., Ltd. (72) Inventor Seiichi Ariga 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hiritsu Super L.S.I. Within Engineering Co., Ltd. (72) Inventor Chiemi Mori 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Taiji Iwanaga, Kodaira-shi, Tokyo 5-20-1 Honmachi Hiritsu Cho LLS Engineering Co., Ltd.

Claims (2)

[Claims] 1. A semiconductor device having a lower gate structure in which a gate electrode is formed on an insulating main surface, the gate electrode is formed on the insulating main surface of a substrate, and the gate electrode is a gate insulating film. By forming a first semiconductor layer on the gate electrode upper part and the main surface upper part through an insulating film, and removing the first semiconductor layer on the gate insulating film located on the gate electrode upper part. A source region and a drain region are formed on both sides of the gate electrode, and a second semiconductor layer serving as a channel region having a conductivity type opposite to that of the first semiconductor layer is formed on the insulating film above the gate electrode and the first semiconductor layer. A semiconductor device, which is formed on a layer. 2. A method of manufacturing a semiconductor device having a lower gate structure, which comprises forming a gate electrode on an insulating main surface,
(1) A step of forming a gate electrode on the insulating main surface,
(2) a step of forming a gate insulating film covering the gate electrode,
(3) First on the upper part of the gate electrode and the upper part of the main surface via an insulating film
And (4) removing the first semiconductor layer on the gate insulating film located above the gate electrode and forming source and drain regions on both sides of the gate electrode. (5) A step of forming a second semiconductor layer, which serves as a channel having a conductivity type opposite to that of the first semiconductor layer, on the gate insulating film and the first semiconductor layer. Device manufacturing method.