JPH06196553A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which open circuit or defective patterning is prevented in the following processes while ensuring sufficient isolation even in case of fine isolation interval by making smooth the edge of a field plate electrode. CONSTITUTION:The semiconductor device having isolation structure comprises a semiconductor substrate 1, a thin oxide film 2 formed thereon, and a field plate electrode 3 formed on the oxide film while having a tapered edge and fixed at a constant potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an element isolation structure suitable for high integration.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices (especially silicon LS
The isolation between the active elements of I) is performed by a selective oxidation method or LOCOS (Local Oxidation of).
The method also called Silicon) has been widely used. FIG. 5 is a cross-sectional view of manufacturing steps of such a conventional semiconductor device.

First, as shown in FIG. 5 (a), a thermal oxide film 102 and a silicon nitride film 103 are sequentially deposited on a silicon single crystal substrate 101, and a photolithography technique is used.
After removing the silicon nitride film and the thermal oxide film at the portion where the isolation oxide film is to be formed by etching, channel stop ion implantation is performed to form the diffusion layer 104 if necessary to improve the isolation capability.

Then, as shown in FIG.
Wet oxidation at about 0 ° C. is performed to form the field oxide film 10.
5 is formed. At this time, the silicon nitride film 103 blocks oxidation species and has oxidation resistance.
Silicon under 3 is not oxidized, and a thick field oxide film 105 is formed in the other portion. After that, FIG.
As shown in (c), when the silicon nitride film 103 and the thermal oxide film 102 are removed, the element formation region 106 and the element isolation region 107 are formed separately. 105a is a bird's beak.

[0005]

However, in the above-described method for manufacturing a semiconductor device, when the pattern pitch becomes small, there is a taper (so-called bird's beak) 105a at the edge of the field oxide film, so that the element formation region is very small. Finally, there was a fatal drawback that it could not be formed at all. In addition, the channel stop ion implantation diffusion layer 104 oozes into the element formation region,
There are also drawbacks such as narrowing the effective channel width of the MOS transistor formed in this portion and varying the threshold voltage.

A separation method which has improved these drawbacks is disclosed in, for example, JP-A-3-205868. FIG. 6 is a sectional view of such a conventional semiconductor device. As shown in this figure, the isolation region gate oxide film 2 is formed on the silicon substrate 201.
02, and the isolation gate electrode 203 is formed thereon. A potential is applied to the separation gate electrode 203 so that the separation MOS is turned off. In the separated active region, the gate oxide film 204, the gate electrode 205,
A MOS transistor including the diffusion layer 206 is formed.

However, in the structure of this semiconductor device, a step due to the separation gate electrode 203 is generated, and in a subsequent step, for example, gate electrode patterning of an active transistor, the step causes a photolithographic patterning defect and an etching residue, and the yield However, there was a drawback that In order to eliminate the above-mentioned problems, the present invention smoothes the edge shape of a field plate electrode in a semiconductor device having an element isolation structure, thereby preventing step disconnection and patterning failure in a subsequent process. Moreover, it is an object of the present invention to provide a semiconductor device having a sufficient separation ability even when the separation distance is minute.

[0008]

To achieve the above object, the present invention provides a semiconductor device having an element isolation structure, a semiconductor substrate, a thin insulating film formed on the semiconductor substrate, and the insulating film. A field plate electrode which is formed on the upper surface and has a tapered edge and which is fixed at a constant potential is provided.

Further, in a CMOS type semiconductor device having an element isolation structure, a thin insulating film formed on a P type semiconductor layer and a tapered edge formed on this insulating film and fixed at a first constant potential. Formed first field plate electrode, a thin insulating film formed on the N-type semiconductor layer, and a second constant potential higher than the first constant potential and having a tapered edge formed on the thin insulating film The second field plate electrode fixed to the above is provided.

[0010]

According to the present invention, as described above, in a semiconductor device having an element isolation structure, a field plate electrode having a tapered edge is provided on a semiconductor substrate through a relatively thin oxide film, and this is fixed. Device isolation is realized by fixing the potential.

Therefore, since the edge of the field plate electrode is smooth, step disconnection or patterning failure does not occur in the subsequent process, and sufficient separation ability can be obtained even with a minute separation interval.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings. 1 is a plan view of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG. 3 is a sectional view taken along line BB of FIG. In this embodiment, an example of forming an N channel MOS transistor on a P type silicon substrate is shown.

In the figure, 1 is a P-type silicon single crystal substrate, and 2 is
The oxide film 3 formed on the isolation region 52 is the oxide film 2
It is a field plate electrode formed above. Active element
N-channel MOS is provided in the child area (active area) 51.
A transistor is formed. MOS transistor
Gate oxide film 4, gate electrode 6, source / drain N ⁺
It is composed of the diffusion layer 7. Field plate electrode
3 and the gate electrode 6 are separated by an insulating film (oxide film) 5
There is. An interlayer insulating film 8 is formed on the transistor
And contact holes 9A, 9B, 9C where necessary
Has been opened.

A conductor is embedded in the contact hole and is connected to the metal wirings 10A, 10B and 10C. A passivation film for protection (not shown) is formed on the uppermost layer. A constant voltage is applied to the field plate electrode 3, but this voltage is set sufficiently lower than the threshold voltage of the MOS structure in the isolation region portion. Desirably, it is set to the lowest voltage used in the circuit. By configuring in this way,
The isolation capability is determined by the punch-through characteristics of the MOS structure in the isolation region.

Usually, this separation ability is superior to that of the conventional LOCOS separation, and it has a sufficient separation ability even with a fine pattern. Next, a method of manufacturing this semiconductor device will be described with reference to FIG. First, as shown in FIG. 4A, a thermal oxide film 2 having a film thickness of 10 to 20 nm is formed on a P-type silicon single crystal substrate 1 by thermal oxidation. Polycrystalline silicon 21 having a film thickness of 100 to 2 is formed thereon by the CVD method.
It is deposited to a thickness of 00 nm, and phosphorus is doped at a high concentration as an impurity. For this doping, a method may be used in which a gas containing impurities is mixed into the source gas at the time of depositing the polycrystalline silicon and doping is performed at the same time as the deposition. After depositing an oxide film 22 having a film thickness of about 20 nm and a nitride film 23 having a film thickness of about 100 nm on the polycrystalline silicon 21 by the CVD method, the nitride film 23 and the oxide film 22 are selectively removed by a photolithography technique.

Subsequently, as shown in FIG. 4B, the exposed polycrystalline silicon 21 is selectively thermally oxidized using the nitride film 23 as an oxidation resistant mask. The conditions for oxidation include
Wet or dry oxidation at 800 to 1000 ° C. is suitable. When the exposed polycrystalline silicon 21 is completely made into an oxide film by the selective oxidation, the field plate electrode 3 of the polycrystalline silicon 21 having a tapered edge at the bottom of the nitride film 23 remains.

Further, as shown in FIG. 4C, the nitride film 2
3 is etched with a hot phosphoric acid aqueous solution, and the unnecessary oxide film 2 is etched with a dilute hydrofluoric acid aqueous solution to expose the substrate in the active region. The separation area and the active area are separated by the steps up to this point. Next, as shown in FIG. 4D, the gate oxide film 4 of the MOS transistor is formed by thermal oxidation. At this time, the oxide film 5 is also formed on the field plate electrode 3 at the same time, but the oxide film 5 is formed thicker on the polycrystalline silicon than on the single crystal. The gate electrode 6 of the transistor is formed thereon. After that, elements such as MOS transistors and wirings are formed using a known technique.

Next, another embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a plan view of a semiconductor device showing another embodiment of the present invention, and FIG. 8 is a sectional view taken along line CC of FIG. This embodiment is an example applied to a CMOS. As shown in the figure, an N channel MOS transistor is formed on a P-type silicon single crystal substrate 61, and a P channel MOS transistor is formed on an N well 62 formed in the substrate. 63 is a thin oxide film formed on the isolation region, 64A and 64B are field plate electrodes formed thereon, and when the N channel MOS transistors are separated from each other, the field plate electrode 64A has a low potential V.
_The field plate electrode 64B is connected to the _SS line and the V _DD line having a high potential when the P channel MOS transistors are separated from each other.

An N ⁺ diffusion layer 67A is provided around the N well to fix the potential of the well. 65 is a gate oxide film of a MOS transistor, 66 is a gate electrode,
67 is the source / drain N ⁺ of the N-channel transistor
The diffusion layer 68 is a source / drain P ⁺ diffusion layer of the P-channel transistor. Further, 67A is an N ⁺ diffusion layer for fixing N well potential, and 68A is a P ⁺ diffusion layer for fixing P substrate potential.

An interlayer insulating film 69 is formed on the upper part of the transistor, and contact holes 70 are formed at necessary places. A conductor is embedded in the contact hole 70, and metal wirings 71A, 71B,
71C and 71D are formed. A protective passivation film (not shown) is formed on the uppermost layer. With such a structure, in the N channel region, the field plate electrode 6 of the N channel MOS in the isolation portion is formed.
Connect the 4A to low V _SS line of potential, low potential V _SS
In addition, in the P channel region, the field plate electrode 64B of the P channel MOS of the isolation portion is set to V with high potential.
_Since it is connected to the _DD line so as to have a high potential V _DD , the MOS of each separation portion can be completely cut off, and good separation characteristics can be obtained.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0022]

As described above in detail, according to the present invention, a MOS transistor having a field plate electrode having a tapered edge in an element isolation region is formed,
Since the potential for cutting off is applied to the field plate electrode, the following effects can be obtained.

(1) Since the edge of the field plate electrode is smooth, step disconnection or patterning failure in the subsequent process does not occur. (2) Sufficient separation ability can be obtained even with a minute separation interval. (3) There is no seepage from the channel stop layer as in the LOCOS method, and there is no adverse effect on the active transistor.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG.

FIG. 4 is a sectional view of a semiconductor device manufacturing process showing the embodiment of the present invention.

FIG. 5 is a cross-sectional view of manufacturing steps of a conventional semiconductor device.

FIG. 6 is a cross-sectional view of another conventional semiconductor device.

FIG. 7 is a plan view of a semiconductor device showing another embodiment of the present invention.

8 is a sectional view taken along line CC of FIG.

[Explanation of symbols]

1,61 P-type silicon single crystal substrate 2,5,22,63 oxide film 3,64A, 64B field plate electrode 4,65 gate oxide film 6,66 gate electrode 7 source / drain N ⁺ diffusion layer 8,69 interlayer insulation Films 9A, 9B, 9C, 70 Contact holes 10A, 10B, 10C, 71A, 71B, 71C, 7
1D metal wiring 21 polycrystalline silicon 23 nitride film 51 active element region (active region) 52 isolation region 62 N well 67 source / drain N of N-channel transistor
⁺ Diffusion layer 67A N well potential fixing N ⁺ Diffusion layer 68 P-channel transistor source / drain P
⁺ Diffusion layer 68A P Substrate potential fixing P ⁺ Diffusion layer

Claims (3)

[Claims] 1. A semiconductor device having an element isolation structure comprising: (a) a semiconductor substrate; (b) a thin insulating film formed on the semiconductor substrate; and (c) a tapered edge formed on the insulating film. A semiconductor device having a field plate electrode having a fixed potential. 2. A CMOS type semiconductor device having an element isolation structure, comprising: (a) a thin insulating film formed on a P type semiconductor layer; (b) a thin insulating film formed on the insulating film, having a tapered edge, and No. 1, a first field plate electrode fixed at a constant potential, (c) a thin insulating film formed on the N-type semiconductor layer, (d) formed on the insulating film, having a tapered edge, and A semiconductor device comprising a second field plate electrode fixed to a second constant potential higher than the first constant potential. 3. The semiconductor device according to claim 2, wherein the first constant potential is a ground potential V _SS and the second constant potential is a power supply potential V _DD .