CN102253325A - Method for analyzing chip failure - Google Patents
Method for analyzing chip failure Download PDFInfo
- Publication number
- CN102253325A CN102253325A CN2010101814776A CN201010181477A CN102253325A CN 102253325 A CN102253325 A CN 102253325A CN 2010101814776 A CN2010101814776 A CN 2010101814776A CN 201010181477 A CN201010181477 A CN 201010181477A CN 102253325 A CN102253325 A CN 102253325A
- Authority
- CN
- China
- Prior art keywords
- chip
- analytical approach
- grid
- failure
- failure analytical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000004458 analytical method Methods 0.000 claims abstract description 22
- 230000007547 defect Effects 0.000 claims abstract description 11
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- 238000000227 grinding Methods 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 238000013459 approach Methods 0.000 claims description 27
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 12
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 9
- 239000012670 alkaline solution Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 7
- 239000007767 bonding agent Substances 0.000 claims description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000523 sample Substances 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005299 abrasion Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
Images
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Sampling And Sample Adjustment (AREA)
Abstract
The invention provides a method for analyzing chip failure, which is used for detecting defect characteristics of a chip grid and comprises the following steps: removing most of a substrate and an active region of a chip to be subjected to failure analysis through mechanical grinding; removing the remained substrate and active region of the chip through wet etching; removing most of a gate oxide layer of the chip through dry etching, wherein the remained gate oxide layer is used for protecting a first polysilicon layer of the grid; and detecting whether the defect characteristics exist on the first polysilicon layer or not. By utilizing the method provided by the invention, the chip can be accurately stripped to the bottom of the first polysilicon layer of the grid, the accurate size parameters of the bottom of the first polysilicon layer can be measured, the working efficiency can be greatly improved, and the time can be saved.
Description
Technical field
The present invention relates to the semiconductor failure analysis field, particularly a kind of chip failure analytical approach.
Background technology
In the modern integrated circuits manufacturing process, chip manufacture need experience process procedures such as a series of chemistry, optics, metallurgy, hot-working.Per pass technology all may be introduced various defectives.Meanwhile because constantly the dwindling of characteristic dimension, all kinds of processing facility costs also sharply rise, so the loss cost that device defects causes is very high.Under this condition, by validation test, analyze failure cause, reduce device defects and just become indispensable link in the integrated circuit manufacturing.By failure analysis work, can help the integrated circuit (IC) design personnel to find not matching of defective in the design, technological parameter, also help integrated circuit application personnel to find to use problems such as design or misoperation simultaneously.
The failure analysis common method has a lot, roughly is divided into two kinds of hard method (Hard Method) and soft methods (SoftMethod).Hard method comprises that mainly hardware devices such as using photoelectric microscope checks and definite failure cause, thereby improves technological process.At present, these are used to diagnose, the system and the advanced analytical equipment instrument of failure analysis comprise electron beam probe (E-beam probe) diagnostic system, plasma beam mending system (FIB-Focused Ion Beam), thermal infrared imager, scanning electron microscope (SEM-Scanning ElectronMicroscopy), Laser Scanning Confocal Microscope, analyzing parameters of semiconductor instrument etc.The failure analysis personnel just can analyze each top layer of chip and longitudinal profile by using these instruments, and accurately the positioning chip defective provides complete failure analysis report.
In the present prior art, the chip failure analytical approach adopts the method for cmp that chip is successively peeled off usually and then adopts above-mentioned hard method to check and whether definite chip lost efficacy.With non-volatile Flash memory chip is example, be illustrated in figure 1 as the side structure cut-open view of Flash memory chip, this chip comprises substrate 1, has active area 2 (source-drain area) in the substrate 1, be formed with grid oxide layer 3, control grid 4 and metal level 5 on the substrate 1 successively, wherein, grid oxide layer 3 is the stepped construction of monox, silicon nitride, monox, be the ONO structure, silicon nitride is used for stored charge; Grid 4 is made of first polysilicon layer 41 and second polysilicon layer 42; Metal level 5 can be provided with one or more layers according to cabling requirement, as signal, has drawn three layers among the figure.Because the bottom live width of grid 4 is for the reading and writing of Flash storer and wipe the performance important influence, therefore, failure analysis at this Flash memory chip mainly passes through to measure grid 4 bottom sizes, the i.e. length and wide the carrying out of first polysilicon layer, 41 bottoms, after the bottom size that obtains first polysilicon layer 41, again by observing and relatively judging whether this grid exists the defect characteristic that causes chip failure.
Owing to also be coated with grid second polysilicon layer 42 and metal level 5 on first polysilicon layer 41, for the bottom that can directly observe grid first polysilicon layer 41 and then measure its characteristic dimension, in the prior art, usually successively stripping metal layer 5, grid second polysilicon layer 42, grid first polysilicon layer 41 adopt scanning electron microscope sem or perspective Electronic Speculum TEM to check the bottom length and width equidimension of grid first polysilicon layer 41 until the bottom of exposing first polysilicon layer 41 then from chip front side to adopt chemical mechanical milling method.But in fact, adopt the method to grind when peeling off grid first polysilicon layer 41 to be the bottom that is difficult to peel off accurately stop to the first polysilicon layer 41, operating personnel are ground to the grid oxide layer 3 or the active area 2 of chip through regular meeting.Even grind the zone that has finally rested on very close first polysilicon layer, 41 bottoms, because factors such as abrasion error or uneven thickness, the size of first polysilicon layer, 41 bottoms that finally record also is easy to generate error, so just be easy to deal with problems and cause misleading, and general about 10 first polysilicon layer, 41 bottom sizes of every observation just need 4 hours to the slip-stick artist.This shows that the method efficient that prior art adopts is very low, success ratio is very little, and the data that obtain are also inaccurate.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of chip failure analytical approach, and very difficult precisely grinding efficiently is stripped to the bottom of grid ground floor polysilicon to record the problem of its bottom accurate size parameter in the failure analysis of chip to solve.
For solving the problems of the technologies described above, the invention provides a kind of chip failure analytical approach, be used to detect the defect characteristic that causes chip failure, may further comprise the steps:
Remove the substrate of the chip that carries out failure analysis and the major part of active area by mechanical lapping;
Remove remaining substrate and the active area of chip by wet etching;
Remove the major part of the grid oxide layer of chip by dry etching, the part grid oxide layer of reservation is used to protect grid first polysilicon layer;
Detect described first polycrystal layer and whether have defect characteristic.
Optionally, the step of described chip failure analytical approach also comprises: the chip front side that will carry out failure analysis before carrying out mechanical lapping pastes on the plummer with bonding agent down.
Optionally, the described chip that carries out failure analysis can be a complete chip, also can be the part of the chip under the cutting.
Optionally, the material of described plummer is a glass.
Optionally, described mechanical lapping can automatically be ground and realizes by plummer and chip being put into automatic grinding device.
Optionally, the manual plummer of lifting of described mechanical lapping employing is pressed in sample the mechanical lapping that realizes on the muller chip.
Optionally, describedly remove the remaining substrate of chip and the step of active area comprises by wet etching: chip is together put into together with plummer in the weakly alkaline solution of the heating that has added isopropyl alcohol, and remaining substrate and active area removed fully on chip.
Optionally, the temperature of the weakly alkaline solution of described heating is 80-85 ℃.
Optionally, described weakly alkaline solution is that concentration is lower than 40% potassium hydroxide solution.
Optionally, described wet etching is removed the remaining substrate of chip and the step of active area also comprises: pull out after chip is put into hydrogen peroxide number minute together with plummer, use deionized water chip to be cleaned and make the chip drying.
Optionally, the temperature of described hydrogen peroxide is 50-90 ℃.
Optionally, adopt high vacuum scanning electron microscope or low vacuum scanning electron microscope to detect described first polycrystal layer and whether have defect characteristic.Preferred low vacuum scanning electron microscope.
Chip failure analytical approach provided by the invention can accurately be peeled off chip to the bottom of grid ground floor polysilicon, record the accurate dimension parameter of its bottom, and skilled operating personnel adopt method of the present invention to carry out the bottom size of all grid ground floor polysilicons can be just finished in failure analysis within 2 hours observation, improve work efficiency greatly, saved time cost.
Description of drawings
Fig. 1 is the side structure cut-open view of Flash memory chip;
Fig. 2 a-Fig. 2 d is a chip failure analytical approach step synoptic diagram of the present invention;
Fig. 3 is the process flow diagram of chip failure analytical approach of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Chip failure analytical approach of the present invention can be widely used in the failure analysis of memory chip and other semi-conductor chips; and can utilize multiple substitute mode to realize; be to be illustrated below by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes synoptic diagram to describe in detail, and when the embodiment of the invention was described in detail in detail, for convenience of explanation, synoptic diagram was disobeyed the local amplification of general ratio, should be with this as limitation of the invention.
Below be that example describes the inventive method in detail with the failure analysis of Flash memory chip.
Please at first consult Fig. 1, Figure 1 shows that the side structure cut-open view of Flash memory chip.As shown in Figure 1, the structure of chip comprises substrate 1 as describing in detail in background technology, have active area 2 (source-drain area) in the substrate 1, be formed with grid oxide layer 3, control grid 4 and metal level 5 on the substrate 1 successively, wherein grid 4 is made of first polysilicon layer 41 and second polysilicon layer 42.Because ground floor polysilicon 41 oxide-semiconductor control transistors of grid, operation such as affect the reading and writing of chip and wipe, the length and width size of its bottom has determined that the grid of active device are long, and can influence transistorized performance, thereby the length and width size of its bottom has become the important dimensional parameters of product.Therefore, at the grid progress row failure analysis of chip the time, need to measure the length and width dimensional parameters of ground floor polysilicon 41 bottoms of grid.Common metal level 5 in the prior art from chip front side, successively peel off the second layer polysilicon 42 of grid, the ground floor polysilicon 41 of grid by mechanical lapping, until the bottom of the ground floor polysilicon 41 that exposes grid and then measure its length and width size, chip failure analytical approach of the present invention is then from the back side substrate 1 of chip, method by mechanical lapping and etching phase combination can finally intactly reveal ground floor polysilicon 41 bottoms of grid, and then records its length and width dimensional data accurately.
Describe chip failure analytical approach of the present invention in detail below in conjunction with Fig. 2 a-Fig. 2 d and Fig. 3.Fig. 2 a-Fig. 2 d is a chip failure analytical approach step synoptic diagram of the present invention, and Fig. 3 is the process flow diagram of chip failure analytical approach of the present invention.Chip structure among Fig. 2 a-Fig. 2 d is identical with the chip structure of Fig. 1, and Yin Ben second layer polysilicon 2 of metal level 1 and grid in inventive method does not need to mention so it is not marked in the chip structure of Fig. 2 a-2d.
At first, shown in Fig. 2 a, the metal level of need being carried out the chip of failure analysis pastes on the plummer 9 with bonding agent 8 down.
The chip that adopts the inventive method to carry out failure analysis can be a complete chip, also can be the part of the chip under the cutting; Plummer 9 can be the material of glass or other quality; The adhesion of bonding agent 8 must be finished ensuing mechanical lapping and heat treatment process by supporting chip on plummer 9.
Secondly, shown in Fig. 2 a and Fig. 2 b, remove the substrate 1 of chip and the major part of active area 2 by mechanical lapping.
Begin the substrate 1 and the active area 2 of chip are carried out mechanical lapping from the back of chip, until the major part that peels off substrate 1 and active area 2, almost imperceptible chip or can stop to grind during printing opacity when chip when stroking the edge of plummer 9 with hand.Above-mentioned process of lapping can adopt to be put into the mode that automatic grinding device automatically grinds with plummer 9 and chip and realizes, also can adopt the manual plummer of lifting sample is pressed in the mode that realizes on the muller the mechanical lapping of chip realizes.
Once more, shown in Fig. 2 b and Fig. 2 c, remove remaining substrate 1 and the active area 2 of chip by wet etching.
The chip that will pass through mechanical lapping was together put into together with plummer 9 in the weakly alkaline solution of the heating that has added isopropyl alcohol several minutes, until shown in Fig. 2 c with chip on by mechanical lapping after remaining substrate 1 and active area 2 remove fully; The temperature of the weakly alkaline solution of described heating is 80-85 ℃; Be a kind of embodiment of the present invention, described weakly alkaline solution can be concentration and is lower than 40% potassium hydroxide solution.Chip together with plummer 9 put in hydrogen peroxide and pull out after several minutes, use deionized water chip to be cleaned and make the chip drying thereafter; The temperature of described hydrogen peroxide can be chosen between 50-90 ℃.
Once more, shown in Fig. 2 c and Fig. 2 d, remove the major part of the grid oxide layer 3 of chip, keep the integrality of grid oxide layer 3 oxides of skim with protection grid ground floor polysilicon 41 bottoms by dry etching.
So far, the bottom characteristic of the grid ground floor polysilicon 41 of chip comes out.
At last, utilize the length and width dimensional parameters of chip grid ground floor polysilicon 41 bottoms on the observation instrument observation plummer 9.
Observation instrument can adopt high vacuum scanning electron microscope (High Vacuum SEM) or low vacuum scanning electron microscope (Low Vacuum SEM), because it is extremely thin through mechanical lapping and chip after etching, can not well meet the observation requirement of high vacuum scanning electron microscope, thereby adopt the low vacuum scanning electron microscope to be observed the preferred version of the inventive method.
Above method is a kind of embodiment of the inventive method at a kind of chip structure, and the inventive method can be widely used in the failure analysis of different memory chip and other semi-conductor chips.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (12)
1. chip failure analytical approach is used for the defect characteristic of detection chip grid, may further comprise the steps:
Remove the substrate of the chip that carries out failure analysis and the major part of active area by mechanical lapping;
Remove remaining substrate and the active area of chip by wet etching;
Remove the major part of the grid oxide layer of chip by dry etching, the part grid oxide layer of reservation is used to protect grid first polysilicon layer;
Detect described first polysilicon layer and whether have defect characteristic.
2. chip failure analytical approach as claimed in claim 1 is characterized in that, the step of described chip failure analytical approach also comprises: the chip front side that will carry out failure analysis before carrying out mechanical lapping pastes on the plummer with bonding agent down.
3. chip failure analytical approach as claimed in claim 1 is characterized in that, the described chip that carries out failure analysis is a complete chip, or the part of the chip under the cutting.
4. chip failure analytical approach as claimed in claim 2 is characterized in that, the material of described plummer is a glass.
5. chip failure analytical approach as claimed in claim 2 is characterized in that, described mechanical lapping is automatically ground and realized by plummer and chip being put into automatic grinding device.
6. chip failure analytical approach as claimed in claim 2 is characterized in that, described mechanical lapping adopts the manual plummer of lifting sample to be pressed in the mechanical lapping that realizes on the muller chip.
7. chip failure analytical approach as claimed in claim 1, it is characterized in that, describedly remove the remaining substrate of chip and the step of active area comprises by wet etching: chip is put in the weakly alkaline solution of the heating that has added isopropyl alcohol, remaining substrate and active area removed fully on chip.
8. chip failure analytical approach as claimed in claim 7 is characterized in that, the temperature of the weakly alkaline solution of described heating is 80-85 ℃.
9. chip failure analytical approach as claimed in claim 7 is characterized in that, described weakly alkaline solution is that concentration is lower than 40% potassium hydroxide solution.
10. chip failure analytical approach as claimed in claim 7, it is characterized in that, describedly remove the remaining substrate of chip and the step of active area also comprises: pull out after chip is put into hydrogen peroxide number minute, use deionized water chip to be cleaned and make the chip drying by wet etching.
11. chip failure analytical approach as claimed in claim 10 is characterized in that, the temperature of described hydrogen peroxide is 50-90 ℃.
12. chip failure analytical approach as claimed in claim 1 is characterized in that, adopts high vacuum scanning electron microscope or low vacuum scanning electron microscope to detect described first polysilicon layer and whether has defect characteristic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010181477 CN102253325B (en) | 2010-05-21 | 2010-05-21 | Method for analyzing chip failure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010181477 CN102253325B (en) | 2010-05-21 | 2010-05-21 | Method for analyzing chip failure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102253325A true CN102253325A (en) | 2011-11-23 |
| CN102253325B CN102253325B (en) | 2013-07-31 |
Family
ID=44980695
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010181477 Active CN102253325B (en) | 2010-05-21 | 2010-05-21 | Method for analyzing chip failure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102253325B (en) |
Cited By (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103776668A (en) * | 2012-10-26 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of active region failure analysis sample of semiconductor device |
| CN103811410A (en) * | 2012-11-12 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Method for finding weak connection of through holes |
| CN103809103A (en) * | 2012-11-08 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Chip failpoint positioning method |
| CN103926120A (en) * | 2014-03-20 | 2014-07-16 | 上海华力微电子有限公司 | Preparation method of SEM sample |
| CN103969569A (en) * | 2013-01-25 | 2014-08-06 | 上海华虹宏力半导体制造有限公司 | Preparation method and analytical method for back optical failure positioning sample of integrated circuit |
| CN104049199A (en) * | 2014-06-16 | 2014-09-17 | 武汉新芯集成电路制造有限公司 | Failure analysis system |
| CN104237239A (en) * | 2013-06-09 | 2014-12-24 | 致茂电子(苏州)有限公司 | Detection method for defects of semiconductor element |
| CN104332420A (en) * | 2013-07-22 | 2015-02-04 | 中芯国际集成电路制造(上海)有限公司 | Method for positioning failure points of polysilicon layer |
| CN104535392A (en) * | 2015-01-05 | 2015-04-22 | 武汉新芯集成电路制造有限公司 | Flat sample manufacturing method capable of improving quality of transmission electron microscope images |
| CN104700903A (en) * | 2014-12-24 | 2015-06-10 | 上海华虹宏力半导体制造有限公司 | Memory chip scrambling verification method |
| CN105334445A (en) * | 2014-06-18 | 2016-02-17 | 上海华力微电子有限公司 | Back failure positioning method of chip |
| CN105334085A (en) * | 2014-08-12 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Sample preparation method and secondary ion mass spectrometry method |
| CN105513986A (en) * | 2014-10-14 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting bottom defects of grid electrode |
| CN106596609A (en) * | 2016-12-15 | 2017-04-26 | 武汉新芯集成电路制造有限公司 | Method for making transmission electron microscope samples |
| CN106997856A (en) * | 2016-01-25 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | The sample treatment of wafer acceptability test is carried out for open-grid resistance |
| CN108091561A (en) * | 2017-12-19 | 2018-05-29 | 北京智芯微电子科技有限公司 | It is a kind of uniformly to remove layer method for aluminum manufacturing procedure chip |
| CN108447796A (en) * | 2018-03-14 | 2018-08-24 | 中国空间技术研究院 | A kind of semiconductor chip structure parameters analysis method |
| CN109342920A (en) * | 2018-09-30 | 2019-02-15 | 上海华力集成电路制造有限公司 | IC chip failure independent positioning method |
| CN109406555A (en) * | 2018-10-15 | 2019-03-01 | 上海华力微电子有限公司 | A kind of sample removes hierarchical method |
| CN109716148A (en) * | 2016-09-16 | 2019-05-03 | 高通股份有限公司 | The isolation of visible laser fault |
| CN110836905A (en) * | 2019-11-13 | 2020-02-25 | 上海华力集成电路制造有限公司 | Failure analysis method for automatically identifying physical defects of chip |
| CN111883453A (en) * | 2020-08-28 | 2020-11-03 | 长江存储科技有限责任公司 | Wafer obtaining method and semiconductor device failure analysis method |
| CN112179915A (en) * | 2019-07-04 | 2021-01-05 | 深圳长城开发科技股份有限公司 | Layer removing method for positioning damage points in bare chip |
| TWI738568B (en) * | 2020-11-18 | 2021-09-01 | 汎銓科技股份有限公司 | A method of preparing a semiconductor specimen for failure analysis |
| CN113675083A (en) * | 2021-10-25 | 2021-11-19 | 江山季丰电子科技有限公司 | Method for exposing active region of silicon-on-insulator device, application and failure analysis method |
| CN113702807A (en) * | 2021-08-25 | 2021-11-26 | 长鑫存储技术有限公司 | Chip carrier and chip detection device |
| CN114089171A (en) * | 2022-01-19 | 2022-02-25 | 北京软件产品质量检测检验中心 | Chip measurement and control system and test method for integrated circuit electrical failure analysis |
| CN114354665A (en) * | 2022-03-21 | 2022-04-15 | 晶芯成(北京)科技有限公司 | Stripping method for failure chip |
| CN114778537A (en) * | 2022-04-12 | 2022-07-22 | 胜科纳米(苏州)股份有限公司 | Method for identifying failure mechanism of transistor gate silicon oxide layer |
| CN116148642A (en) * | 2023-04-21 | 2023-05-23 | 上海聚跃检测技术有限公司 | Chip failure analysis method and device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106646196A (en) * | 2016-12-23 | 2017-05-10 | 苏州华碧微科检测技术有限公司 | On-board direct current voltage reduction chip failure analysis method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1147146A (en) * | 1995-06-30 | 1997-04-09 | 现代电子产业株式会社 | Deprocessing method for analyzing failure in semiconductor device |
| US5677204A (en) * | 1995-10-17 | 1997-10-14 | Mitsubishi Denki Kabushiki Kaisha | Method of evaluating a thin film for use in semiconductor device |
| US6482748B1 (en) * | 1999-09-03 | 2002-11-19 | Taiwan Semiconductor Manufacturing Company | Poly gate silicide inspection by back end etching |
-
2010
- 2010-05-21 CN CN 201010181477 patent/CN102253325B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1147146A (en) * | 1995-06-30 | 1997-04-09 | 现代电子产业株式会社 | Deprocessing method for analyzing failure in semiconductor device |
| US5677204A (en) * | 1995-10-17 | 1997-10-14 | Mitsubishi Denki Kabushiki Kaisha | Method of evaluating a thin film for use in semiconductor device |
| US6482748B1 (en) * | 1999-09-03 | 2002-11-19 | Taiwan Semiconductor Manufacturing Company | Poly gate silicide inspection by back end etching |
Non-Patent Citations (1)
| Title |
|---|
| 陈媛等: "芯片剥层技术在集成电路失效分析中的应用", 《电子产品可靠性与环境试验》, 19 October 2009 (2009-10-19) * |
Cited By (42)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103776668B (en) * | 2012-10-26 | 2016-03-09 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices active region failure analysis sample |
| CN103776668A (en) * | 2012-10-26 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of active region failure analysis sample of semiconductor device |
| CN103809103A (en) * | 2012-11-08 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Chip failpoint positioning method |
| CN103809103B (en) * | 2012-11-08 | 2017-02-08 | 中芯国际集成电路制造(上海)有限公司 | Chip failpoint positioning method |
| CN103811410A (en) * | 2012-11-12 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Method for finding weak connection of through holes |
| CN103811410B (en) * | 2012-11-12 | 2016-10-19 | 上海华虹宏力半导体制造有限公司 | The method finding through hole Weak link |
| CN103969569A (en) * | 2013-01-25 | 2014-08-06 | 上海华虹宏力半导体制造有限公司 | Preparation method and analytical method for back optical failure positioning sample of integrated circuit |
| CN104237239A (en) * | 2013-06-09 | 2014-12-24 | 致茂电子(苏州)有限公司 | Detection method for defects of semiconductor element |
| CN104237239B (en) * | 2013-06-09 | 2017-02-08 | 致茂电子(苏州)有限公司 | Detection method for defects of semiconductor element |
| CN104332420A (en) * | 2013-07-22 | 2015-02-04 | 中芯国际集成电路制造(上海)有限公司 | Method for positioning failure points of polysilicon layer |
| CN103926120A (en) * | 2014-03-20 | 2014-07-16 | 上海华力微电子有限公司 | Preparation method of SEM sample |
| CN104049199A (en) * | 2014-06-16 | 2014-09-17 | 武汉新芯集成电路制造有限公司 | Failure analysis system |
| CN105334445A (en) * | 2014-06-18 | 2016-02-17 | 上海华力微电子有限公司 | Back failure positioning method of chip |
| CN105334085A (en) * | 2014-08-12 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Sample preparation method and secondary ion mass spectrometry method |
| CN105334085B (en) * | 2014-08-12 | 2018-03-20 | 中芯国际集成电路制造(上海)有限公司 | Sample preparation methods and SIMS analysis method |
| CN105513986A (en) * | 2014-10-14 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting bottom defects of grid electrode |
| CN105513986B (en) * | 2014-10-14 | 2019-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting the bottom defect of grid |
| CN104700903A (en) * | 2014-12-24 | 2015-06-10 | 上海华虹宏力半导体制造有限公司 | Memory chip scrambling verification method |
| CN104535392A (en) * | 2015-01-05 | 2015-04-22 | 武汉新芯集成电路制造有限公司 | Flat sample manufacturing method capable of improving quality of transmission electron microscope images |
| CN106997856B (en) * | 2016-01-25 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Sample processing method for wafer acceptability test aiming at grid open-circuit resistance |
| CN106997856A (en) * | 2016-01-25 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | The sample treatment of wafer acceptability test is carried out for open-grid resistance |
| CN109716148A (en) * | 2016-09-16 | 2019-05-03 | 高通股份有限公司 | The isolation of visible laser fault |
| CN106596609A (en) * | 2016-12-15 | 2017-04-26 | 武汉新芯集成电路制造有限公司 | Method for making transmission electron microscope samples |
| CN106596609B (en) * | 2016-12-15 | 2019-05-03 | 武汉新芯集成电路制造有限公司 | A method of making transmission electron microscope sample |
| CN108091561A (en) * | 2017-12-19 | 2018-05-29 | 北京智芯微电子科技有限公司 | It is a kind of uniformly to remove layer method for aluminum manufacturing procedure chip |
| CN108091561B (en) * | 2017-12-19 | 2020-02-07 | 北京智芯微电子科技有限公司 | Uniform layer removing method for aluminum process chip |
| CN108447796A (en) * | 2018-03-14 | 2018-08-24 | 中国空间技术研究院 | A kind of semiconductor chip structure parameters analysis method |
| CN109342920A (en) * | 2018-09-30 | 2019-02-15 | 上海华力集成电路制造有限公司 | IC chip failure independent positioning method |
| CN109406555A (en) * | 2018-10-15 | 2019-03-01 | 上海华力微电子有限公司 | A kind of sample removes hierarchical method |
| CN112179915A (en) * | 2019-07-04 | 2021-01-05 | 深圳长城开发科技股份有限公司 | Layer removing method for positioning damage points in bare chip |
| CN110836905A (en) * | 2019-11-13 | 2020-02-25 | 上海华力集成电路制造有限公司 | Failure analysis method for automatically identifying physical defects of chip |
| CN111883453B (en) * | 2020-08-28 | 2021-11-12 | 长江存储科技有限责任公司 | Wafer obtaining method and semiconductor device failure analysis method |
| CN111883453A (en) * | 2020-08-28 | 2020-11-03 | 长江存储科技有限责任公司 | Wafer obtaining method and semiconductor device failure analysis method |
| TWI738568B (en) * | 2020-11-18 | 2021-09-01 | 汎銓科技股份有限公司 | A method of preparing a semiconductor specimen for failure analysis |
| CN113702807A (en) * | 2021-08-25 | 2021-11-26 | 长鑫存储技术有限公司 | Chip carrier and chip detection device |
| CN113675083A (en) * | 2021-10-25 | 2021-11-19 | 江山季丰电子科技有限公司 | Method for exposing active region of silicon-on-insulator device, application and failure analysis method |
| CN113675083B (en) * | 2021-10-25 | 2021-12-21 | 江山季丰电子科技有限公司 | Method for exposing active region of silicon-on-insulator device, application and failure analysis method |
| CN114089171A (en) * | 2022-01-19 | 2022-02-25 | 北京软件产品质量检测检验中心 | Chip measurement and control system and test method for integrated circuit electrical failure analysis |
| CN114354665A (en) * | 2022-03-21 | 2022-04-15 | 晶芯成(北京)科技有限公司 | Stripping method for failure chip |
| CN114354665B (en) * | 2022-03-21 | 2022-05-17 | 晶芯成(北京)科技有限公司 | Stripping method for failure chip |
| CN114778537A (en) * | 2022-04-12 | 2022-07-22 | 胜科纳米(苏州)股份有限公司 | Method for identifying failure mechanism of transistor gate silicon oxide layer |
| CN116148642A (en) * | 2023-04-21 | 2023-05-23 | 上海聚跃检测技术有限公司 | Chip failure analysis method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102253325B (en) | 2013-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102253325B (en) | Method for analyzing chip failure | |
| CN101996911B (en) | Failure analysis method of gate oxide | |
| KR101242246B1 (en) | Apparatus for measuring impurities on wafer and Method for measuring impurities on wafer | |
| CN109920742B (en) | Semiconductor device failure detection method | |
| WO2003090262A1 (en) | Apparatus and method for semiconductor wafer test yield enhancement | |
| US20220362815A1 (en) | Wafer wet cleaning system | |
| US7314766B2 (en) | Semiconductor wafer treatment method, semiconductor wafer inspection method, semiconductor device development method and semiconductor wafer treatment apparatus | |
| CN104020408A (en) | Memory chip bit line failure analyzing method | |
| CN104851820A (en) | Semiconductor device defect detection method | |
| US20100258143A1 (en) | Scrubber clean before oxide chemical mechanical polish (cmp) for reduced microscratches and improved yields | |
| US20080318343A1 (en) | Wafer reclaim method based on wafer type | |
| JP3910324B2 (en) | Semiconductor manufacturing equipment | |
| CN111257715B (en) | Wafer testing method and device | |
| US7745236B2 (en) | Floating gate process methodology | |
| JP4346537B2 (en) | Surface inspection apparatus and surface inspection method | |
| CN104821284B (en) | It is removed using the superficial layer of programming executor | |
| Choi et al. | A new Delayering application workflow in advanced 5nm technology device with xenon plasma focus ion beam microscopy | |
| Morillo et al. | Edge and bevel automated defect inspection for 300mm production wafers in manufacturing | |
| CN112435961A (en) | Sample processing method in wafer failure analysis | |
| Song et al. | Efficient Identification of Wafer Edge’s Defect with Volume Diagnosis Analysis and Plasma-FIB Planar Deprocessing | |
| Zachariasse | CMOS front-end investigation over large areas by deprocessing from the back side | |
| Nowakowski et al. | An innovative technique for large-scale delayering of semiconductor devices with nanometric-scale surface flatness | |
| US7078247B2 (en) | Early detection of contact liner integrity by chemical reaction | |
| US6171874B1 (en) | Non-defect image and data transfer and storage methodology | |
| Peng et al. | A novel solution for efficient in situ TEM cross-section and plan-view analyses with an advanced sample preparation scheme |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 201203 No. 18 Zhangjiang Road, Shanghai Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Country or region after: China Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Country or region before: China Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. |