CN109342920A - IC chip failure independent positioning method - Google Patents
IC chip failure independent positioning method Download PDFInfo
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- CN109342920A CN109342920A CN201811154287.8A CN201811154287A CN109342920A CN 109342920 A CN109342920 A CN 109342920A CN 201811154287 A CN201811154287 A CN 201811154287A CN 109342920 A CN109342920 A CN 109342920A
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- chip
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- independent positioning
- fails
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a kind of IC chip failure independent positioning methods, comprising the following steps: releases tested IC chip ground connection；It releases and is connected between tested each structure of IC chip；Ground connection operation is carried out to tested IC chip short circuit monitoring route；Failpoint is accurately positioned by secondary electron voltage contrast (VC).IC chip failure independent positioning method provided by the invention changes the old process of the failure analysis slave interconnection line layer to device layer of conventional localization method, by realizing accurate positionin to the method for interconnection line layer from device layer.The failure analysis of IC chip ground short circuit failure mode itself can be realized using IC chip failure independent positioning method of the invention, and then find the failure cause of this type failure mode, the improvement of auxiliary pushing online process, and then promote product yield.
Description
Technical field
The present invention relates to semiconductor fields, more particularly to a kind of IC chip failure independent positioning method.
Background technique
The failure analysis process of integrated circuit routine includes: first electrically verifying failure mode, then with various means into
Row failure positioning, the basic reason of failure is found in anchor point in turn using various Physical Property Analysis, wherein failure positioning is very
A crucial step, we will be positioned on the chip of a millimeter magnitude by failure, by failpoint locking in micron
To nanometer scale, the considered repealed point of nanoscale is finally determined by physical method again.It can thus be appreciated that failure location technology exists
Important function in semiconductor chip analysis.
The positioning means that commonly fail in semicon industry at present have photon radiation microscope (EMMI), light value resistance value respectively
Change microscope (OBIRCH), heat emission microscope (Thermal), nano-probe technology and secondary electron voltage contrast
The methods of (VC).Conventional FAILURE ANALYSIS TECHNOLOGY means take forward analysis method " from top to bottom ": fixed using optics first
Then position equipment coarse localization failpoint successively grinds de-layer and is accurately positioned abnormal position using some means.With partly leading
Body technology technology is increasingly advanced, and failure analysis becomes increasingly complex, can not be accurately using this conventional positioning analysis means
Surely invalid position is arrived.
In actual operation, failpoint can not be navigated to conventional method by encountering a kind of short circuit, structure as shown in Figure 1, when
In the case that appearance the first metal layer M1 and contact hole CT has short circuit, ideal situation is accurately determined in this way it is desirable that obtaining Fig. 1
Position information.But when being positioned using conventional method, the metal layer on upper layer or the structure of same level can be interfered or even be blocked from target
The location information of structural feedback can cause very big difficulty (as shown in Figure 3) to being accurately positioned, so that subsequent transmitted electron is aobvious
Micro mirror (TEM) analysis can not carry out, and entire failure analysis is caused to fail.It is pinpoint currently without being carried out for short-circuit structure
Effective ways.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of pinpoint ic core can be carried out to short-circuit structure
Piece failure independent positioning method
In order to solve the above technical problems, the present invention provides a kind of IC chip failure independent positioning method, including following
Step:
1) tested IC chip ground state is released；
2) continuous state between tested each structure of IC chip is released；The knot that analysis method of the invention is directed to
Structure is a kind of continuous line of M1+CT+AA composition, if AA (active area) is removed, the route for lacking AA link will be located
The continuous state between each structure is released in open-circuit condition.
3) ground connection operation is carried out to tested IC chip short circuit monitoring route；
4) failpoint is accurately positioned by secondary electron voltage contrast (VC).
It is further improved the IC chip failure independent positioning method, wherein implementation steps 1) when, by tested collection
It is fixed on slide glass at circuit chip front using solidification glue, it is back side up to be tested IC chip.
It is further improved the IC chip failure independent positioning method, wherein implementation steps 1) when, slide glass area is
0.8cm2-1.2cm2。
It is further improved the IC chip failure independent positioning method, wherein implementation steps 2) when, by tested collection
It is thinned at circuit chip back side silicon base, until energy clear view connects to tested IC chip under the first preset condition
Contact hole figure, AA are removed, and are connected and are released between tested each structure of IC chip, and all contact holes are in outstanding
It is empty.
It is further improved the IC chip failure independent positioning method, wherein implementation steps 2) when, utilize polishing machine
(Auto-polisher) tested IC chip back side silicon base is thinned.
It is further improved the IC chip failure independent positioning method, wherein implementation steps 2) when, ic core
Piece back side silicon base, which is thinned, will keep the former all structural integrities of IC chip.
It is further improved the IC chip failure independent positioning method, wherein implementation steps 2) when, the first default item
Part is: scanning electron microscope (SEM) 1kv-3kv condition energy clear view to tested IC chip contact hole graph.
It is further improved the IC chip failure independent positioning method, wherein implementation steps 3) when, it is ensured that ground connection behaviour
Make breakthrough solidification glue, makes to need earthing test integrated circuit chip structure and slide glass connection.
Be further improved IC chip failure independent positioning method, wherein implementation steps 3) when, using focus from
Beamlet (FIB) or laser calibration (Laser marker) ensure that tested IC chip ground connection operation breaks through solidification glue.
It is further improved the IC chip failure independent positioning method, wherein implementation steps 4) when, if tested collection
Difference, which is formed, with the mutually isostructural voltage contrast of surrounding at the voltage contrast of circuit chip region contact hole then judges the region
For failpoint.
IC chip provided by the invention failure independent positioning method change conventional localization method " from interconnection line layer
To device layer " old process of failure analysis, accurate positionin is realized by the method for " from device layer to interconnection line layer ".This hair
The IC chip failure independent positioning method of bright offer is released tested integrated by the accurate thinned die back side to contact hole
The ground state and continuous state of circuit chip itself.Then the structure with tested IC chip short circuit is grounded
Operation generates the contact hole of the abnormal location of short circuit of tested IC chip not at scanning electron microscope (SEM)
The voltage contrast picture of same secondary electron, to be accurately positioned failpoint.It is fixed using IC chip failpoint of the invention
Position method can realize the failure analysis of IC chip ground short circuit failure mode itself, and then find the failure of this type
The failure cause of mode, the improvement of auxiliary pushing online process, and then promote product yield.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is that a kind of there are the integrated circuit chip structure schematic diagrames of the first metal layer and contact hole short circuit.
Fig. 2 is the ideal failure point location schematic diagram that structure shown in Fig. 1 should be obtained by the positioning of existing theory analysis.
Fig. 3 is that structure shown in Fig. 1 is positioned the failure point location schematic diagram actually obtained by existing theory analysis
Fig. 4 is present invention failure independent positioning method schematic diagram one.
Fig. 5 is present invention failure independent positioning method schematic diagram two.
Fig. 6 is present invention failure independent positioning method schematic diagram three.
Description of symbols
1 is AA
2 be the first metal layer ground area
3 be the hanging region of the first metal layer
4 be SEM objective table
5 be slide glass
6 be solidification glue
7 be contact hole
8 be silicide
9 be silicon base
A is the failpoint domain of the existence (area to be tested) of tested IC chip
B is the ground structure (detection structure) of tested IC chip
C is failpoint
D is grounding point.
Specific embodiment
The present invention provides a kind of IC chip failure one possible embodiments of independent positioning method, comprising the following steps:
1) tested IC chip ground connection is released；
As shown in figure 4, tested IC chip positive (arranging devices face) is attached to one piece of 0.8- with solidification glue
On 1.2cm2 slide glass, it is tested the IC chip back side (basal surface) upwards, so realizes the hanging shape of whole sample
State.
2) it releases and is connected between tested each structure of IC chip；As shown in figure 5, utilizing automatic polishing machine Auto-
Polisher is to tested IC chip thinning back side chip silicon base to be analyzed, until in scanning electron microscope
(SEM) until capable of seeing tested IC chip contact hole graph under the conditions of 1KV-3kv clearly, AA is removed at this time, and structure connects
Continuous state is released from, and all contact holes are in vacant state.Tested IC chip thinning back side will keep all knots
Structure is complete.
3) ground connection operation is carried out to tested IC chip short circuit monitoring route；Using focused ion beam (FIB) or
Laser calibration (Laser marker) ensures to be grounded operation and breaks through solidification glue, makes to need ground structure and slide glass connection, if ground junction
There is the voltage contrast of secondary electron in structure, then is grounded success.
4) failpoint is accurately positioned by secondary electron voltage contrast (VC).IC chip is tested in step 1)
Ground connection released, be tested the failpoint domain of the existence (area to be tested) of IC chip and tested integrated electric at this time
The state of road chip ground structure (detection structure) is different.When the failpoint domain of the existence of tested IC chip is (to be checked
Survey region) when certain has short-circuit conditions, corresponding contact hole just will appear voltage contrast and the mutually isostructural voltage contrast of surrounding
The case where forming difference, to be pin-pointed to failpoint.If the voltage lining of tested IC chip region contact hole
Degree then judges the region for failpoint.
With the CAA chain (chain structure that metal interconnection wire, contact hole, active area collectively constitute) of real work with
For Comb metal short (comb teeth-shaped metal interconnection cable architecture, whether short-circuit to monitor CAA chain), routine is used
Method (EMMI/OBIRCH/THERMAL positioning, Nano-probe location technology, the modes such as point-by-point SEM inspection) fails to find
Invalid position, afterwards using IC chip failure independent positioning method of the invention, after IC chip thinning back side, from
The IC chip has obtained VC effect backwards to actual measurement, and realizes the accurate positioning of failpoint.
Above by specific embodiment and embodiment, invention is explained in detail, but these are not composition pair
Limitation of the invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Into these also should be regarded as protection scope of the present invention.
Claims (10)
- The independent positioning method 1. a kind of IC chip fails, which comprises the following steps:1) tested IC chip ground state is released；2) continuous state between tested each structure of IC chip is released；3) ground connection operation is carried out to tested IC chip short circuit monitoring route；4) failpoint is accurately positioned by secondary electron voltage contrast (VC).
- The independent positioning method 2. IC chip as described in claim 1 fails, it is characterised in that: implementation steps 1) when, it will be by Testing integrated circuit chip front is fixed on slide glass using solidification glue, and it is back side up to be tested IC chip.
- The independent positioning method 3. IC chip as claimed in claim 2 fails, it is characterised in that: implementation steps 1) when, slide glass Area is 0.8cm2-1.2cm2.
- The independent positioning method 4. IC chip as described in claim 1 fails, it is characterised in that: implementation steps 2) when, it will be by Testing integrated circuit chip back side silicon base is thinned, until under the first preset condition can clear view to tested integrated circuit Chip contact hole graph, active area are removed, and are tested the state connected between each structure of IC chip by active area It is released from, and all contact holes are in vacant state.
- The independent positioning method 5. IC chip as claimed in claim 4 fails, it is characterised in that: implementation steps 2) when, it utilizes Tested IC chip back side silicon base is thinned polishing machine (Auto-polisher).
- The independent positioning method 6. IC chip as claimed in claim 5 fails, it is characterised in that: implementation steps 2) when, it integrates Circuit chip back side silicon base, which is thinned, will keep all regional structures to be analyzed of IC chip complete.
- The independent positioning method 7. IC chip as claimed in claim 6 fails, it is characterised in that: implementation steps 2) when, first Preset condition is: scanning electron microscope (SEM) 1kv-3kv condition energy clear view to tested IC chip contact hole Figure.
- The independent positioning method 8. IC chip as claimed in claim 2 fails, it is characterised in that: implementation steps 3) when, it is ensured that Ground connection operation breaks through solidification glue, makes to need earthing test integrated circuit chip structure and slide glass connection.
- The independent positioning method 9. IC chip as claimed in claim 8 fails, it is characterised in that: implementation steps 3) when, it utilizes Focused ion beam (FIB) or laser calibration equipment (Laser marker) ensure that tested IC chip ground connection operation is broken through Solidification glue.
- The independent positioning method 10. IC chip as described in claim 1 fails, it is characterised in that: implementation steps 4) when, if by The voltage contrast of testing integrated circuit chip region contact hole forms difference with the mutually isostructural voltage contrast of surrounding and then judges The region is failpoint.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811154287.8A CN109342920A (en) | 2018-09-30 | 2018-09-30 | IC chip failure independent positioning method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811154287.8A CN109342920A (en) | 2018-09-30 | 2018-09-30 | IC chip failure independent positioning method |
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| CN109342920A true CN109342920A (en) | 2019-02-15 |
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| CN201811154287.8A Pending CN109342920A (en) | 2018-09-30 | 2018-09-30 | IC chip failure independent positioning method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111239590A (en) * | 2020-02-24 | 2020-06-05 | 珠海格力电器股份有限公司 | Method and device for positioning electrostatic damage of chip |
| CN112305407A (en) * | 2020-10-21 | 2021-02-02 | 上海华力集成电路制造有限公司 | Method for positioning failure position and reason of test structure |
| CN112379242A (en) * | 2020-10-27 | 2021-02-19 | 珠海格力电器股份有限公司 | Chip failure point positioning method, device and system |
| CN114089171A (en) * | 2022-01-19 | 2022-02-25 | 北京软件产品质量检测检验中心 | Chip measurement and control system and test method for integrated circuit electrical failure analysis |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111239590A (en) * | 2020-02-24 | 2020-06-05 | 珠海格力电器股份有限公司 | Method and device for positioning electrostatic damage of chip |
| CN111239590B (en) * | 2020-02-24 | 2020-12-04 | 珠海格力电器股份有限公司 | Method and device for positioning electrostatic damage of chip |
| CN112305407A (en) * | 2020-10-21 | 2021-02-02 | 上海华力集成电路制造有限公司 | Method for positioning failure position and reason of test structure |
| CN112305407B (en) * | 2020-10-21 | 2024-06-11 | 上海华力集成电路制造有限公司 | Method for locating failure position and reason of test structure |
| CN112379242A (en) * | 2020-10-27 | 2021-02-19 | 珠海格力电器股份有限公司 | Chip failure point positioning method, device and system |
| CN114089171A (en) * | 2022-01-19 | 2022-02-25 | 北京软件产品质量检测检验中心 | Chip measurement and control system and test method for integrated circuit electrical failure analysis |
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Application publication date: 20190215 |