CN102466778A - Failure positioning method for defects of power metal-oxide-semiconductor chip - Google Patents
Failure positioning method for defects of power metal-oxide-semiconductor chip Download PDFInfo
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Abstract
The invention discloses a failure positioning method for defects of a power metal-oxide-semiconductor chip, comprising steps of: 1) removing an aluminum layer on the surface of the power metal-oxide-semiconductor chip; and 2) as for the chip comprising a Ti/TiN diffusion impervious layer under the aluminum layer, perfusing current into grid, source and drain of the chip by directly inserting needles to perform EMMI (Emission Microscopy) or OBIRCH (Optical Beam Induced Resistance Change) analysis, and then positioning defects; and as for the chip comprising no diffusion impervious layer under the aluminum layer, depositing two metal pads by FIB (Focused Ion Beam) at an area free from transistors in the chip, further depositing a metal strip in connection with the metal pad at the edge of each metal pad by FIB, wherein the other ends of the two metal strips are respectively connected with the grid and the source, and completing EMMI or OBIRCH tests by using the two metal pads and the drain on the back of the chip, and then positioning the defects. The failure positioning method for the defects of the power metal-oxide-semiconductor chip has effect far better than liquid crystal analysis, and the defect positions can be rapidly and accurately found.
Description
Technical field
The present invention relates to a kind of inefficacy localization method of semi-conductor chip, particularly relate to a kind of defective inefficacy localization method that is used for power metal-oxide transistor (Power Metal-Oxide-Semiconductor, Power MOS) chip.
Background technology
In the common structure of power metal-oxide transistor (Power MOS) chip; Tens thousand of above transistorized grids (polysilicon formation) are connected in parallel, and chip back is drain electrode, and chip front side is a source electrode; Through the band diffusion impervious layer [titanium nitride (TiN) that covers several micron thick; The hundreds of dust is thick] aluminium lamination and connect together, and from the needs of follow-up bonding, big portion zone no longer covers other materials (this provides condition for enforcement of the present invention) on the aluminium lamination.Power MOS has a variety of structures, comprises VMOS (V-type groove MOS), UMOS, and DMOS or the like, wherein, the master of VMOS chip looks synoptic diagram and schematic top plan view respectively like Fig. 1, shown in Figure 2.
The process of chip failure analysis is to find defective and then analyzing defect earlier.Existing liquid crystal analysis (Liquid Crystal, LC) technology is that liquid crystal material is applied to the whole surface of chip, the chip energising gets into failure state then; For the electric leakage zone, current density is maximum, and the local heating of generation is the most serious; Temperature rises, and material embodies liquid crystal state under this temperature then, solid-state lattice and liquid fluidity; Use polarized light microscope observing again, can see spot shape image at fault location, so far defect location is accomplished.But the problem that this defect positioning method exists is following:
1. require electric leakage bigger, usually more than milliampere;
2. represent the spot shape image of defective locations, area big (more than tens of square microns) usually can cover tens unit (or transistor), and when this defective during in micron dimension, such location is too coarse, and scope is too big, can't accomplish follow-up physics microanalysis;
3. it can only locate big defective or the defective very serious to performance impact.
In addition, also have some technology to be applied to imaging, chip failure location, analysis for current leakage etc., specific as follows:
1. the focused particle beam electron microscope (Focused Ion Beam, FIB)
This equipment or technology as incident particle (or being primary ions) bump sample surfaces, can form secondary ion, secondary electron etc. with the gallium positive ion beam after focusing on, again through collecting the secondary electron imaging; Most common use has section fine cut, imaging (comprising the voltage contrast picture), transmission electron microscope sample preparation, circuit reparation (comprising perforate and metal cladding line) etc.
2. light emission microscopic analysis technology (Emission Microscopy, EMMI)
What utilize is semiconductor light emitting principle (semiconductor excites in all kinds of external worlds down, excites like electricity, and electronics has the emission of photon in be with or during difference ability interband generation transition); Through with specialized camera [like Si-CCD (Silicon-Charge Coupled Device, silicon charge-coupled image sensor) camera], photon is caught; Obtain light emission analysis image; The stack of the material object picture of this image and chip just can be judged luminous particular location, the most seriously position of leaking electricity exactly, this position.EMMI is suitable for the relevant inefficacy location of junction leakage.Bearing accuracy can be depending on the camera lens of equipment, and to model PHEMOS1000 commonly used, enlargement ratio reaches 1000, and resolution is less than 1 micron.
3. photic impedance variations technology (Optical Beam Induced Resistance Change, OBIRCH)
Cause resistance variations through LASER HEATING, resistance variations causes that electric current changes or change in voltage, and this changes can be by equipment records, and the fault location resistance characteristic often changes more responsive, thereby orients defective locations.OBIRCH is suitable for the analysis for current leakage of Ohmic contact class.Bearing accuracy can be depending on the camera lens of equipment, and to model PHEMOS1000 commonly used, enlargement ratio reaches 1000, and resolution is less than 1 micron.
But for POWER MOS chip, an inner transistor leakage lost efficacy the chip global failure; And all tens thousand of above transistor arrangements are identical; And all covered by thick metal, thick metal layers possesses the highly reflective to light, to the splendid heat conductivity of heat; To therefrom find very difficulty of defective or imperfect crystal pipe, and yet not have good method at present.
Summary of the invention
The technical matters that the present invention will solve provides a kind of defective inefficacy localization method that is used for power metal-oxide transistor (PowerMOS) chip.This method can find the position of the defective that causes inefficacy fast, and be accurate to individual unit (or transistor) to the Power MOS chip that exists electric leakage to lose efficacy from tens thousand of above repetitives (or transistor).Just can find failure cause and improvement method afterwards through physical analysis to defective.
For solving the problems of the technologies described above, the defective inefficacy localization method that is used for the power metal-oxide transistor chip of the present invention comprises step:
(1) removes surperficial aluminium (Al) layer of power metal-oxide transistor chip with acid; Wherein, this acid is epistasis and the acid of free-floride (F) element of oxidisability of not having, and comprising: hydrochloric acid, dilute sulfuric acid, phosphoric acid etc.;
(2) for the power metal-oxide transistor chip of dissimilar removal surface aluminium laminations, adopt following method:
A, for the chip that contains Ti/TiN (titanium/titanium nitride) diffusion impervious layer under the aluminium lamination
After aluminium lamination is removed; Expose the Ti/TiN layer; Grid and source electrode exist metal to draw layer; Irritate through directly acupuncture treatment grid, source electrode, drain electrode that electric current is made light emission microscopic analysis technology (EMMI) or photic impedance variations technology (OBIRCH) is analyzed, objective lens is amplified to maximum 100 times guarantees that defect location arrives the transistor rank, orients the defective that is accurate to single transistor;
B, for the following chip of no diffusion impervious layer of aluminium lamination
After aluminium lamination is removed, the oxide layer of insulation below exposing; No transistor area in chip is with two metal gaskets of focused particle beam electron microscope (FIB) deposit; Again on the limit of each metal gasket with bonding jumper that is connected with this metal gasket of focused particle beam electron microscope deposit, the other end of two bonding jumpers respectively separate connection to grid and source electrode;
Utilize two metal gaskets and chip back drain electrode completion light emission microscopic analysis technology (EMMI) or photic impedance variations technology (OBIRCH) analysis; Objective lens is amplified to maximum 100 times guarantees that defect location arrives the transistor rank, orients the defective that is accurate to single transistor.
Described each metal gasket can be that size is the platinum pad of 50 microns of 50 microns *, be positioned at the no transistor area of chip, and two platinum pads does not link together.
It is 1 micron wide platinum bar that described each bonding jumper can be one, and length is to guarantee that the length that has connected platinum pad and needed grid or drain electrode is as the criterion, and also is deposited on the no transistor area in the chip.
The present invention can locate the defective or the trickle defective of small electric leakage; Simultaneously can navigate to single transistor; Through removing surperficial thick aluminium lamination earlier; Utilize existing EMMI and OBIRCH defect location instrument then, with finding out defective or the transistor of imperfect crystal pipe more than tens thousand of, for defective physical analysis at the back lays the first stone.Therefore, the present invention has following beneficial effect:
(1) speed is fast, and precision is high, after failure cause is found in the application of the invention and physical analysis subsequently, can help improve the problem that exists in Power MOS explained hereafter or the practical application, improves the quality of products, and produces great economic benefit;
(2) response low-carbon environment-friendly can be evaded it has been generally acknowledged that the liquid crystal that has a little toxicity uses;
(3) and qualitatively, all be far superior to the liquid crystal analysis from speed.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is that the master of VMOS chip looks synoptic diagram;
Fig. 2 is the schematic top plan view of VMOS chip;
Fig. 3 is that the master of VMOS chip among the embodiment looks synoptic diagram;
Fig. 4 is the schematic top plan view of VMOS chip among the embodiment;
Fig. 5 is that the master of the VMOS chip of surface removal aluminium lamination among the embodiment looks synoptic diagram;
Fig. 6 is the schematic top plan view of the VMOS chip of surface removal aluminium lamination among the embodiment;
Fig. 7 is that the master as a result with the VMOS chip behind EMMI or the OBIRCH lens analysis surface removal aluminium lamination looks synoptic diagram among the embodiment;
Fig. 8 is with the schematic top plan view as a result of the VMOS chip behind EMMI or the OBIRCH lens analysis surface removal aluminium lamination among the embodiment;
Fig. 9 is that the master of VMOS chip of the removal surface aluminium lamination of deposit platinum pad and platinum bar among the embodiment looks synoptic diagram;
Figure 10 is the schematic top plan view of VMOS chip of the removal surface aluminium lamination of deposit platinum pad and platinum bar among the embodiment;
Figure 11 is that the master with the VMOS chip of the removal of EMMI or OBIRCH lens analysis deposit platinum pad and platinum bar surface aluminium lamination looks synoptic diagram among the embodiment;
Figure 12 is with the schematic top plan view of the VMOS chip of the removal of EMMI or OBIRCH lens analysis deposit platinum pad and platinum bar surface aluminium lamination among the embodiment;
Figure 13 is to the VMOS chip, adopts the master as a result who obtains behind the methods analyst of the present invention to look synoptic diagram;
Figure 14 is to the VMOS chip, adopts the schematic top plan view as a result that obtains behind the methods analyst of the present invention;
Figure 15 is to the VMOS chip, looks synoptic diagram with the master as a result who obtains after the existing liquid crystal analytical;
Figure 16 is to the VMOS chip, with the schematic top plan view as a result that obtains after the existing liquid crystal analytical.
Embodiment
To be example, method of the present invention is described in the present embodiment to VMOS chip defect inefficacy positioning analysis.Wherein, there is the aluminium lamination of several micron thick in the surface of VMOS chip, and the master of this VMOS chip looks synoptic diagram and diagrammatic top view respectively like Fig. 3, shown in Figure 4.
In following examples, the model of the equipment camera lens that applies in light emission microscopic analysis technology (EMMI) or the photic impedance variations technology (OBIRCH) is PHEMOS100, available from Japanese Hamamatsu company.Wherein, utilization EMMI or OBIRCH technology are to be undertaken by existing conventional operation.
The defective inefficacy localization method that is used for the power metal-oxide transistor chip of the present invention comprises step:
(1) to the aluminium lamination of VMOS chip (shown in Fig. 3-4) with watery hydrochloric acid (is 20% like mass concentration) or dilute sulfuric acid removal VMOS chip surface, i.e. the whole corrosion of aluminium lamination when the surface promptly stop, and this can guarantee only to remove aluminum metal layer; Wherein, the master who removes the VMOS chip behind the aluminium lamination looks synoptic diagram and schematic top plan view respectively like Fig. 5, shown in Figure 6, and this chip surface can be seen transistorized part pattern.
(2) for the VMOS chip of dissimilar removal surface aluminium laminations, adopt following method:
A, for the VMOS chip of the removal surface aluminium lamination that contains the Ti/TiN diffusion impervious layer under the aluminium lamination
After aluminium lamination is removed; Harmless, that homogeneous conductive is good fully Ti/TiN layer below exposing; Grid and source electrode still have metal complete but that thickness greatly reduces to draw layer, irritate through directly acupuncture treatment grid, source electrode, drain electrode that electric current is made EMMI or OBIRCH analyzes, and objective lens is amplified to maximum 100 times guarantees that defect location arrives the transistor rank; Orient this defective position; Its result such as Fig. 7, shown in Figure 8 are close to the actual defects position from the luminous point that camera lens obtains, and can be accurate to the actual crystal pipe.
In this step, but because diffusion impervious layer still be a conductive layer, therefore, can be directly as the acupuncture treatment electrode use of subsequent analysis.Common Ti/TiN thickness is at the hundreds of dust, and its crystal grain is less, and density is lower, does not influence printing opacity, can directly analyze with EMMI; Be because the thin thickness of Ti/TiN equally, when the susceptibility of laser is much better than to have thick aluminium lamination, so that OBIRCH analyzes is also suitable.
B, for the following VMOS chip of the surperficial aluminium lamination of removal of no diffusion impervious layer of aluminium lamination
After aluminium lamination is removed, the oxide layer of insulation below exposing; No transistor area in chip is with the platinum pad of 50 microns of two 50 microns * of focused particle beam electron microscope (FIB) deposit, and these two platinum pads do not link together; Then on the limit of each platinum pad with one 1 micron wide of FIB deposit and the platinum bar that is connected with this metal gasket; The length of platinum bar is with the length that guarantees to have connected platinum pad and needed grid or source electrode be as the criterion (Fig. 9, shown in Figure 10); The platinum bar also is deposited on the no transistor area in the chip; And two platinum bars do not link together yet, and the other end of two bonding jumpers separate connection respectively arrives grid and source electrode.In this step, utilized circuit reparation and the voltage contrast imaging function of FIB.
VMOS chip for the removal of above-mentioned deposit platinum pad and platinum bar surface aluminium lamination; Utilize the drain electrode of two metal gaskets and chip back to accomplish EMMI or OBIRCH analysis (objective lens is amplified to maximum 100 times) again; Its result is shown in Figure 11-12; Be close to the actual defects position from the luminous point that camera lens obtains, and can orient the defective that is accurate to single transistor.
In sum; For the VMOS chip, adopt the little luminous point that goes out through EMMI or OBIRCH technological orientation of the present invention, be close to actual defects position (shown in Figure 13); And the luminous point of micron level, can be accurate to concrete certain unit (certain transistor) and locate (shown in Figure 14).And for same chip, the large tracts of land spot that adopts the liquid crystal analytical approach then can only obtain, this spot shows actual defects somewhere (shown in Figure 15) below spot, and can't confirm this actual defects position is specifically at which place, unit (shown in Figure 16).Therefore, effect of the present invention is better than the liquid crystal analysis far away, and can find defective locations quickly and accurately.
Claims (4)
1. defective inefficacy localization method that is used for the power metal-oxide transistor chip comprises step:
(1) removes the surperficial aluminium lamination of power metal-oxide transistor chip with acid;
(2) for the power metal-oxide transistor chip of dissimilar removal surface aluminium laminations, adopt following method:
A, for the chip that contains the Ti/TiN diffusion impervious layer under the aluminium lamination
Aluminium lamination exposes the Ti/TiN layer after removing, and grid and source electrode exist metal to draw layer, irritates electric current through the grid of directly having an acupuncture treatment, source electrode, drain electrode and makes light emission microscopic analysis technology or photic impedance variations technical Analysis, orients the defective that is accurate to single transistor;
B, for the following chip of no diffusion impervious layer of aluminium lamination
After aluminium lamination is removed, the oxide layer of insulation below exposing; No transistor area in chip is with two metal gaskets of focused particle beam electron microscope deposit; Again on the limit of each metal gasket with bonding jumper that is connected with this metal gasket of focused particle beam electron microscope deposit, the other end of two bonding jumpers respectively separate connection to grid and source electrode;
Utilize the drain electrode of two metal gaskets and chip back to accomplish light emission microscopic analysis technology or photic impedance variations technical Analysis, orient the defective that is accurate to single transistor.
2. the defective inefficacy localization method that is used for the power metal-oxide transistor chip as claimed in claim 1 is characterized in that: the acid in the said step (1) is epistasis and the acid of no fluorine element of oxidisability of not having, and comprising: hydrochloric acid, dilute sulfuric acid, phosphoric acid.
3. the defective inefficacy localization method that is used for the power metal-oxide transistor chip as claimed in claim 1; It is characterized in that: among said steps A, the B, the objective lens in light emission microscopic analysis technology or the photic impedance variations technical Analysis is amplified to 100 times and guarantees that defect location arrives the transistor rank.
4. the defective inefficacy localization method that is used for the power metal-oxide transistor chip as claimed in claim 1 is characterized in that: among the said step B, each metal gasket is that size is the platinum pad of 50 microns of 50 microns *;
It is 1 micron wide platinum bar that each bonding jumper is one, and length is to guarantee that the length that has connected platinum pad and needed grid or source electrode is as the criterion.
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| CN103367191A (en) * | 2013-07-03 | 2013-10-23 | 上海华力微电子有限公司 | Failpoint locating method |
| CN103965914A (en) * | 2013-01-25 | 2014-08-06 | 上海华虹宏力半导体制造有限公司 | Composition for etching NPN doped region morphology to carry out failure test, and test method |
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| CN107544012A (en) * | 2016-06-24 | 2018-01-05 | 上海北京大学微电子研究院 | Multichannel microscope semiconductor integrated test system |
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| CN106876296A (en) * | 2017-01-03 | 2017-06-20 | 航天科工防御技术研究试验中心 | A kind of semiconductor device failure localization method |
| CN107958849B (en) * | 2017-11-21 | 2019-12-10 | 上海华虹宏力半导体制造有限公司 | Method for positioning failure point of barrier-layer-free metal layer power device I GSS |
| CN107958849A (en) * | 2017-11-21 | 2018-04-24 | 上海华虹宏力半导体制造有限公司 | Without hindrance barrier metal layer power device IGSSFail independent positioning method |
| CN109342920A (en) * | 2018-09-30 | 2019-02-15 | 上海华力集成电路制造有限公司 | IC chip failure independent positioning method |
| CN111063388A (en) * | 2019-12-30 | 2020-04-24 | 长江存储科技有限责任公司 | Method for positioning failure point of memory |
| CN111063388B (en) * | 2019-12-30 | 2021-12-17 | 长江存储科技有限责任公司 | Method for positioning failure point of memory |
| CN111370347A (en) * | 2020-03-24 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Failure analysis method of power device |
| CN112033996A (en) * | 2020-08-17 | 2020-12-04 | 苏州和萃新材料有限公司 | Chip defect detection positioning system and application method thereof |
| CN112067652A (en) * | 2020-08-17 | 2020-12-11 | 苏州和萃新材料有限公司 | Chip defect detection positioning system and application method thereof |
| CN116106728A (en) * | 2023-04-13 | 2023-05-12 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Failure positioning method and device for MIM capacitor of GaAs integrated circuit |
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Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Free format text: CORRECT: APPLICANT; FROM: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI TO: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION |
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