CN102466778B - Failure positioning method for defects of power metal-oxide-semiconductor chip - Google Patents
Failure positioning method for defects of power metal-oxide-semiconductor chip Download PDFInfo
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Abstract
The invention discloses a failure positioning method for defects of a power metal-oxide-semiconductor chip, comprising steps of: 1) removing an aluminum layer on the surface of the power metal-oxide-semiconductor chip; and 2) as for the chip comprising a Ti/TiN diffusion impervious layer under the aluminum layer, perfusing current into grid, source and drain of the chip by directly inserting needles to perform EMMI (Emission Microscopy) or OBIRCH (Optical Beam Induced Resistance Change) analysis, and then positioning defects; and as for the chip comprising no diffusion impervious layer under the aluminum layer, depositing two metal pads by FIB (Focused Ion Beam) at an area free from transistors in the chip, further depositing a metal strip in connection with the metal pad at the edge of each metal pad by FIB, wherein the other ends of the two metal strips are respectively connected with the grid and the source, and completing EMMI or OBIRCH tests by using the two metal pads and the drain on the back of the chip, and then positioning the defects. The failure positioning method for the defects of the power metal-oxide-semiconductor chip has effect far better than liquid crystal analysis, and the defect positions can be rapidly and accurately found.
Description
Technical field
The present invention relates to a kind of failure positioning method of semi-conductor chip, particularly relate to a kind of defect failure localization method for power metal-oxide transistor (Power Metal-Oxide-Semiconductor, Power MOS) chip.
Background technology
In power metal-oxide transistor (Power MOS) chip common structure, tens thousand of above transistorized grids (polysilicon formation) are connected in parallel, chip back is drain electrode, chip front side is source electrode, by covering the band diffusion impervious layer [titanium nitride (TiN) of several micron thickness, hundreds of dust is thick] aluminium lamination and connect together, and for the needs of follow-up bonding, on aluminium lamination, large portion region no longer covers other materials (this condition is provided for enforcement of the present invention).Power MOS has a variety of structures, comprises VMOS (V-type groove MOS), UMOS, and DMOS etc., wherein, the master of VMOS chip looks schematic diagram and schematic top plan view is distinguished as shown in Figure 1 and Figure 2.
The process of chip failure analysis is first to find defect and then analyzing defect.Existing liquid crystal analysis (Liquid Crystal, LC) technology is that liquid crystal material is applied to the whole surface of chip, and then chip energising enters failure state, for electric leakage region, current density is maximum, the local heating producing is the most serious, and temperature rises, and then material embodies liquid crystal state at this temperature, solid-state lattice and liquid fluidity, use polarized light microscope observing again, can see spot shape image at fault location, so far defect location completes.But the problem that this defect positioning method exists is as follows:
1. require electric leakage larger, conventionally more than milliampere;
2. represent the spot shape image of defective locations, area is large (more than tens of square microns), usually can cover tens unit (or transistor), when this defect is during in micron dimension, such location is too coarse, and scope is too large, cannot complete follow-up physics microanalysis;
3. it can only locate large defect or the defect very serious to performance impact.
In addition, also have some technology to be applied to imaging, chip failure location, analysis for current leakage etc., specific as follows:
1. focused particle beam electron microscope (Focused Ion Beam, FIB)
This equipment or technology, clash into sample surfaces with the gallium positive ion beam after focusing on as incident particle (or being primary ions), can form secondary ion, secondary electron etc., then by collecting secondary electron imaging; Most common use has section fine cut, imaging (comprising voltage contrast picture), TEM sample preparation, circuit reparation (comprising perforate and metal cladding line) etc.
2. light is launched Microbeam Analysis Techniques (Emission Microscopy, EMMI)
What utilize is that (semiconductor is under all kinds of external worlds excite semiconductor light emitting principle, as electricity excites, electronics in being with or the different transmitting that has photon can interband generation transition time), by by specialized camera [as Si-CCD (Silicon-Charge Coupled Device, silicon charge-coupled image sensor) camera], photon is caught, obtain light emission analysis image, the material object picture stack of this image and chip, just can judge luminous particular location, the most serious position of leaking electricity exactly, this position.EMMI is suitable for the inefficacy location that junction leakage is relevant.Positioning precision can be depending on the camera lens of equipment, and to conventional model PHEMOS1000, enlargement ratio reaches 1000, and resolution is less than 1 micron.
3. photic impedance variation technology (Optical Beam Induced Resistance Change, OBIRCH)
By LASER HEATING, cause resistance variations, resistance variations causes curent change or change in voltage, and this changes can be by equipment records, and fault location resistance characteristic often changes more responsive, thereby orients defective locations.OBIRCH is suitable for the analysis for current leakage of Ohmic contact class.Positioning precision can be depending on the camera lens of equipment, and to conventional model PHEMOS1000, enlargement ratio reaches 1000, and resolution is less than 1 micron.
But for POWER MOS chip, an inner transistor leakage lost efficacy, chip global failure, and all tens thousand of above transistor arrangements are identical, and all covered by thick metal, thick metal layers possesses the highly reflective to light, the splendid heat conductivity to heat, to therefrom find defect or imperfect crystal pipe very difficult, and yet there is no at present good method.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of defect failure localization method for power metal-oxide transistor (PowerMOS) chip.The method, for the Power MOS chip that exists electric leakage to lose efficacy, can find the position of the defect that causes inefficacy fast, and be accurate to individual unit (or transistor) from tens thousand of above repetitives (or transistor).Just the physical analysis to defect be can pass through afterwards, failure cause and improvement method found.
For solving the problems of the technologies described above, the defect failure localization method for power metal-oxide transistor chip of the present invention, comprises step:
(1) with acid, remove aluminium (Al) layer on power metal-oxide transistor chip surface; Wherein, this acid is epistasis and the acid of free-floride (F) element of oxidisability of not having, and comprising: hydrochloric acid, dilute sulfuric acid, phosphoric acid etc.;
(2) for the power metal-oxide transistor chip of dissimilar removal surface aluminium lamination, adopt with the following method:
A, for the chip that contains Ti/TiN (titanium/titanium nitride) diffusion impervious layer under aluminium lamination
After aluminium lamination is removed, expose Ti/TiN layer, grid and source electrode exist metal to draw layer, warp directly acupuncture treatment grid, source electrode, drain electrode filling electric current is done light transmitting Microbeam Analysis Techniques (EMMI) or photic impedance variation technology (OBIRCH) analysis, objective lens is amplified to maximum 100 times and guarantees that defect location arrives transistor rank, orients the defect that is accurate to single transistor;
B, under aluminium lamination without the chip of diffusion impervious layer
Aluminium lamination exposes the oxide layer insulating below after removing; In chip without focused particle beam electron microscope (FIB) deposit two metal gaskets for transistor area, again on the limit of each metal gasket with bonding jumper being connected with this metal gasket of focused particle beam electron microscope deposit, the other end of two bonding jumpers is independently connected to respectively grid and source electrode;
Light is launched Microbeam Analysis Techniques (EMMI) or photic impedance variation technology (OBIRCH) is analyzed to utilize two metal gaskets and chip back to drain, objective lens is amplified to maximum 100 times and guarantees that defect location arrives transistor rank, orients the defect that is accurate to single transistor.
Each described metal gasket can be that size is the platinum pad of 50 microns * 50 microns, be positioned at chip without transistor area, and two platinum pads do not link together.
It is the platinum bar of 1 micron wide that each described bonding jumper can be one, and length is to guarantee that the length that has connected platinum pad and needed grid or drain electrode is as the criterion, be also deposited in chip without transistor area.
The present invention can locate defect or the fine defects of small electric leakage, can navigate to single transistor simultaneously, by first removing surperficial thick aluminium lamination, then utilize existing EMMI and OBIRCH defect location instrument, defect or imperfect crystal pipe are found out the transistor more than tens thousand of, for defective physical analysis below lays the first stone.Therefore, the present invention has following beneficial effect:
(1) speed is fast, and precision is high, and the application of the invention and physical analysis are subsequently found after failure cause, can help improve the problem existing in Power MOS explained hereafter or practical application, improves the quality of products, and produces great economic benefit;
(2) response low-carbon environment-friendly, can evade it has been generally acknowledged that slightly the liquid crystal of toxicity is used;
(3) from speed and qualitatively, be all far superior to liquid crystal analysis.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is that the master of VMOS chip looks schematic diagram;
Fig. 2 is the schematic top plan view of VMOS chip;
Fig. 3 is that the master of VMOS chip in embodiment looks schematic diagram;
Fig. 4 is the schematic top plan view of VMOS chip in embodiment;
Fig. 5 is that the master of the VMOS chip of surface removal aluminium lamination in embodiment looks schematic diagram;
Fig. 6 is the schematic top plan view of the VMOS chip of surface removal aluminium lamination in embodiment;
Fig. 7 looks schematic diagram with the result master of the VMOS chip after EMMI or OBIRCH lens analysis surface removal aluminium lamination in embodiment;
Fig. 8 is by the result schematic top plan view of the VMOS chip after EMMI or OBIRCH lens analysis surface removal aluminium lamination in embodiment;
Fig. 9 is that the master of VMOS chip of the removal surface aluminium lamination of deposit platinum pad and platinum bar in embodiment looks schematic diagram;
Figure 10 is the schematic top plan view of VMOS chip of the removal surface aluminium lamination of deposit platinum pad and platinum bar in embodiment;
Figure 11 is that in embodiment, the master with the VMOS chip of the removal surface aluminium lamination of EMMI or OBIRCH lens analysis deposit platinum pad and platinum bar looks schematic diagram;
Figure 12 is by the schematic top plan view of the VMOS chip of the removal surface aluminium lamination of EMMI or OBIRCH lens analysis deposit platinum pad and platinum bar in embodiment;
Figure 13 is to VMOS chip, adopts the result master who obtains after methods analyst of the present invention to look schematic diagram;
Figure 14 is to VMOS chip, adopts the result schematic top plan view obtaining after methods analyst of the present invention;
Figure 15 is to VMOS chip, with the result master who obtains after existing liquid crystal analytical, looks schematic diagram;
Figure 16 is to VMOS chip, by the result schematic top plan view obtaining after existing liquid crystal analytical.
Embodiment
In the present embodiment, take to VMOS chip defect inefficacy positioning analysis is example, and method of the present invention is described.Wherein, there is the aluminium lamination of several micron thickness in the surface of VMOS chip, and the master of this VMOS chip looks schematic diagram and diagrammatic top view is distinguished as shown in Figure 3, Figure 4.
In following examples, the model of the equipment camera lens applying in light transmitting Microbeam Analysis Techniques (EMMI) or photic impedance variation technology (OBIRCH) is PHEMOS100, purchased from Japanese Hamamatsu company.Wherein, using EMMI or OBIRCH technology is to be undertaken by the operation of existing routine.
Defect failure localization method for power metal-oxide transistor chip of the present invention, comprises step:
(1) aluminium lamination to watery hydrochloric acid for VMOS chip (shown in Fig. 3-4) (if mass concentration is 20%) or dilute sulfuric acid removal VMOS chip surface,, when the surperficial whole corrosion of aluminium lamination stop, this can guarantee only to remove aluminum metal layer; Wherein, the master of the VMOS chip after removal aluminium lamination looks schematic diagram and schematic top plan view is distinguished as shown in Figure 5, Figure 6, and this chip surface can be seen transistorized part pattern.
(2) for the VMOS chip of dissimilar removal surface aluminium lamination, adopt with the following method:
A, for the VMOS chip that contains the removal surface aluminium lamination of Ti/TiN diffusion impervious layer under aluminium lamination
After aluminium lamination is removed, expose completely harmless, that homogeneous conductive is good Ti/TiN layer below, grid and source electrode still have metal complete but that thickness greatly reduces to draw layer, through directly acupuncture treatment grid, source electrode, drain electrode filling electric current are done EMMI or OBIRCH analysis, objective lens is amplified to maximum 100 times and guarantees that defect location arrives transistor rank, orient this defect position, its result as shown in Figure 7, Figure 8, the luminous point obtaining from camera lens is close to actual defects position, and can be accurate to actual crystal pipe.
In this step, because diffusion impervious layer is still can conductive layer, therefore, can be directly as the acupuncture treatment electrode of subsequent analysis, use.Common Ti/TiN thickness is at hundreds of dust, and its crystal grain is less, and density is lower, does not affect printing opacity, can directly with EMMI, analyze; Because the thin thickness of Ti/TiN, when the susceptibility of laser is much better than to have thick aluminium lamination, is suitable for therefore OBIRCH analyzes also equally.
B, under aluminium lamination without the VMOS chip of the removal surface aluminium lamination of diffusion impervious layer
Aluminium lamination exposes the oxide layer insulating below after removing; The platinum pad with two 50 microns * 50 microns of focused particle beam electron microscope (FIB) deposits without transistor area in chip, these two platinum pads do not link together; Then on the limit of each platinum pad with one 1 micron wide of FIB deposit and the platinum bar that is connected with this metal gasket, the length of platinum bar is to guarantee the length that has connected platinum pad and needed grid or source electrode be as the criterion (shown in Fig. 9, Figure 10), platinum bar be also deposited in chip without transistor area, and two platinum bars do not link together yet, and the other end of two bonding jumpers is independently connected to respectively grid and source electrode.In this step, utilized circuit reparation and the voltage contrast imaging function of FIB.
VMOS chip for the removal surface aluminium lamination of above-mentioned deposit platinum pad and platinum bar, recycle drained EMMI or OBIRCH of two metal gaskets and chip back and analyze (objective lens is amplified to maximum 100 times), its result is as shown in Figure 11-12, the luminous point obtaining from camera lens is close to actual defects position, and can orient the defect that is accurate to single transistor.
In sum, for VMOS chip, adopt the little luminous point going out by EMMI or OBIRCH technological orientation of the present invention, be close to actual defects position (shown in Figure 13), and the luminous point of micron level, can be accurate to concrete certain unit (certain transistor) and locate (shown in Figure 14).And for same chip, adopt getable large area spot only of liquid crystal analytical approach, this spot shows actual defects below spot somewhere (shown in Figure 15), and cannot confirm this actual defects position is specifically at which place, unit (shown in Figure 16).Therefore, effect of the present invention is better than liquid crystal analysis far away, and can find quickly and accurately defective locations.
Claims (4)
1. for a defect failure localization method for power metal-oxide transistor chip, comprise step:
(1) with acid, remove the aluminium lamination on power metal-oxide transistor chip surface;
Wherein, described acid is epistasis and the acid without fluorine element of oxidisability of not having;
(2) for the power metal-oxide transistor chip of dissimilar removal surface aluminium lamination, adopt with the following method:
A, for the chip that contains Ti/TiN diffusion impervious layer under aluminium lamination
Aluminium lamination exposes Ti/TiN layer after removing, and grid and source electrode exist metal to draw layer, fills with electric current make light transmitting Microbeam Analysis Techniques or photic impedance variation technical Analysis through the grid of directly having an acupuncture treatment, source electrode, drain electrode, orients the defect that is accurate to single transistor;
B, under aluminium lamination without the chip of diffusion impervious layer
Aluminium lamination exposes the oxide layer insulating below after removing; In chip without focused particle beam electron microscope deposit two metal gaskets for transistor area, again on the limit of each metal gasket with bonding jumper being connected with this metal gasket of focused particle beam electron microscope deposit, the other end of two bonding jumpers is independently connected to respectively grid and source electrode;
Utilize two metal gaskets and chip back drained light transmitting Microbeam Analysis Techniques or photic impedance variation technical Analysis, orient the defect that is accurate to single transistor.
2. the defect failure localization method for power metal-oxide transistor chip as claimed in claim 1, is characterized in that: the acid in described step (1) comprises: hydrochloric acid, dilute sulfuric acid or phosphoric acid.
3. the defect failure localization method for power metal-oxide transistor chip as claimed in claim 1, it is characterized in that: in described method A, B, the objective lens in light transmitting Microbeam Analysis Techniques or photic impedance variation technical Analysis is amplified to 100 times and guarantees that defect location arrives transistor rank.
4. the defect failure localization method for power metal-oxide transistor chip as claimed in claim 1, is characterized in that: in described method B, each metal gasket is that size is the platinum pad of 50 microns * 50 microns;
It is the platinum bar of 1 micron wide that each bonding jumper is one, and length is to guarantee that the length that has connected platinum pad and needed grid or source electrode is as the criterion.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016149693A1 (en) * | 2015-03-19 | 2016-09-22 | Dcg Systems, Inc. | Particle beam heating to identify defects |
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| CN112067652A (en) * | 2020-08-17 | 2020-12-11 | 苏州和萃新材料有限公司 | Chip defect detection positioning system and application method thereof |
| CN112033996A (en) * | 2020-08-17 | 2020-12-04 | 苏州和萃新材料有限公司 | Chip defect detection positioning system and application method thereof |
| CN116106728B (en) * | 2023-04-13 | 2023-08-04 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Failure positioning method and device for MIM capacitor of GaAs integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1571135A (en) * | 1998-09-28 | 2005-01-26 | 恩益禧电子股份有限公司 | Device and method for nondestructive inspection on semiconductor device |
| CN1705889A (en) * | 2002-10-03 | 2005-12-07 | 应用材料以色列公司 | System and method for defect localization |
| CN101123245A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Testing structure for MOS capacitor and location method for failure point |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7042647B2 (en) * | 2003-10-02 | 2006-05-09 | Credence Systems Corporation | Scanning optical system |
| JP2005191249A (en) * | 2003-12-25 | 2005-07-14 | Semiconductor Leading Edge Technologies Inc | Teg wiring structure and semiconductor substrate |
| JP2009115459A (en) * | 2007-11-01 | 2009-05-28 | Sanyo Electric Co Ltd | Semiconductor element analyzer |
| JP2010002251A (en) * | 2008-06-19 | 2010-01-07 | Renesas Technology Corp | Failure analysis method of semiconductor device |
-
2010
- 2010-11-17 CN CN201010547545.6A patent/CN102466778B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1571135A (en) * | 1998-09-28 | 2005-01-26 | 恩益禧电子股份有限公司 | Device and method for nondestructive inspection on semiconductor device |
| CN1705889A (en) * | 2002-10-03 | 2005-12-07 | 应用材料以色列公司 | System and method for defect localization |
| CN101123245A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Testing structure for MOS capacitor and location method for failure point |
Non-Patent Citations (2)
| Title |
|---|
| JP特开2009-115459A 2009.05.28 |
| JP特开2010-2251A 2010.01.07 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016149693A1 (en) * | 2015-03-19 | 2016-09-22 | Dcg Systems, Inc. | Particle beam heating to identify defects |
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