CN106356312A - Testing and failure analysis method for packaged chip - Google Patents
Testing and failure analysis method for packaged chip Download PDFInfo
- Publication number
- CN106356312A CN106356312A CN201610817896.1A CN201610817896A CN106356312A CN 106356312 A CN106356312 A CN 106356312A CN 201610817896 A CN201610817896 A CN 201610817896A CN 106356312 A CN106356312 A CN 106356312A
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- China
- Prior art keywords
- encapsulation chip
- failure analysis
- chip
- tested
- failpoint
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Abstract
The invention provides a testing and failure analysis method for a packaged chip. One side of the packaged chip close to a gold ball is subjected to first grinding until the gold ball is exposed such that the packaged chip can be subjected to probe testing through the gold ball by using a detection plate; one side of the packaged chip close to a silicon substrate is subjected to second grinding until the silicon substrate is exposed such that a failure point of the packaged chip can be determined by means of infrared positioning; influence or damage of high temperature and chemical corrosion to the packaged chip in the prior art is avoided, and failure analysis for the packaged chip is more accurate and efficient.
Description
Technical field
The present invention relates to technical field of semiconductors and in particular to a kind of to encapsulation chip tested and failure analysis side
Method.
Background technology
Integrated circuit lost efficacy inevitable, with people to product quality and reliability during developing, produce and using
Property require continuous improvement, failure analysis work also seem more and more important, analyzed by chip failure, integrated electricity can be helped
Road designer find in defect in design, the mismatch of technological parameter or design and operation improper the problems such as.
The method of testing of traditional encapsulation chip mainly includes several steps: using the fuming nitric aicd heating encapsulation chip
The plastic cement of surrounding is got rid of；Encapsulation chip is glued and is tested with probe card on the glass sheet.
But, at least more than 150 degree, thermally sensitive sample is (as the envelope that isb is abnormal for the fuming nitric aicd temperature of heating
Cartridge chip) can recover normal at this temperature, so that follow-up positioning of concentrating on work at selected units cannot be carried out down.Meanwhile, being fuming of heating
Nitric acid also can corrode the copper conductor (nitric acid corrosion aluminum and copper) of aluminum pad (pad al) and lower floor while removing package casing, leads
Cause the probe in probe card too high with encapsulation chip contact resistance.
In addition, for the problem of encapsulation itself, the method using the fuming nitric aicd of heating is also inapplicable.
Therefore, need badly provide a kind of to encapsulation chip tested and failure analysis method.
Content of the invention
It is an object of the invention to provide a kind of to encapsulation chip tested and failure analysis method, it is to avoid high temperature and
Chemical attack, to the impact encapsulating chip or destruction, realizes the probe test of encapsulation chip.
For achieving the above object, the present invention provide a kind of to encapsulation chip tested and failure analysis method, comprising:
Described encapsulation chip is carried out grinding for the first time near the one side of gold goal, to exposing described gold goal；
Near the one side of silicon substrate, second grinding is carried out to described encapsulation chip, to exposing described silicon substrate；
By described gold goal and silicon substrate, described encapsulation chip is tested and failure analysis.
Optionally, described first time is ground to be ground with second and is cmp.
Optionally, the surface diameter of the gold goal exposing is not less than 3/4ths of described gold goal diameter.
Optionally, the surface of the gold goal exposing with diameter greater than 40um.
Optionally, after carrying out described first time grinding, the difference of height of described encapsulation chip surface is within 10um.
Optionally, after carrying out second grinding, also include: described silicon substrate is polished.
Optionally, described test includes probe test and infrared positioning.
Optionally, described probe test includes: the probe in probe card is contacted with the gold goal exposing, to described envelope
Cartridge chip carries out electrical measurement.
Optionally, described infrared positioning includes: chip energising will be encapsulated, logical on described silicon substrate using thermal infrared imager
Enter the failpoint that infrared ray determines encapsulation chip.
Optionally, after determining the abnormal failpoint of encapsulation chip of presence, also include determining a N/R encapsulation core
The failpoint of piece.
Optionally, N/R encapsulation chip is compared with the failpoint that there is abnormal encapsulation chip, exclusion weight
The failpoint closing, carries out failure analysis to there is remaining failpoint on abnormal encapsulation chip.
Compared with prior art, the present invention provide to encapsulation chip tested and failure analysis method, to encapsulation
Chip carries out grinding for the first time near the one side of gold goal, to exposing described gold goal, such that it is able to pass through gold goal using detecting plate
Probe test is carried out to described encapsulation chip；Near the one side of silicon substrate, second grinding is carried out to encapsulation chip, to exposing
Described silicon substrate, such that it is able to determine the failpoint of encapsulation chip, it is to avoid high in prior art using the method for infrared positioning
Gentle chemical attack, to the impact encapsulating chip or destruction, improves accuracy and the efficiency that encapsulation chip is carried out with failure analysis.
Brief description
Fig. 1 by one embodiment of the invention provided to encapsulation chip tested and failure analysis method flow process
Figure.
Fig. 2～3 are each step knot of provided encapsulation chip is tested of one embodiment of the invention and failure analysis
Structure schematic diagram.
The schematic diagram of the failpoint of the N/R encapsulation chip that Fig. 4 is provided by one embodiment of the invention.
The schematic diagram of the failpoint of the encapsulation chip of the presence exception that Fig. 5 is provided by one embodiment of the invention.
Specific embodiment
For making present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is done into one
Step explanation.Certainly the invention is not limited in this specific embodiment, general replacement well known to the skilled artisan in the art is also contained
Lid is within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, when describing present example in detail, for the ease of saying
Bright, schematic diagram not according to general ratio partial enlargement, not should to this as the present invention restriction.
The core concept of the present invention is: encapsulation chip is carried out grinding for the first time near the one side of gold goal, to exposing
State gold goal, such that it is able to probe test is carried out by gold goal to described encapsulation chip using detecting plate；To encapsulation chip near silicon
The one side of substrate carries out second grinding, to exposing described silicon substrate, determines envelope such that it is able to the method using infrared positioning
The failpoint of cartridge chip, it is to avoid the impact to encapsulation chip of prior art high temperature and chemical attack or destruction, improves to envelope
Cartridge chip carries out accuracy and the efficiency of failure analysis.
Refer to Fig. 1, its by one embodiment of the invention provided to encapsulation chip tested and failure analysis side
The flow chart of method.As shown in figure 1, the present invention propose a kind of to encapsulation chip tested and failure analysis method, including with
Lower step:
Described encapsulation chip is carried out grinding for the first time near the one side of gold goal, to exposing described gold goal；
Near the one side of silicon substrate, second grinding is carried out to described encapsulation chip, to exposing described silicon substrate；
By described gold goal and silicon substrate, described encapsulation chip is tested and failure analysis.
Fig. 2～3 are each step structural representation that in one embodiment of the invention, encapsulation chip is carried out with failure analysis, please join
Examine shown in Fig. 1, and combine Fig. 2～Fig. 3, describe in detail proposed by the present invention to encapsulation chip tested and failure analysis side
Method:
First, described encapsulation chip 10 is carried out grinding for the first time near the one side of gold goal, to exposing described gold goal 20,
As shown in Figure 2.
In the present embodiment, described first time is ground to cmp, and the method using cmp removes institute
State the encapsulating material near gold goal one side for the encapsulation chip 10, such as plastic cement, to exposing described gold goal 20.The gold goal 20 exposing
Surface diameter be not less than described gold goal 20 diameter 3/4ths it is preferred that the surface diameter of the gold goal exposing is more than
40um, such as 42um, 45um, 50um.After carrying out first time cmp, the difference of height on described encapsulation chip 10 surface
It is maintained within 10um, to ensure subsequently can touch each gold goal using probe during probe test simultaneously.
Secondly, near the one side of silicon substrate, second grinding is carried out to described encapsulation chip 10, serve as a contrast to exposing described silicon
Bottom 30, as shown in Figure 3.
Described encapsulation chip 10 near silicon substrate 30 near gold goal 20 while be relative two surface.Institute
Stating second grinding is also cmp, grinds away described encapsulation chip 10 near silicon using the method for cmp
The encapsulating material of the one side of substrate 30, such as plastic cement, to exposing described silicon substrate 30.Then, described silicon substrate 30 is carried out
Polishing it is ensured that the smoothness on described silicon substrate 30 surface, thus avoiding image quality when affecting subsequently to determine failpoint.
The present invention, using the method for cmp twice, removes the package material of described encapsulation chip 10 upper and lower surface
Material, exposes the gold goal 20 of upper surface and the silicon substrate 30 of lower surface, need not be using the method for high temperature and chemical attack, it is to avoid
Encapsulation chip is impacted or destroys, maintain the integrity of chip functions, thus improving the accuracy of subsequent failure analysis
And efficiency.
Finally, by described gold goal and silicon substrate, described encapsulation chip is tested and failure analysis, described test bag
Include probe test and infrared positioning.
Described probe test includes: the probe in probe card is contacted with the gold goal exposing, to described encapsulation chip
Carry out electrical measurement, obtain the signal of telecommunication of encapsulation chip internal, judge that described encapsulation chip whether there is with this abnormal.
Described infrared positioning includes: the encapsulation chip losing efficacy energising is led on described silicon substrate using thermal infrared imager
Enter the failpoint that infrared ray determines encapsulation chip.Specifically, by the encapsulation chip losing efficacy energising, have big near failpoint
Leakage current passes through, and the temperature of this segment chip can raise, and can find failpoint using thermal infrared imager, such that it is able to further
It is analyzed for failpoint.
Determine after there is the abnormal failpoint of encapsulation chip, also include determining a N/R envelope using said method
The failpoint of cartridge chip.N/R encapsulation chip is compared with the failpoint that there is abnormal encapsulation chip, exclusion weight
The failpoint closing, carrying out failure analysis to there is remaining failpoint on abnormal encapsulation chip, refer to shown in Fig. 4 and Fig. 5.
The schematic diagram of the failpoint of the N/R encapsulation chip that Fig. 4 is provided by one embodiment of the invention, Fig. 5 is implemented for the present invention one
The schematic diagram of the failpoint of encapsulation chip of the presence exception that example is provided.In the diagram, the failpoint of N/R encapsulation chip
In position 1, in Figure 5, the failpoint that there is abnormal encapsulation chip in position 1, position 2, position 3 and position 4, then excludes position
Putting 1 Null Spot, being analyzed with the failpoint on position 4 to there is position 2, position 3 on abnormal encapsulation chip.Can manage
Solution, is also not excluded for the situation that N/R encapsulation chip does not have failpoint, now on the encapsulation chip that there is exception
All failpoints be analyzed.
It should be noted that being tested and failure analysis has only related to probe survey to described encapsulation chip in the present embodiment
Examination and infrared positioning, obtain the signal of telecommunication of encapsulation chip internal by probe test, are determined using the method for infrared positioning and lose efficacy
The position of point, but failure analysis be confined to the method, for example, can also determine failpoint using the method that liquid crystal detects, will
The encapsulation chip energising lost efficacy, has big leakage current near failpoint and passes through, the temperature of this segment chip can raise, in core
Piece surface applies liquid crystal polarization sem observation, then can find failpoint, be analyzed such that it is able to be further directed to failpoint.When
So, for obvious failpoint on encapsulation chip, for example big vestige (sutrge mark), small crackle (micro
Crack), oxide layer comes off, and can directly position, for the failpoint that cannot observe under visual or microscope, Ke Yijia
Failpoint is found by thermal infrared imager or liquid crystal test after electricity.
After determining failpoint, failpoint can be carried out with electronics magnified sweep (sem) and energy spectrum analysiss (edx), to look for
Form to the pattern of failpoint and chemical element, as the foundation judging failure cause.Radium-shine cutting can also be carried out, swashed with micro-
Beam breakage circuit or chip upper strata specific region, carry out emmi detecting (low-light microscope), (radium-shine light beam lures for obirch application
Send out change in impedance value test) etc. method failure analysis is carried out to chip.
The present invention, by two surfaces encapsulating chip are carried out with cmp, removes the encapsulation of encapsulation chip surface
Material, exposes gold goal and silicon substrate, then encapsulation chip is tested and failure analysis, replaces of the prior art adding
The fuming nitric aicd of heat removes encapsulating material, can avoid the high temperature and chemical attack impact to sample or destruction such that it is able to adopt
Tested with the method for probe test, effectively failure analysis can be carried out to the sample of some encapsulation problems, such as to temperature
Degree is than more sensitive packaged sample.
In sum, the present invention provide to encapsulation chip tested and failure analysis method, to encapsulation chip lean on
The one side of nearly gold goal carries out grinding for the first time, to exposing described gold goal, such that it is able to pass through gold goal to described using detecting plate
Encapsulation chip carries out probe test；Near the one side of silicon substrate, second grinding is carried out to encapsulation chip, to exposing described silicon
Substrate, such that it is able to determine the failpoint of encapsulation chip, it is to avoid prior art high temperature and change using the method for infrared positioning
Learn the impact to encapsulation chip for the corrosion or destruction, improve accuracy and the efficiency that encapsulation chip is carried out with failure analysis.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention, this
Any change that the those of ordinary skill in bright field does according to the disclosure above content, modification, belong to the protection of claims
Scope.
Claims (11)
1. a kind of to encapsulation chip tested and failure analysis method it is characterised in that include:
Described encapsulation chip is carried out grinding for the first time near the one side of gold goal, to exposing described gold goal；
Near the one side of silicon substrate, second grinding is carried out to described encapsulation chip, to exposing described silicon substrate；
By described gold goal and silicon substrate, described encapsulation chip is tested and failure analysis.
2. as claimed in claim 1 encapsulation chip is tested and failure analysis method it is characterised in that described first
Secondary grinding is cmp with second grinding.
3. as claimed in claim 1 encapsulation chip tested and failure analysis method it is characterised in that exposing
The surface diameter of gold goal is not less than 3/4ths of described gold goal diameter.
4. as claimed in claim 3 encapsulation chip tested and failure analysis method it is characterised in that exposing
The surface diameter of gold goal is more than 40um.
5. as claimed in claim 1 encapsulation chip is tested and failure analysis method it is characterised in that carrying out described
After grinding for the first time, the difference of height of described encapsulation chip surface is within 10um.
6. as claimed in claim 1 encapsulation chip is tested and failure analysis method it is characterised in that carrying out second
After secondary grinding, also include: described silicon substrate is polished.
7. the method for encapsulation chip is tested as described in any one of claim 1～6 and failure analysis, its feature exists
In described test includes probe test and infrared positioning.
8. the method for encapsulation chip is tested as described in any one of claim 7 and failure analysis is it is characterised in that institute
State probe test to include: the probe in probe card is contacted with the gold goal exposing, carries out electricity survey to described encapsulation chip
Amount.
9. as claimed in claim 8 encapsulation chip is tested and failure analysis method it is characterised in that described infrared
Positioning includes: will encapsulate chip energising, and be passed through infrared ray using thermal infrared imager and determine encapsulation chip on described silicon substrate
Failpoint.
It is 10. as claimed in claim 9 that to encapsulating, chip is tested and the method for failure analysis is deposited it is characterised in that determining
After the failpoint of abnormal encapsulation chip, also include determining the failpoint of a N/R encapsulation chip.
11. as claimed in claim 10 encapsulation chip is tested and failure analysis method it is characterised in that will be as good as
Normal encapsulation chip is compared with the failpoint that there is abnormal encapsulation chip, and the failpoint that exclusion overlaps is abnormal to existing
Encapsulation chip on remaining failpoint carry out failure analysis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610817896.1A CN106356312A (en) | 2016-09-12 | 2016-09-12 | Testing and failure analysis method for packaged chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610817896.1A CN106356312A (en) | 2016-09-12 | 2016-09-12 | Testing and failure analysis method for packaged chip |
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| CN106356312A true CN106356312A (en) | 2017-01-25 |
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| CN201610817896.1A Pending CN106356312A (en) | 2016-09-12 | 2016-09-12 | Testing and failure analysis method for packaged chip |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105021970A (en) * | 2015-07-30 | 2015-11-04 | 厦门乾照光电股份有限公司 | LED failure analysis dissecting apparatus and dissecting method |
| CN109406555A (en) * | 2018-10-15 | 2019-03-01 | 上海华力微电子有限公司 | A kind of sample removes hierarchical method |
| CN110146803A (en) * | 2019-05-16 | 2019-08-20 | 长江存储科技有限责任公司 | Chip sample and its acquisition methods, test packaging body and forming method thereof |
| CN111665403A (en) * | 2020-04-29 | 2020-09-15 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Failure point positioning method, device and system for laminated electronic component |
| CN113466740A (en) * | 2021-07-07 | 2021-10-01 | 深圳市美信咨询有限公司 | Fault positioning method and fault positioning device |
| CN113514298A (en) * | 2021-06-23 | 2021-10-19 | 闳康技术检测(上海)有限公司 | Preparation method of chip detection sample with bare wafer back |
| CN114035029A (en) * | 2021-10-29 | 2022-02-11 | 上海华力集成电路制造有限公司 | Method and device for quickly positioning failure position of integrated circuit |
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| CN101769876A (en) * | 2008-12-29 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Method for carrying out failure analysis in semiconductor device |
| CN105206546A (en) * | 2015-09-10 | 2015-12-30 | 宜特(上海)检测技术有限公司 | Flip chip failure analysis method and preparation method of detection sample in electric property positioning |
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Patent Citations (2)
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| CN101769876A (en) * | 2008-12-29 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Method for carrying out failure analysis in semiconductor device |
| CN105206546A (en) * | 2015-09-10 | 2015-12-30 | 宜特(上海)检测技术有限公司 | Flip chip failure analysis method and preparation method of detection sample in electric property positioning |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105021970A (en) * | 2015-07-30 | 2015-11-04 | 厦门乾照光电股份有限公司 | LED failure analysis dissecting apparatus and dissecting method |
| CN109406555A (en) * | 2018-10-15 | 2019-03-01 | 上海华力微电子有限公司 | A kind of sample removes hierarchical method |
| CN110146803A (en) * | 2019-05-16 | 2019-08-20 | 长江存储科技有限责任公司 | Chip sample and its acquisition methods, test packaging body and forming method thereof |
| CN111665403A (en) * | 2020-04-29 | 2020-09-15 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Failure point positioning method, device and system for laminated electronic component |
| CN113514298A (en) * | 2021-06-23 | 2021-10-19 | 闳康技术检测(上海)有限公司 | Preparation method of chip detection sample with bare wafer back |
| CN113466740A (en) * | 2021-07-07 | 2021-10-01 | 深圳市美信咨询有限公司 | Fault positioning method and fault positioning device |
| CN114035029A (en) * | 2021-10-29 | 2022-02-11 | 上海华力集成电路制造有限公司 | Method and device for quickly positioning failure position of integrated circuit |
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Application publication date: 20170125 |