CN104037107A - Failure analysis method for through hole chain structure - Google Patents
Failure analysis method for through hole chain structure Download PDFInfo
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- CN104037107A CN104037107A CN201410253207.XA CN201410253207A CN104037107A CN 104037107 A CN104037107 A CN 104037107A CN 201410253207 A CN201410253207 A CN 201410253207A CN 104037107 A CN104037107 A CN 104037107A
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- sample
- contact electrode
- semiconductor substrate
- metal wire
- chain structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The invention discloses a failure analysis method for a through hole chain structure. The failure analysis method for the through hole chain structure includes that providing a sample to be analyzed, wherein the sample to be analyzed comprises a through hole chain structure, the through hole chain comprises a semiconductor substrate, a metal wire and a contact electrode located between the semiconductor substrate and the metal wire, and the semiconductor substrate is well electrically connected with the contact electrode; cutting the sample to enable the distance between one lateral surface of the cut sample and one side of the through hole chain to locate at 1 to 20 micrometers; grinding the plane of the cut sample till appearing the surface of the metal wire; depositing a metal layer at the sample surface, wherein the metal layer covers the surface of the metal wire; grounding the metal layer; placing the sample in a focused electronic beam, vertically cutting the sample in the direction parallel to the thickness direction of the semiconductor substrate, and removing the semiconductor substrate below the contact electrode to appear the bottom of the contact electrode; carrying out voltage contrast failure location analysis on the contact electrode and the metal wire from the bottom of the contact electrode.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of failure analysis method of via chain structure.
Background technology
In order to find as early as possible the technological problems in integrated circuit production process, different test structures is set on semiconductor chip, and for wafer acceptance test, (WAT) is tested arrives, once discovery test failure, will carry out failure analysis to confirm the processing step of problem, facilitate production line to make in time improvement.
Via chain (CT Chain) structure is a kind of very conventional test structure, for monitoring contact electrode and Semiconductor substrate, and contact resistance size between the metal wire of contact electrode and this contact electrode top.Please refer to Fig. 1, Semiconductor substrate 11, contact electrode 12 and metal wire 13 form via chain structure.If when via chain fracture, and the position of opening circuit is between Semiconductor substrate 11 and contact electrode 12, prior art adopts grinding technics that metal wire 13 is removed conventionally so, by using the method for voltage contrast (VC) to position, determine the position that fracture occurs between contact electrode 12 and Semiconductor substrate 11.If but the position that fracture occurs is between metal wire 13 and contact electrode 12, cannot carry out by the method for existing voltage contrast location and the analysis of defect.
Therefore, need a kind of failure analysis method of via chain structure, can be used in the failure analysis of the fracture between metal wire and contact electrode.
Summary of the invention
The problem that the present invention solves provides a kind of failure analysis method of via chain structure, can be used in the failure analysis of the fracture between metal wire and contact electrode.
For addressing the above problem, the failure analysis method of a kind of via chain structure of the present invention, comprising:
Sample to be analyzed is provided, in described sample to be analyzed, has via chain structure, described via chain comprises Semiconductor substrate, metal wire and the contact electrode between Semiconductor substrate and metal wire, is electrically connected good between described Semiconductor substrate and contact electrode;
Described sample is cut, and the side that makes the sample after cutting is 1-10 micron with the distance of the side that through hole links;
Sample after cutting is carried out to plane lapping to the surface of exposing metal wire;
At sample surfaces depositing metal layers, the surface of described metal level covering metal line;
By metal level ground connection;
Sample is put into focused beam, utilize along the direction of the thickness that is parallel to Semiconductor substrate sample is carried out to perpendicular cuts, the Semiconductor substrate that is positioned at contact electrode below is removed to the bottom of exposing contact electrode;
From the bottom of contact electrode, contact electrode and metal wire are carried out to voltage contrast inefficacy positioning analysis.
Alternatively, described ground connection is utilized laser ground connection or conductive tape ground connection.
Alternatively, described metal level utilizes gilding machine deposition.
Compared with prior art, the present invention has the following advantages:
The present invention by will metal wire the metal level of top deposition ground connection, and the substrate of contact electrode below is removed, contact electrode is exposed, thereby realized contact electrode bottom, contact electrode and metal wire are carried out to voltage contrast inefficacy positioning analysis.
Brief description of the drawings
Fig. 1 is the structural representation of via chain structure;
Fig. 2-Fig. 5 is the inefficacy methods analyst schematic diagram of the via chain structure of one embodiment of the invention;
Fig. 6-Fig. 9 is the plan structure schematic diagram of the Semiconductor substrate shown in Fig. 2-Fig. 5.
Embodiment
The problem that the present invention solves provides a kind of failure analysis method of via chain structure, can be used in the failure analysis of the fracture between metal wire and contact electrode.
For addressing the above problem, the failure analysis method of a kind of via chain structure of the present invention, comprising:
Sample to be analyzed is provided, in described sample to be analyzed, has via chain structure, described via chain comprises Semiconductor substrate, metal wire and the contact electrode between Semiconductor substrate and metal wire, is electrically connected good between described Semiconductor substrate and contact electrode;
Described sample is cut, and the side that makes the sample after cutting is 1-10 micron with the distance of the side that through hole links;
Sample after cutting is carried out to plane lapping to the surface of exposing metal wire;
At sample surfaces depositing metal layers, the surface of described metal level covering metal line;
By metal level ground connection;
Sample is put into focused beam, utilize along the direction of the thickness that is parallel to Semiconductor substrate sample is carried out to perpendicular cuts, the Semiconductor substrate that is positioned at contact electrode below is removed to the bottom of exposing contact electrode;
From the bottom of contact electrode, contact electrode and metal wire are carried out to voltage contrast inefficacy positioning analysis.
Below in conjunction with embodiment, technical scheme of the present invention is described in detail.For technical scheme of the present invention is better described, please refer to Fig. 2-Fig. 5 is the inefficacy methods analyst schematic diagram of the via chain structure of one embodiment of the invention.
First, please refer to Fig. 2 and in conjunction with Fig. 6, Fig. 6 is the Semiconductor substrate plan structure schematic diagram shown in Fig. 2.Sample 100 to be analyzed is provided, in described sample to be analyzed 100, there is via chain structure, described via chain comprises Semiconductor substrate 101, metal wire 103 and the contact electrode 102 between Semiconductor substrate 101 and metal wire 103, between described Semiconductor substrate 101 and contact electrode 102, be electrically connected well, do not find to have occurred to open circuit between Semiconductor substrate 101 and contact electrode 102 by analyzing.
Then, still with reference to figure 2 and in conjunction with Fig. 6, described sample 100 is cut, the side that makes the sample 100 after cutting is 1-10 micron with the distance B of the side that through hole links.The object of cutting is that a lateral extent of this side and sample is shortened, and is conducive to follow-up focused beam, from this side, sample is carried out to perpendicular cuts, and substrate 103 is removed the most at last, specifically will be described in detail follow-up.
Then, please refer to Fig. 3 and in conjunction with Fig. 7, Fig. 7 is the plan structure schematic diagram of the Semiconductor substrate shown in Fig. 3.Sample 100 after cutting is carried out to plane lapping to the surface of exposing metal wire 103.The described cmp that is ground to.
Then,, with reference to figure 4 and in conjunction with Fig. 8, Fig. 8 is the plan structure schematic diagram of the Semiconductor substrate shown in Fig. 4.On sample 100 surface deposition metal levels 104, the surface of described metal level 104 covering metal lines 103.Described metal level 104 utilizes gilding machine deposition.In Fig. 8, metal level 104 covers sample completely, thereby sample is owing to being positioned at metal level 104 belows, does not therefore illustrate in the drawings.
Then, continue with reference to figure 4 and Fig. 8, by metal level 104 ground connection; Described ground connection can be utilized laser ground connection or conductive tape ground connection.As an embodiment, described ground connection is utilized conductive tape ground connection.
Then,, with reference to figure 5 and in conjunction with Fig. 9, Fig. 9 is the plan structure schematic diagram of the Semiconductor substrate shown in Fig. 5.Sample 100 is put into focused beam (FIB), utilize along the direction of the thickness that is parallel to Semiconductor substrate 101 sample 100 is carried out to perpendicular cuts, the Semiconductor substrate 101 that is positioned at contact electrode 102 belows is removed, exposed the bottom of contact electrode 101.With reference to figure 9, wherein dotted portion is the part of having carried out perpendicular cuts, and follow-up inefficacy positioning analysis carries out the sample for this dotted portion.
Finally, from the bottom of contact electrode 101, contact electrode 101 and metal wire 103 are carried out to voltage contrast inefficacy positioning analysis, after utilizing inefficacy positioning analysis, can further utilize SEM or TEM method to carry out a step analysis to sample.
To sum up, the present invention by will metal level the conductive metal layer of top deposition ground connection, and the substrate of contact electrode below is removed, contact electrode is exposed, thereby realized contact electrode bottom, contact electrode and metal level are carried out to voltage contrast inefficacy positioning analysis.
Therefore, above-mentioned preferred embodiment is only explanation technical conceive of the present invention and feature, and its object is to allow person skilled in the art can understand content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalences that Spirit Essence is done according to the present invention change or modify, within all should being encompassed in protection scope of the present invention.
Claims (3)
1. the failure analysis method of a via chain structure, it is characterized in that, comprising: sample to be analyzed is provided, in described sample to be analyzed, there is via chain structure, described via chain comprises Semiconductor substrate, metal wire and the contact electrode between Semiconductor substrate and metal wire, describedly partly leads
Between body substrate and contact electrode, be electrically connected good;
Described sample is cut, and the side that makes the sample after cutting is 1-10 micron with the distance of the side that through hole links;
Sample after cutting is carried out to plane lapping to the surface of exposing metal wire;
At sample surfaces depositing metal layers, the surface of described metal level covering metal line;
By metal level ground connection;
Sample is put into focused beam, utilize along the direction of the thickness that is parallel to Semiconductor substrate sample is carried out to perpendicular cuts, the Semiconductor substrate that is positioned at contact electrode below is removed to the bottom of exposing contact electrode;
From the bottom of contact electrode, contact electrode and metal wire are carried out to voltage contrast inefficacy positioning analysis.
2. the failure analysis method of via chain structure as claimed in claim 1, is characterized in that, described ground connection is utilized laser ground connection or conductive tape ground connection.
3. the failure analysis method of via chain structure as claimed in claim 1, is characterized in that, described metal level utilizes gilding machine deposition.
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| CN201410253207.XA CN104037107B (en) | 2014-06-09 | 2014-06-09 | The failure analysis method of via chain structure |
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| CN201410253207.XA CN104037107B (en) | 2014-06-09 | 2014-06-09 | The failure analysis method of via chain structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990169A (en) * | 2015-01-28 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Detection method of chip through hole connection defects |
| CN106298579A (en) * | 2016-11-01 | 2017-01-04 | 武汉新芯集成电路制造有限公司 | The localization method that the via chain structure resistance of a kind of semiconductor chip is abnormal |
| CN109360770A (en) * | 2015-08-27 | 2019-02-19 | 马赛尔·P·霍夫萨埃斯 | Temperature detect switch (TDS) with cutting thorn |
| CN109686675A (en) * | 2018-12-12 | 2019-04-26 | 上海华力集成电路制造有限公司 | A kind of localization method of failure |
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| CN101226930A (en) * | 2007-01-15 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure with layer or structure identification mark and manufacturing method and application thereof |
| CN102339815A (en) * | 2010-07-15 | 2012-02-01 | 中芯国际集成电路制造(上海)有限公司 | Test structure for analyzing through-hole type metal-interconnected electromigration reliability |
| CN103576039A (en) * | 2012-07-20 | 2014-02-12 | 上海华虹Nec电子有限公司 | Method for finding open circuit at the top of connection hole |
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2014
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| JP2004335914A (en) * | 2003-05-12 | 2004-11-25 | Renesas Technology Corp | Semiconductor device |
| CN101226930A (en) * | 2007-01-15 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure with layer or structure identification mark and manufacturing method and application thereof |
| CN102339815A (en) * | 2010-07-15 | 2012-02-01 | 中芯国际集成电路制造(上海)有限公司 | Test structure for analyzing through-hole type metal-interconnected electromigration reliability |
| CN103576039A (en) * | 2012-07-20 | 2014-02-12 | 上海华虹Nec电子有限公司 | Method for finding open circuit at the top of connection hole |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990169A (en) * | 2015-01-28 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Detection method of chip through hole connection defects |
| CN105990169B (en) * | 2015-01-28 | 2019-01-08 | 中芯国际集成电路制造(上海)有限公司 | The detection method of chip through-hole connection defect |
| CN109360770A (en) * | 2015-08-27 | 2019-02-19 | 马赛尔·P·霍夫萨埃斯 | Temperature detect switch (TDS) with cutting thorn |
| CN109360770B (en) * | 2015-08-27 | 2020-03-10 | 马赛尔·P·霍夫萨埃斯 | Temperature control switch with cutting thorn |
| CN106298579A (en) * | 2016-11-01 | 2017-01-04 | 武汉新芯集成电路制造有限公司 | The localization method that the via chain structure resistance of a kind of semiconductor chip is abnormal |
| CN106298579B (en) * | 2016-11-01 | 2019-09-27 | 武汉新芯集成电路制造有限公司 | A kind of localization method of the through-hole chain structure resistance value exception of semiconductor chip |
| CN109686675A (en) * | 2018-12-12 | 2019-04-26 | 上海华力集成电路制造有限公司 | A kind of localization method of failure |
| CN109686675B (en) * | 2018-12-12 | 2020-09-18 | 上海华力集成电路制造有限公司 | Failure positioning method |
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| CN104037107B (en) | 2017-01-04 |
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