CN104319245A - Method for detecting potential of node inside chip - Google Patents
Method for detecting potential of node inside chip Download PDFInfo
- Publication number
- CN104319245A CN104319245A CN201410482675.4A CN201410482675A CN104319245A CN 104319245 A CN104319245 A CN 104319245A CN 201410482675 A CN201410482675 A CN 201410482675A CN 104319245 A CN104319245 A CN 104319245A
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- Prior art keywords
- chip
- sample chip
- pad
- sample
- current potential
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
The invention discloses a method for detecting the potential of a node inside a chip, comprising the following steps: selecting a sample chip and grinding the back of the sample chip to a target level; corroding the back of the sample chip by a chemical corrosion method until an insulation and isolation layer is exposed; passing through the insulation layer with a focused ion beam machine to etch out a connection pathway, filling the connection pathway with platinum metal, and forming a pad at the tail end of the connection pathway; transferring the sample chip to a manual testing machine, carrying out pre-needling on the pad with a probe having a ground potential, and releasing charges; and applying a corresponding test signal to the probe, testing the sample chip and detecting the change of a pad node signal. By adopting the method, potential detection can be carried out on multi-level metal interconnection from both the front and the back, and the level of chip failure analysis is improved.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, refer in a kind of Integrated circuit failure analysis especially, the method for detection chip internal node current potential.
Background technology
Along with the development of integrated circuit technique, the size of chip constantly reduces and performance improves constantly, and the level of chip also gets more and more.Be in research and development or fabrication stage at product, if there is exception, which partial circuit measurement internal node current potential distinguishes has exception to become very important.If measurement node is in the top layer of chip or close to top layer, FIB (focused ion beam) circuit production tie point is fairly simple; If measurement node is in the bottom of chip, intricate owing to connecting up, comparatively multi-level owing to will pass in manufacturing process, be very easily short-circuited, FIB becomes very difficult.
As shown in Figure 1, be the cutaway view of the metal interconnection layer of a sample chip, 1AL ~ 6AL represents different metal interconnection layers.The measurement node A of 6AL is positioned in figure, be positioned at the measurement node B of 5AL, and the measurement node C the being positioned at 4AL mode that all can grow pad by FIB carries out the monitoring of signal, but measurement node D, E and F, due to above it cover by 4AL, 5AL, 6AL metal interconnection layer on upper strata, if FIB downwards etching touch measurement node D, E and F, upper strata metal must be penetrated, so be short-circuited, measure and become meaningless.
Summary of the invention
Technical problem to be solved by this invention is a kind of method providing detection chip internal node current potential, realizes the potentiometric detection to chip internal low layer.
For solving the problem, the method for detection chip internal node current potential of the present invention, comprises following steps:
The first step, chooses sample chip, is ground to the hierarchy of objectivies to the back side of sample chip;
Second step, adopts the method for chemical corrosion to continue the back side of corrosion sample chip, exposes to dielectric isolation layer;
3rd step, adopts focused ion beam board, passes through insulating barrier and etch connecting path, and adopt platinum to fill, and forms pad at the end of connecting path;
4th step, is transferred to manual test board by sample chip, use the probe of earthing potential to have an acupuncture treatment in advance to pad, release electric charge;
5th step, applies corresponding test signal to probe, carries out the test of sample chip, detects the change of pad node signal.
Further, the sample chip of described the first to five step is packaged chip; If bare chip, first need encapsulate, carry out subsequent step more afterwards.
Further, the described first step, per sample chip thickness, corase grind falls 5 ~ 200 μm, retains 2 ~ 20 μm.
Further, described second step, dielectric isolation layer is preferably larger position, region, is greater than 10x10 μm
2.
Further, described 3rd step, platinum is filled and is adopted 1000pA line, and depth of cracking closure and sectional area are fixed with hole size; The length of platinum pad is 10 ~ 100 μm, and width is 10 ~ 100 μm, and thickness is 0.4 ~ 1 μm, and growth area is according to the area-optimized adjustment of insulation isolated area.
The method of detection chip internal node current potential of the present invention, adopt legacy equipment, by common process means such as corase grind, chemical corrosion, focused ion beam, realize the detection all can carrying out node potential to chip positive and negative, improve chip failure analysis level.
Accompanying drawing explanation
Fig. 1 is the cutaway view of multiple layer metal interconnection layer.
Fig. 2 is sample chip packaging body schematic diagram.
Fig. 3 is sample chip back side corase grind schematic diagram.
Fig. 4 is sample chip backside chemical corrosion schematic diagram.
Fig. 5 is sample chip back side focused ion beam process schematic representation.
Fig. 6 is that sample chip backside pads carries out pre-acupuncture treatment electric discharge schematic diagram.
Fig. 7 is the flow chart of steps of detection chip internal node current potential of the present invention.
Embodiment
The method of detection chip internal node current potential of the present invention, comprises following steps:
The first step, chooses sample chip, and sample chip is packaged chip, if bare chip, carries out subsequent step again after need first encapsulating.As shown in Figures 2 and 3, for the form not requirement of encapsulation, various encapsulation.Be ground to the hierarchy of objectivies to the back side of sample chip, per sample chip thickness, corase grind falls 5 ~ 200 μm, retains 2 ~ 20 μm.
Second step, adopts the method for chemical corrosion to continue the back side of corrosion sample chip, exposes to dielectric isolation layer; As shown in Figure 4 (for convenience of description, different from Fig. 2, Fig. 3,180 degree of upsets that sample chip is carried out by Fig. 4 make the back side of sample chip upward, same Fig. 5,6 also overturns), dielectric isolation layer has plenty of LOCOS (localized oxide), or STI, is limited to the tip dimensions of probe, preferably select the position that isolated area area is larger, generally all at 10x10 μm
2above.
3rd step, adopts focused ion beam board, passes through insulating barrier and etch connecting path, and adopt platinum to fill.Platinum is filled and is adopted 1000pA line, and depth of cracking closure and sectional area are fixed with hole size; Pad is formed at the end of through hole platinum.The length of platinum pad is 10 ~ 100 μm, and width is 10 ~ 100 μm, and thickness is 0.4 ~ 1 μm, as shown in Figure 5, and two pad corresponding measurement node D and F respectively in figure.Growth area is area-optimized according to insulation isolated area, and growth area can also suitably tune up by words as enough large in insulation isolated area area.
4th step, is transferred to manual test board by sample chip, owing to have accumulated more electric charge in the process of growth pad, therefore, first have an acupuncture treatment in advance to each pad with the probe of earthing potential, release electric charge, as shown in Figure 6.
5th step, applies corresponding test signal to probe, carries out the conventionally test of sample chip, detects the change of pad node signal.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. a method for detection chip internal node current potential, is characterized in that: comprise following steps:
The first step, chooses sample chip, is ground to the hierarchy of objectivies to the back side of sample chip;
Second step, adopts the method for chemical corrosion to continue the back side of corrosion sample chip, exposes to dielectric isolation layer;
3rd step, adopts focused ion beam board, passes through insulating barrier and etch connecting path, and adopt platinum to fill, and forms pad at the end of connecting path;
4th step, is transferred to manual test board by sample chip, use the probe of earthing potential to have an acupuncture treatment in advance to pad, release electric charge;
5th step, applies corresponding test signal to probe, carries out the test of sample chip, detects the change of pad node signal.
2. the method for detection chip internal node current potential as claimed in claim 1, is characterized in that: the sample chip of described the first to five step is packaged chip; If bare chip, first need encapsulate, carry out subsequent step more afterwards.
3. the method for detection chip internal node current potential as claimed in claim 1, is characterized in that: the described first step, per sample chip thickness, and corase grind falls 5 ~ 200 μm, retains 2 ~ 20 μm.
4. the method for detection chip internal node current potential as claimed in claim 1, it is characterized in that: described second step, dielectric isolation layer is preferably larger position, region, is greater than 10x10 μm
2.
5. the method for detection chip internal node current potential as claimed in claim 1, is characterized in that: described 3rd step, and platinum is filled and adopted 1000pA line, and depth of cracking closure and sectional area are fixed with hole size; The length of platinum pad is 10 ~ 100 μm, and width is 10 ~ 100 μm, and thickness is 0.4 ~ 1 μm, and growth area is according to the area-optimized adjustment of insulation isolated area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410482675.4A CN104319245A (en) | 2014-09-19 | 2014-09-19 | Method for detecting potential of node inside chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410482675.4A CN104319245A (en) | 2014-09-19 | 2014-09-19 | Method for detecting potential of node inside chip |
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| CN104319245A true CN104319245A (en) | 2015-01-28 |
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| CN201410482675.4A Pending CN104319245A (en) | 2014-09-19 | 2014-09-19 | Method for detecting potential of node inside chip |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206546A (en) * | 2015-09-10 | 2015-12-30 | 宜特(上海)检测技术有限公司 | Flip chip failure analysis method and preparation method of detection sample in electric property positioning |
| CN105301475A (en) * | 2015-09-22 | 2016-02-03 | 上海华虹宏力半导体制造有限公司 | Packaging chip back surface failure point locating method |
| CN105842611A (en) * | 2016-03-31 | 2016-08-10 | 工业和信息化部电子第五研究所 | Flip chip detection sample preparation method |
| CN106997856A (en) * | 2016-01-25 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | The sample treatment of wafer acceptability test is carried out for open-grid resistance |
| CN107564829A (en) * | 2017-08-24 | 2018-01-09 | 北京智芯微电子科技有限公司 | The method that internal signal for TSV encapsulation chips measures |
| CN112345336A (en) * | 2020-10-12 | 2021-02-09 | 上海华力集成电路制造有限公司 | Method for polishing back of ultra-small sample |
| TWI737548B (en) * | 2020-11-25 | 2021-08-21 | 華星光通科技股份有限公司 | Method for manufacturing a sample for observing failure areas in failure analysis |
| CN114236364A (en) * | 2022-02-24 | 2022-03-25 | 上海聚跃检测技术有限公司 | Failure analysis method and system for integrated circuit chip |
| CN115639460A (en) * | 2022-12-22 | 2023-01-24 | 北京紫光芯能科技有限公司 | Chip failure analysis method and device |
| CN115910919A (en) * | 2023-02-21 | 2023-04-04 | 上海聚跃检测技术有限公司 | Capacitance increasing method and capacitance increasing structure of integrated circuit chip |
| CN117291146A (en) * | 2023-11-24 | 2023-12-26 | 杭州广立微电子股份有限公司 | Test chip layout generation method, device and storage medium |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206546A (en) * | 2015-09-10 | 2015-12-30 | 宜特(上海)检测技术有限公司 | Flip chip failure analysis method and preparation method of detection sample in electric property positioning |
| CN105206546B (en) * | 2015-09-10 | 2017-11-21 | 宜特(上海)检测技术有限公司 | The preparation method of sample is detected in crystal covered chip failure analysis method and electrically positioning |
| CN105301475A (en) * | 2015-09-22 | 2016-02-03 | 上海华虹宏力半导体制造有限公司 | Packaging chip back surface failure point locating method |
| CN106997856A (en) * | 2016-01-25 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | The sample treatment of wafer acceptability test is carried out for open-grid resistance |
| CN105842611A (en) * | 2016-03-31 | 2016-08-10 | 工业和信息化部电子第五研究所 | Flip chip detection sample preparation method |
| CN107564829A (en) * | 2017-08-24 | 2018-01-09 | 北京智芯微电子科技有限公司 | The method that internal signal for TSV encapsulation chips measures |
| CN112345336A (en) * | 2020-10-12 | 2021-02-09 | 上海华力集成电路制造有限公司 | Method for polishing back of ultra-small sample |
| CN112345336B (en) * | 2020-10-12 | 2023-02-03 | 上海华力集成电路制造有限公司 | Method for polishing back of ultra-small sample |
| TWI737548B (en) * | 2020-11-25 | 2021-08-21 | 華星光通科技股份有限公司 | Method for manufacturing a sample for observing failure areas in failure analysis |
| CN114236364A (en) * | 2022-02-24 | 2022-03-25 | 上海聚跃检测技术有限公司 | Failure analysis method and system for integrated circuit chip |
| CN114236364B (en) * | 2022-02-24 | 2022-05-31 | 上海聚跃检测技术有限公司 | Failure analysis method and system for integrated circuit chip |
| CN115639460A (en) * | 2022-12-22 | 2023-01-24 | 北京紫光芯能科技有限公司 | Chip failure analysis method and device |
| CN115910919A (en) * | 2023-02-21 | 2023-04-04 | 上海聚跃检测技术有限公司 | Capacitance increasing method and capacitance increasing structure of integrated circuit chip |
| CN117291146A (en) * | 2023-11-24 | 2023-12-26 | 杭州广立微电子股份有限公司 | Test chip layout generation method, device and storage medium |
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Application publication date: 20150128 |