CN106997856A - The sample treatment of wafer acceptability test is carried out for open-grid resistance - Google Patents
The sample treatment of wafer acceptability test is carried out for open-grid resistance Download PDFInfo
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- CN106997856A CN106997856A CN201610048644.7A CN201610048644A CN106997856A CN 106997856 A CN106997856 A CN 106997856A CN 201610048644 A CN201610048644 A CN 201610048644A CN 106997856 A CN106997856 A CN 106997856A
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- testing sample
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of sample treatment that wafer acceptability test is carried out for open-grid resistance, and methods described includes：The front of testing sample is bonded together with support sample；The back side of testing sample is ground, until the thickness of the substrate of testing sample is 1 microns；Testing sample is handled using silicon etch solution until exposing the isolation structure being formed in the substrate.According to the present invention, the failure site that will not be destroyed in grid can more effectively obtain and analyze the information on the failure site in grid.
Description
Technical field
The present invention relates to the test of semiconductor devices, open-grid is directed in particular to one kind
Resistance carries out the sample treatment of wafer acceptability test (Wafer Acceptance Test).
Background technology
In manufacture of semiconductor, for the quality and stability on ensuring wafer to some extent, need
WAT tests are carried out to wafer.WAT tests are examined by the electrical parameter of test chip
Whether wafer has abnormal to ensure that chip is normal during manufacture, so as to avoid low yield
Occur.Another free-revving engine of WAT tests is come anti-by the electrical parameter of test chip
The problem of reflecting on production line, such as in terms of judging interconnection metal with the presence or absence of broken string, bridge joint
Problem, can be by the different pattern (Test to be measured of test wafer in WAT tests
Pattern) reflect which or a certain step have problem on production line.
WAT failure analyses for open-grid resistance, it is necessary to be located in advance to test sample
Reason, the sample after processing exposes contact etch stop layer or is formed at the silication of top portions of gates
Nitride layer.However, the control for sample pretreatment terminal is extremely difficult, it is easily destroyed in sample
There is the position of defect, even if the position for defect occur is not destroyed, once it is exposed, after
Continuing the Coating Materials needed for forming focused ion beam or transmission electron microscope observation can also fill out
Fill in sample and the position of defect occur, cause the decrease of feedback signal, and then influence the knot of observation
Really.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of brilliant for the progress of open-grid resistance
The sample treatment of circle acceptability test, including：
The front of testing sample is bonded together with support sample；Grind the testing sample
The back side, until the thickness of the substrate of the testing sample is 0.9 micron -1.1 microns；
The testing sample is handled using silicon etch solution to be formed in the substrate until exposing
Isolation structure.
In one example, the silicon etch solution is using nitric acid, hydrofluoric acid and deionized water system
Into solution, sodium hydroxide solution or potassium hydroxide solution.
In one example, after to testing sample processing, in addition to test sample is treated to described
The step of product are observed.
In one example, using SEM from the back side of the testing sample to institute
The internal observation of testing sample is stated to find out the grid in failure state.
In one example, using focusing on electron beam or transmission electron microscope from described to be measured
Failure site in grid described in the cross-section analysis of sample.
In one example, the isolation structure is fleet plough groove isolation structure or selective oxidation silicon
Isolation structure.
In one example, the step of forming the fleet plough groove isolation structure includes：In the base
Hard mask layer is formed on bottom；The hard mask layer is patterned, to be formed in the hard mask layer
Constitute the opening of the fleet plough groove isolation structure pattern；Hard mask layer using the patterning is covers
Film, etches the groove for forming the fleet plough groove isolation structure in the substrate；Institute
State in groove and depositing isolation material on the hard mask layer；Perform chemical mechanical milling tech
To grind the isolated material, until exposing the hard mask layer.
In one example, the deposition of the isolated material is completed several times, is formed each time
The composition of isolated material be identical.
In one example, after the deposition of the isolated material, annealing is performed, so that shape
Into the isolated material densification.
In one example, after the grinding, another annealing is performed, to repair the base
The damage at bottom, improves the interfacial characteristics between the fleet plough groove isolation structure and the substrate.
According to the present invention, the failure site that will not be destroyed in grid can be obtained more effectively
Information with analysis on the failure site in grid.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 is the method according to exemplary embodiment of the present to entering for open-grid resistance
The schematic diagram that the sample of row wafer acceptability test is handled；
Fig. 2 is flow the step of implementation successively according to the method for exemplary embodiment of the present
Figure.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and it will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, element, the presence or addition of part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
WAT failure analyses for open-grid resistance, it is necessary to be located in advance to test sample
Reason, the sample after processing exposes contact etch stop layer or is formed at the silication of top portions of gates
Nitride layer.However, the control for sample pretreatment terminal is extremely difficult, it is easily destroyed in sample
There is the position of defect, even if the position for defect occur is not destroyed, once it is exposed, after
Continuing the Coating Materials needed for forming focused ion beam or transmission electron microscope observation can also fill out
Fill in sample and the position of defect occur, cause the decrease of feedback signal, and then influence the knot of observation
Really.
In order to solve the above problems, as shown in Fig. 2 treating test sample the invention provides one kind processing
The method of product, this method includes：
In step 201, the front of testing sample is bonded together with support sample；
In step 202., the back side of testing sample is ground, until the thickness of the substrate of testing sample
Spend for 1 microns；
In step 203, handle testing sample using silicon etch solution and be formed at substrate until exposing
In isolation structure.
According to the method for processing testing sample proposed by the present invention, the failure that will not be destroyed in grid
Position, can more effectively obtain and analyze the information on the failure site in grid.
In order to thoroughly understand the present invention, will be proposed in following description detailed structure and/or
Step, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is retouched in detail
State it is as follows, but except these detailed description in addition to, the present invention can also have other embodiment.
[exemplary embodiment]
WAT failure analyses for open-grid resistance, it is necessary to be located in advance to test sample
Reason, it is common practice to grind the front of testing sample, until exposing contact etch stop layer
Or it is formed at the silicide layer of top portions of gates.The shortcoming of this processing method is to be easily destroyed
There is the position of defect, even if the position for defect occur is not destroyed, once it is exposed, after
Continuing the Coating Materials needed for forming focused ion beam or transmission electron microscope observation can also fill out
Fill in sample and the position of defect occur, cause the decrease of feedback signal, and then influence the knot of observation
Really.
Therefore, the present invention proposes a kind of method pre-processed to test sample, such as Fig. 1 institutes
Show, the front of testing sample 101 is bonded together with support sample 102, ground to be measured
The back side of sample 101, until the thickness of the substrate of testing sample 101 is 1 microns, example
Such as 0.9 micron -1.1 microns.
Then, (for example it is made using silicon etch solution using nitric acid, hydrofluoric acid and deionized water
Solution, sodium hydroxide solution or potassium hydroxide solution) testing sample 101 is handled until exposing
The isolation structure in substrate is formed at, so that the backside surface of the testing sample 101 after processing is put down
It is whole.
According to the method proposed by the present invention pre-processed to test sample, grid will not be destroyed
In failure site, can more effectively obtain and analyze the letter on the failpoint in grid
Breath.
Next, starting to be observed test sample, comprise the following steps that：Use scanning electricity
Sub- microscope is from the back side of testing sample 101 to the internal observation of testing sample 101 with from finding out
In the grid of failure state；Using focused ion beam or transmission electron microscope from testing sample
101 section (section obtained along the direction perpendicular to the surface of testing sample 101) point
The failure site in grid is analysed, confirmation causes having its source in for failure site to be formed in substrate
Air blister defect capture impurity in interlayer dielectric layer, impurity corrosion is positioned at top portions of gates
Silicide and grid, so as to form the defect in such as cavity etc, cause the failure of grid.
It should be noted that testing sample 101 includes substrate, the constituent material of the substrate can
With using undoped with monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI),
Silicon (SSOI), stacking SiGe (S-SiGeOI), insulator on insulator are laminated on insulator
Upper SiGe (SiGeOI) and germanium on insulator (GeOI) etc..
Isolation structure and various traps (well) structure are formed with the substrate, as showing
Example, the isolation structure is that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS)
Isolation structure.
By taking fleet plough groove isolation structure as an example, hard mask layer is first formed on the substrate, using this
The various suitable technologies that art personnel are familiar with form the hard mask layer, for example
Chemical vapor deposition method, the preferred silicon nitride of material of the hard mask layer.
Pattern the hard mask layer again, with the hard mask layer formed constituted shallow trench every
From the opening of structure plan, the process includes：Being formed on the hard mask layer has shallow trench
The photoresist layer of isolation structure pattern, using the photoresist layer as mask, etches the hard mask
Layer is until expose the substrate, using the cineration technics removal photoresist layer.
Then, using the hard mask layer of the patterning as mask, use is etched in the substrate
In the groove for forming fleet plough groove isolation structure.Then, in the trench and on hard mask layer
Depositing isolation material, the isolated material is usually oxide, preferably HARP.Next,
Chemical mechanical milling tech is performed to grind the isolated material, until exposing the hard mask
Layer.
In above process, in order to ensure realizing that the zero-clearance of isolated material is filled out in the trench
Fill, (being usually three times) completes the deposition of the isolated material several times, is formed each time
The composition of isolated material be identical.After said deposition, annealing is performed, so as to be formed
Isolated material densification, lift its mechanical strength.After the grinding, another move back is performed
Fire, to repair damage of the said process to the substrate, improve fleet plough groove isolation structure with it is described
Interfacial characteristics between substrate.
It should be noted that in the examples described above, being formed before the hard mask layer, Ke Yixian
One layer of oxide thin layer thing is formed as cushion, with discharge the hard mask layer and the substrate it
Between stress；Before depositing the isolated material, on the hard mask layer and for being formed
The side wall of the groove of fleet plough groove isolation structure and bottom form another oxide thin layer thing and constitute lining
Layer.
Grid structure is formed with the substrate, as an example, the grid structure is included certainly
Gate dielectric, gate material layers and the grid hard masking layer of lower and upper stacking.
Gate dielectric includes oxide skin(coating), such as silica (SiO2) layer.Grid material
Layer includes polysilicon layer, and grid hard masking layer includes oxide skin(coating), nitride layer, nitrogen oxides
One or more in layer and amorphous carbon, wherein, the constituent material of oxide skin(coating) includes boron phosphorus
Silica glass (BPSG), phosphorosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped with
Silica glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin coating
Dielectric (SOD), nitride layer includes silicon nitride (Si3N4) layer, oxynitride layer includes
Silicon oxynitride (SiON) layer.
The side wall construction against the grid structure is formed with the grid structure both sides, it is described
Side wall construction is made up of oxide, nitride or combination；Between the side wall construction
Substrate in be formed with embedded germanium silicon layer and embedded carbon silicon layer, as a rule, embedded carbon
The U-shaped profile of silicon layer, the cross section of embedded germanium silicon layer is in ∑ shape, further to increase
The carrier mobility of strong channel region.
The grid structure top and the top of the embedded germanium silicon layer and embedded carbon silicon layer
Portion is formed with metal silicide, as an example, the composition of metal silicide can be Ni
PtSiGeC, NiPtSiC etc..
As an example, forming the processing step of the metal silicide includes：
Metal level is initially formed, to cover the substrate, the side wall construction and the grid knot
The top of structure, the technique for forming the metal level can be using method conventional in the art, example
Such as, physical vaporous deposition or vapour deposition method etc., the thickness of the metal level can be 50-300
Angstrom, meanwhile, protective layer can be formed on the metal level, the material of the protective layer can be
The nitride of refractory metal, such as TiN, the effect of the protective layer are to avoid the metal level
Aoxidized exposed to the environment of non-inert, the thickness of the protective layer can be 50-200
Angstrom.
The metal level is annealed using low-temperature rapid thermal annealing (RTA) technique again, institute
The temperature for stating low-temperature rapid thermal annealing can be 200-350 DEG C, by annealing, the gold
Category layer in material spread into the silicon materials of the substrate and grid structure, and with the silicon material
Material reacts and forms metal silicide.
Finally, the metal silicide of formation is entered using high-temperature quick thermal annealing (RTA) technique
Row annealing, the temperature of the high-temperature quick thermal annealing can be 300-600 DEG C.
Cover the layer from bottom to top of the substrate, grid structure, side wall construction and metal silicide
Folded contact etch stop layer and interlayer dielectric layer.The material of the contact etch stop layer
Silicon nitride (SiN) may be selected, the material of the interlayer dielectric layer may be selected have low-k
The material of (dielectric constant is less than 4.0).
Confirm to cause the having its source in for grid failure to be formed at the base by aforementioned observed
There is air blister defect in the interlayer dielectric layer on bottom, air blister defect capture impurity, the impurity
Corrosion again is located at the metal silicide and the grid of the top portions of gates, so as to form such as empty
The defect in hole etc, causes the failure of the grid.
The process conditions of the interlayer dielectric layer, the interlayer that can be avoided the formation of are formed by improving
There is air blister defect in dielectric layer, and then eliminate the inducement for causing the grid failure.As an example,
Can be by strengthening before depositing the interlayer dielectric layer to the prerinse of the substrate and right
Implement further control of cleaning condition of the operating room of the deposition of the interlayer dielectric layer etc. to arrange
There is air blister defect in the interlayer dielectric layer for applying to avoid the formation of.
The making of whole semiconductor devices can be completed by subsequent technique, including：In the layer
Between dielectric layer formation contact hole, expose the metal silicide；Fill metal (being usually tungsten)
In the contact hole, to form the interconnecting metal layer and the metal silication that connection is subsequently formed
The contact plug of thing；Multiple interconnecting metal layers are formed, are generally completed using dual damascene process；
Form metal pad, wire bonding when being encapsulated for subsequent implementation device.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of sample treatment side that wafer acceptability test is carried out for open-grid resistance
Method, it is characterised in that including：
The front of testing sample is bonded together with support sample；
The back side of the testing sample is ground, until the thickness of the substrate of the testing sample is
0.9 micron -1.1 microns；
The testing sample is handled using silicon etch solution to be formed in the substrate until exposing
Isolation structure.
2. according to the method described in claim 1, it is characterised in that the silicon etch solution is
Solution, sodium hydroxide solution or the potassium hydroxide being made using nitric acid, hydrofluoric acid and deionized water
Solution.
3. according to the method described in claim 1, it is characterised in that to the testing sample
After processing, in addition to the step of be observed to the testing sample.
4. method according to claim 3, it is characterised in that shown using scanning electron
Micro mirror is in from the back side of the testing sample to the internal observation of the testing sample with finding out
The grid of failure state.
5. method according to claim 4, it is characterised in that use focusing electron beam
Or transmission electron microscope is from the failure in grid described in the cross-section analysis of the testing sample
Position.
6. according to the method described in claim 1, it is characterised in that the isolation structure is
Fleet plough groove isolation structure or selective oxidation silicon seperate structure.
7. method according to claim 6, it is characterised in that form the shallow trench
The step of isolation structure, includes：Hard mask layer is formed on the substrate；Patterning is described to be covered firmly
Film layer, opening for the fleet plough groove isolation structure pattern is constituted to be formed in the hard mask layer
Mouthful；Using the hard mask layer of the patterning as mask, etched in the substrate for being formed
The groove of the fleet plough groove isolation structure；Deposit in the trench and on the hard mask layer
Isolated material；Chemical mechanical milling tech is performed to grind the isolated material, until exposing institute
State hard mask layer.
8. method according to claim 7, it is characterised in that the isolated material
Deposition is completed several times, and the composition of the isolated material formed each time is identical.
9. method according to claim 7, it is characterised in that in the isolated material
Deposition after, perform annealing so that formed the isolated material densification.
10. method according to claim 7, it is characterised in that after the grinding,
Perform another annealing, to repair the damage of the substrate, improve the fleet plough groove isolation structure and
Interfacial characteristics between the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610048644.7A CN106997856B (en) | 2016-01-25 | 2016-01-25 | Sample processing method for wafer acceptability test aiming at grid open-circuit resistance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610048644.7A CN106997856B (en) | 2016-01-25 | 2016-01-25 | Sample processing method for wafer acceptability test aiming at grid open-circuit resistance |
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| CN106997856B CN106997856B (en) | 2020-03-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114720842A (en) * | 2022-06-08 | 2022-07-08 | 合肥新晶集成电路有限公司 | Preparation method of failure analysis structure and failure analysis method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0468550A (en) * | 1990-07-09 | 1992-03-04 | Fujitsu Ltd | Failure analysis of semiconductor device |
| JP2008004897A (en) * | 2006-06-26 | 2008-01-10 | Toshiba Corp | Manufacturing method for semiconductor device |
| JP2008177342A (en) * | 2007-01-18 | 2008-07-31 | Nikon Corp | Imaging device, alignment method, and alignment device |
| CN102044461A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Detection method used for failure analysis of semiconductor device |
| CN102253325A (en) * | 2010-05-21 | 2011-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN104319245A (en) * | 2014-09-19 | 2015-01-28 | 上海华虹宏力半导体制造有限公司 | Method for detecting potential of node inside chip |
| CN104810239A (en) * | 2014-01-23 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of spreading resistance test sample |
-
2016
- 2016-01-25 CN CN201610048644.7A patent/CN106997856B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0468550A (en) * | 1990-07-09 | 1992-03-04 | Fujitsu Ltd | Failure analysis of semiconductor device |
| JP2008004897A (en) * | 2006-06-26 | 2008-01-10 | Toshiba Corp | Manufacturing method for semiconductor device |
| JP2008177342A (en) * | 2007-01-18 | 2008-07-31 | Nikon Corp | Imaging device, alignment method, and alignment device |
| CN102044461A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Detection method used for failure analysis of semiconductor device |
| CN102253325A (en) * | 2010-05-21 | 2011-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN104810239A (en) * | 2014-01-23 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of spreading resistance test sample |
| CN104319245A (en) * | 2014-09-19 | 2015-01-28 | 上海华虹宏力半导体制造有限公司 | Method for detecting potential of node inside chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114720842A (en) * | 2022-06-08 | 2022-07-08 | 合肥新晶集成电路有限公司 | Preparation method of failure analysis structure and failure analysis method |
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| CN106997856B (en) | 2020-03-10 |
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