CN114720842A - Preparation method of failure analysis structure and failure analysis method - Google Patents
Preparation method of failure analysis structure and failure analysis method Download PDFInfo
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- CN114720842A CN114720842A CN202210639068.9A CN202210639068A CN114720842A CN 114720842 A CN114720842 A CN 114720842A CN 202210639068 A CN202210639068 A CN 202210639068A CN 114720842 A CN114720842 A CN 114720842A
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- 238000002360 preparation method Methods 0.000 title abstract description 18
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/32—Polishing; Etching
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- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
- G01N23/2202—Preparing specimens therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
- G01N23/225—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion
- G01N23/2251—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion using incident electron beams, e.g. scanning electron microscopy [SEM]
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Abstract
The invention relates to a preparation method of a failure analysis structure and a failure analysis method. The preparation method of the failure analysis structure comprises the following steps: providing a sample to be analyzed, wherein the sample to be analyzed comprises a chip to be analyzed and a bearing substrate, and the bearing substrate is positioned on the front surface of the chip to be analyzed; providing a bottom plate; the sample to be analyzed is attached to the bottom plate, and the back surface of the chip to be analyzed faces the bottom plate; forming a protective layer, wherein the protective layer at least covers the side wall of the chip to be analyzed; and removing the bearing substrate by using an etching solution. According to the preparation method of the failure analysis structure, no complex equipment such as an ion etcher is needed in the process of removing the bearing substrate, the operation is convenient, corrosive gases such as chlorine are not used, and the chip to be analyzed cannot be corroded and damaged; and the protective layer is formed to at least cover the side wall of the chip to be analyzed, so that the side wall of the chip is not damaged in the process of removing the bearing substrate, and further, the information and the positioning pattern of the chip are not damaged, so that the information of the chip is confirmed in the following process.
Description
Technical Field
The application relates to the technical field of semiconductor chip failure analysis, in particular to a preparation method of a failure analysis structure and a failure analysis method.
Background
With the development of semiconductor technology, a layer of bearing base is formed on the surface of a back-illuminated chip product in the process flow, so that the substrate can be thinned conveniently. And then, for the failure analysis of the back-illuminated chip, the sample preparation is required, so that the bearing substrate on the front surface of the chip needs to be removed.
At present, one method for removing the bearing substrate is to strip the bearing substrate by an inductively coupled plasma reactive ion etching machine, but the method has high requirements on equipment, the reaction gases mainly comprise chlorine and sulfur fluoride, the two gases are easy to leak and have corrosivity, the experimental risk is high, and the requirements on the equipment environment are high. Another method is to remove the carrier substrate by sanding, but this method is prone to damage to the edge of the chip, because the chip's identification information and positioning pattern are usually at the edge, and this method is not suitable for samples with target areas at the edge, nor is it advantageous to identify the sample number and position the sample when no sample information is known.
Disclosure of Invention
In view of the above, it is necessary to provide a method for manufacturing a failure analysis structure and a failure analysis method.
In order to achieve the above object, in one aspect, the present invention provides a method for manufacturing a failure analysis structure, including:
providing a sample to be analyzed, wherein the sample to be analyzed comprises a chip to be analyzed and a bearing substrate, and the bearing substrate is positioned on the front surface of the chip to be analyzed;
providing a bottom plate;
attaching the sample to be analyzed to the bottom plate, wherein the back surface of the chip to be analyzed faces the bottom plate;
forming a protective layer, wherein the protective layer at least covers the side wall of the chip to be analyzed;
and removing the bearing substrate by using an etching solution.
According to the preparation method of the failure analysis structure, the sample to be analyzed is attached to the bottom plate, the back surface of the chip to be analyzed of the sample to be analyzed faces the bottom plate, the bearing substrate is positioned on the front surface of the chip to be analyzed, the protective layer at least covers the side wall of the chip to be analyzed, and then the bearing substrate is removed by using the corrosive liquid, so that complex equipment such as an ion etching machine is not needed in the whole preparation process, the operation is simple and convenient, corrosive gases such as chlorine and the like are not used, and the chip to be analyzed cannot be corroded and damaged; and the protective layer is formed to at least cover the side wall of the chip to be analyzed, so that the side wall of the chip is not damaged in the process of removing the bearing substrate, and further, the information and the positioning pattern of the chip are not damaged, so that the information of the chip is confirmed in the following process.
In one embodiment, the chip to be analyzed comprises a back-illuminated image sensor chip.
In one embodiment, the area of the bottom plate is larger than the area of the chip to be analyzed; after providing the bottom plate, before attaching the sample to be analyzed on the bottom plate, the method further comprises:
and forming a protective layer on the upper surface of the bottom plate, wherein the protective layer covers the upper surface of the bottom plate.
In one embodiment, the attaching the sample to be analyzed to the base plate includes:
coating a hot melt adhesive layer on the upper surface of the bottom plate to serve as the protective layer;
and attaching the sample to be analyzed to the upper surface of the protective layer, wherein the back surface of the chip to be analyzed is in contact with the protective layer.
In one embodiment, after the removing the carrier substrate with the etching solution, the method further includes:
and removing the exposed protective layer and the protective layer.
In one embodiment, the forming a protective layer, the protective layer covering at least a sidewall of the chip to be analyzed, includes:
forming a first protective layer on the side wall of the chip to be analyzed, wherein the first protective layer covers the side wall of the chip to be analyzed and comprises a hot melt adhesive layer;
and forming a second protective layer on the exposed surface of the first protective layer, wherein the second protective layer covers the exposed surface of the first protective layer and comprises a UV adhesive layer.
In one embodiment, the removing the carrier substrate using an etching solution includes:
dripping the corrosive liquid to the upper surface of the bearing substrate for reaction;
washing the upper surface of the bearing substrate after reaction;
repeating the steps until the bearing substrate is completely removed.
In one embodiment, the carrier substrate comprises a silicon substrate; the corrosive liquid comprises a potassium hydroxide solution; the temperature of the corrosive liquid is 80-100 ℃; before each flushing, the reaction time of the corrosive liquid and the bearing substrate is 20-60 s;
the washing the upper surface of the reacted carrier substrate comprises: and washing the upper surface of the bearing substrate after reaction by using alcohol.
In one embodiment, after forming the protective layer and before removing the carrier substrate with an etching solution, the method further includes:
and roughening the upper surface of the bearing substrate.
The invention also provides a failure analysis method, which comprises the following steps:
preparing the failure analysis structure by adopting the preparation method of the failure analysis structure according to any scheme;
and carrying out layer-by-layer failure analysis on the chip to be analyzed.
In the failure analysis method of the present invention, the failure analysis structure is prepared by the preparation method of the failure analysis structure, so the beneficial effects refer to the beneficial effects of the preparation method of the failure analysis structure, and are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow diagram of a method for fabricating a failure analysis structure provided in one embodiment;
fig. 2 is a schematic cross-sectional view of the structure obtained in step S101 in the method for manufacturing a failure analysis structure provided in an embodiment;
fig. 3 is a schematic cross-sectional view of the structure obtained in step S102 in the method for manufacturing a failure analysis structure provided in an embodiment;
fig. 4 is a schematic cross-sectional view of the structure obtained in step S103 in the method for manufacturing a failure analysis structure provided in an embodiment;
fig. 5 is a schematic cross-sectional view of the structure obtained in step S104 in the method for manufacturing a failure analysis structure provided in one embodiment;
fig. 6 is a schematic top view of the structure obtained in step S104 in the method for manufacturing a failure analysis structure provided in an embodiment;
fig. 7 is a schematic cross-sectional view of the structure obtained in step S105 in the method for manufacturing a failure analysis structure provided in one embodiment;
fig. 8 is a schematic cross-sectional view of a structure obtained by forming a protective layer on an upper surface of a base plate and covering the protective layer on the upper surface of the base plate in the method for manufacturing a failure analysis structure according to an embodiment;
FIG. 9 is a flowchart illustrating a step of attaching a sample to be analyzed to a substrate in a method of manufacturing a failure analysis structure according to an embodiment;
fig. 10 is a schematic cross-sectional view of a structure obtained in step S902 of the method for manufacturing a failure analysis structure provided in an embodiment;
FIG. 11 is a schematic cross-sectional view of a structure obtained by removing an exposed passivation layer and a passivation layer in a method for fabricating a failure analysis structure according to an embodiment;
FIG. 12 is a flowchart illustrating a step of forming a protective layer at least covering a sidewall of a chip to be analyzed in a method for fabricating a failure analysis structure according to an embodiment;
fig. 13 is a schematic cross-sectional view of a structure obtained in step S1201 in the method for manufacturing a failure analysis structure provided in one embodiment;
fig. 14 is a schematic cross-sectional view of a structure obtained in step S1202 in the method for manufacturing a failure analysis structure provided in one embodiment;
FIG. 15 is a flowchart illustrating a step of removing a carrier substrate using an etchant in a method of fabricating a failure analysis structure according to an embodiment;
fig. 16 is a schematic cross-sectional view of the structure obtained in step S1501 in the method for manufacturing a failure analysis structure provided in one embodiment;
fig. 17 is a schematic sectional structure view of a sample to be analyzed in the method of producing a failure analysis structure provided in one embodiment;
fig. 18 is a schematic top view illustrating a structure obtained by forming a scribe line on an upper surface of a carrier substrate to form a plurality of carrier grooves in the method for manufacturing a failure analysis structure according to an embodiment;
FIG. 19 is a flow diagram of a failure analysis method provided in an embodiment.
Description of reference numerals:
1. a sample to be analyzed; 11. a chip to be analyzed; 111. a substrate; 112. a wiring layer; 113. a passivation layer; 12. a carrier substrate; 121. a bearing groove; 2. a base plate; 3. a protective layer; 31. a first protective layer; 32. a second protective layer; 4. a protective layer; 5. and (4) corrosive liquid.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
With the development of semiconductor technology, a CIS (Contact Image Sensor) chip is a core chip commonly used in a camera product. Common CIS chips are chips made by two different processes, front and back illumination. A layer of bearing base is formed on the surface of the back-illuminated chip product in the technological process, so that the substrate can be thinned conveniently. And then, for the failure analysis of the back-illuminated chip, the sample preparation is required, so that the bearing substrate on the front surface of the chip needs to be removed.
At present, one method for removing the bearing substrate is to strip the bearing substrate by using an inductively coupled plasma reactive ion etching machine, but the method has high requirements on equipment, and the reaction gases mainly comprise chlorine and sulfur fluoride, and the two gases are easy to leak and have corrosiveness, high experimental risk and high requirements on equipment environment. Another method is to remove the carrier substrate by sanding, but this method is prone to damage to the edge of the chip, because the chip's identification information and positioning pattern are usually at the edge, and this method is not suitable for samples with target areas at the edge, nor is it advantageous to identify the sample number and position the sample when no sample information is known.
In view of the above, it is necessary to provide a method for manufacturing a failure analysis structure and a failure analysis method.
In order to achieve the above object, the present invention provides a method for manufacturing a failure analysis structure, as shown in fig. 1, the method for manufacturing a failure analysis structure includes:
s101: providing a sample to be analyzed, wherein the sample to be analyzed comprises a chip to be analyzed and a bearing substrate, and the bearing substrate is positioned on the front surface of the chip to be analyzed;
s102: providing a bottom plate;
s103: the sample to be analyzed is attached to the bottom plate, and the back surface of the chip to be analyzed faces the bottom plate;
s104: forming a protective layer, wherein the protective layer at least covers the side wall of the chip to be analyzed;
s105: and removing the bearing substrate by using an etching solution.
According to the preparation method of the failure analysis structure, the sample to be analyzed is attached to the bottom plate, the back surface of the chip to be analyzed of the sample to be analyzed faces the bottom plate, the bearing substrate is positioned on the front surface of the chip to be analyzed, the protective layer at least covers the side wall of the chip to be analyzed, and then the bearing substrate is removed by using the corrosive liquid, so that complex equipment such as an ion etching machine is not needed in the whole preparation process, the operation is simple and convenient, corrosive gases such as chlorine and the like are not used, and the chip to be analyzed cannot be corroded and damaged; and the protective layer is formed to at least cover the side wall of the chip to be analyzed, so that the side wall of the chip cannot be damaged in the process of removing the bearing substrate, and further, the information and the positioning pattern of the chip cannot be damaged, so that the chip can be positioned subsequently.
In step S101, please refer to step S101 in fig. 1 and fig. 2, a sample 1 to be analyzed is provided, the sample 1 to be analyzed includes a chip 11 to be analyzed and a carrier substrate 12, and the carrier substrate 12 is located on a front surface of the chip 11 to be analyzed.
In step S102, please refer to step S102 in fig. 1 and fig. 3, a bottom plate 2 is provided.
In one embodiment, the material of the base plate 2 may be a semiconductor material; after the carrier substrate 12 is removed by using the corrosive liquid, the bottom plate 2 does not need to be removed, and when the microscopic morphology of the chip is observed subsequently, the chip and the bottom plate 2 can be put into an SEM machine table together for morphology observation, and the surface discharge (charge) phenomenon can not be generated, so that the damage to the chip when the bottom plate 2 is removed can be overcome, and because the size of the chip is small, the bottom plate 2 is kept, so that the later-stage operations of clamping the chip, manually grinding the chip and the like can be facilitated.
In step S103, please refer to step S103 in fig. 1 and fig. 4, the sample 1 to be analyzed is attached to the bottom plate 2, and the back surface of the chip 11 to be analyzed faces the bottom plate 2.
In step S104, please refer to step S104 in fig. 1 and fig. 5 and 6, the protective layer 3 is formed, and the protective layer 3 at least covers the sidewall of the chip 11 to be analyzed.
Specifically, the protective layer 3 is formed to at least cover the side wall of the chip 11 to be analyzed, so that the side wall of the chip is not damaged in the process of removing the bearing substrate 12, information and a positioning pattern of the chip are not damaged, and subsequent positioning of the chip is not influenced.
In one embodiment, the chip to be analyzed 11 may be, but is not limited to, a back-illuminated image sensor chip; other types of chips may be possible that require some substrate to be removed prior to failure analysis.
In step S105, please refer to step S105 in fig. 1 and fig. 7, the carrier substrate 12 is removed by using an etchant.
In one embodiment, carrier substrate 12 may include, but is not limited to, a silicon substrate; the etching solution may include, but is not limited to, KOH (potassium hydroxide) solution; the temperature of the corrosive liquid is 80-100 ℃; before each flushing, the reaction time of the corrosive liquid and the bearing substrate 12 is 20-60 s; rinsing the upper surface of the reacted carrier substrate 12 comprises: the upper surface of the support substrate 12 after the reaction is rinsed with alcohol.
In some examples, the carrier substrate 12 is not limited to a silicon substrate, but may be other common material substrates; the selection of the etching solution can remove the corresponding bearing substrate 12, and is not limited to the KOH solution; the temperature of the etching solution can be 80 ℃, 85 ℃, 90 ℃, 95 ℃ or 100 ℃ to help increase the reaction rate between the etching solution and the carrier substrate 12, or any other temperature between 80 ℃ and 100 ℃, without being limited by the illustrated embodiment; the reaction time of the etching solution and the carrier substrate 12 can be 20s, 30s, 40s, 50s or 60s, or any other reaction time between 20s and 60s, and is not limited by the illustrated embodiment; rinsing the upper surface of the reacted carrier substrate 12 with alcohol may also help to increase the reaction rate between the etching solution and the carrier substrate 12.
In one embodiment, the area of the base plate 2 may be larger than the area of the chip to be analyzed; after providing the base plate 2 and before attaching the sample to be analyzed on the base plate 2, the method further includes the step of forming a protective layer 4 on the upper surface of the base plate 2, and the protective layer 4 covers the upper surface of the base plate 2, and the obtained structure is shown in fig. 8.
In one embodiment, as shown in fig. 9, the sample to be analyzed is attached to a base plate, comprising:
s901: coating a hot melt adhesive layer on the upper surface of the bottom plate to serve as a protective layer;
s902: and (3) pasting the sample to be analyzed on the upper surface of the protective layer, wherein the back surface of the chip to be analyzed is in contact with the protective layer.
In step S902, please refer to step S902 in fig. 9 and fig. 10, the sample 1 to be analyzed is attached to the upper surface of the protection layer 4, and the back surface of the chip 11 to be analyzed is in contact with the protection layer 4.
In one embodiment, after the carrier substrate is removed by using the etching solution, the step of removing the exposed protective layer 4 and the protective layer is further included, and the obtained structure is as shown in fig. 11, where the unexposed protective layer 4 between the chip 11 to be analyzed and the bottom plate 2 still remains.
In one example, the exposed protective layer 4 and the protective layer may be removed using an acetone solution.
In one embodiment, as shown in fig. 12, forming a protective layer covering at least the side wall of the chip to be analyzed includes:
s1201: forming a first protective layer on the side wall of the chip to be analyzed, wherein the first protective layer covers the side wall of the chip to be analyzed and comprises a hot melt adhesive layer;
s1202: and forming a second protective layer on the exposed surface of the first protective layer, wherein the second protective layer covers the exposed surface of the first protective layer and comprises a UV adhesive layer.
In step S1201, please refer to step S1201 in fig. 12 and fig. 13, a first protection layer 31 is formed on a sidewall of the chip 11 to be analyzed, the first protection layer 31 covers the sidewall of the chip 11 to be analyzed, and the first protection layer 31 includes a thermal melting adhesive layer.
In step S1202, please refer to step S1202 in fig. 12 and fig. 14, a second protective layer 32 is formed on the exposed surface of the first protective layer 31, the second protective layer 32 covers the exposed surface of the first protective layer 31, and the second protective layer 32 includes a UV glue layer.
Specifically, the surface of the first protective layer 31 is covered with the second protective layer 32 to ensure that the side wall of the sample is well sealed; the second protective layer 32 may include a UV glue layer that is small in size, suitable for thin coating, and resistant to high temperatures and acids and bases.
In one embodiment, as shown in FIG. 15, removing the carrier substrate using an etching solution includes:
s1501: dripping the corrosive liquid onto the upper surface of the bearing substrate for reaction;
s1502: washing the upper surface of the bearing substrate after reaction;
s1503: and repeating the steps until the bearing substrate is completely removed.
In step S1501, referring to step S1501 in fig. 15 and fig. 16, the etchant 5 is dropped onto the upper surface of the carrier substrate 12 for reaction.
Specifically, because the molecular weight of the corrosive liquid 5 is small, and the overall size of the chip 11 to be analyzed is also small, if a mode of directly and wholly soaking a sample in the corrosive liquid 5 is adopted, molecules of the corrosive liquid 5 easily permeate into the chip 11 to be analyzed, and the chip is greatly damaged; in the scheme of the application, the corrosive liquid 5 is dripped on the upper surface of the bearing substrate 12 for reaction, and is intermittently washed, and the dripping and washing modes are adopted for many times, so that the condition that the chip 11 to be analyzed is seriously damaged due to the fact that the sample is entirely soaked in the corrosive liquid 5 can be avoided; and, flushing once after each reaction of the etching solution 5 with the carrier substrate 12 can help to increase the reaction rate between the etching solution 5 and the carrier substrate 12.
In one embodiment, as shown in fig. 17, the chip to be analyzed 11 may include a substrate 111, a wiring layer 112, and a passivation layer 113; the wiring layer 112 is located on the upper surface of the substrate 111; the passivation layer 113 is positioned on the upper surface of the wiring layer 112, and the passivation layer 113 does not react with the etching solution; the carrier substrate 12 is located on an upper surface of the passivation layer 113.
Specifically, when the etching solution reacts with the carrier substrate 12 to the end, the etching solution leaks out of the surface of the passivation layer 113, and the passivation layer 113 does not react with the etching solution, so that the etching solution does not corrode the chip when the carrier substrate 12 is completely removed.
In one embodiment, after the formation of the protective layer and before the removal of the carrier substrate by using the etching solution, the method further includes a step of roughening the upper surface of the carrier substrate.
Specifically, the upper surface of the bearing substrate is roughened, so that the corrosion liquid can be prevented from flowing outwards and diffusing to the periphery, and the chip to be analyzed can be better protected.
In one embodiment, roughening the upper surface of the carrier substrate 12 includes: scribing grooves are formed on the upper surface of the carrier substrate 12 to form a plurality of carrier grooves 121, as shown in fig. 18.
In one embodiment, the roughening treatment of the upper surface of the carrier substrate may include the following steps:
forming a closed scribing groove, such as a circular scribing groove, an elliptical scribing groove or a rectangular scribing groove, on the upper surface of the bearing substrate;
forming a scratch or a scribing groove in the inner side area of the closed scribing groove.
In other embodiments, the upper surface of the carrier substrate may also be roughened by a process method such as rough grinding or etching.
The invention also provides a failure analysis method, as shown in fig. 19, the failure analysis method includes:
s1901: preparing a failure analysis structure by adopting the preparation method of the failure analysis structure in any scheme;
s1902: and carrying out layer-by-layer failure analysis on the chip to be analyzed.
The failure analysis structure and the method for manufacturing the failure analysis structure may refer to the content described in the foregoing text and the embodiments of fig. 1 to 18, which are not repeated herein.
Specifically, performing layer-by-layer failure analysis on the chip to be analyzed includes processing the structure from which the bearing substrate has been removed, and then analyzing each layer of the structure of the chip to be analyzed.
It should be noted that, the specific method for performing layer-by-layer failure analysis on the chip to be analyzed is known to those skilled in the art, and will not be described herein again.
In the failure analysis method of the present invention, the failure analysis structure used for analyzing the failure analysis structure is prepared by the above preparation method of the failure analysis structure, so the beneficial effects refer to the beneficial effects of the preparation method of the failure analysis structure, and are not described herein again.
It should be understood that, although the steps in the flowcharts of the embodiments are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method of making a failure analysis structure, comprising:
providing a sample to be analyzed, wherein the sample to be analyzed comprises a chip to be analyzed and a bearing substrate, and the bearing substrate is positioned on the front surface of the chip to be analyzed;
providing a bottom plate;
the sample to be analyzed is attached to the bottom plate, and the back surface of the chip to be analyzed faces the bottom plate;
forming a protective layer, wherein the protective layer at least covers the side wall of the chip to be analyzed;
and removing the bearing substrate by using an etching solution.
2. The method for manufacturing a failure analysis structure according to claim 1, wherein the chip to be analyzed includes a back-illuminated image sensor chip.
3. The method for manufacturing a failure analysis structure according to claim 1, wherein the area of the base plate is larger than the area of the chip to be analyzed; after providing the bottom plate, before attaching the sample to be analyzed on the bottom plate, the method further comprises:
and forming a protective layer on the upper surface of the bottom plate, wherein the protective layer covers the upper surface of the bottom plate.
4. The method for preparing a failure analysis structure according to claim 3, wherein the step of attaching the sample to be analyzed to the base plate comprises:
coating a hot melt adhesive layer on the upper surface of the bottom plate to serve as the protective layer;
and attaching the sample to be analyzed to the upper surface of the protective layer, wherein the back surface of the chip to be analyzed is in contact with the protective layer.
5. The method of manufacturing a failure analysis structure according to claim 3, further comprising, after removing the carrier substrate using an etching solution:
and removing the exposed protective layer and the protective layer.
6. The method for preparing a failure analysis structure according to claim 1, wherein the forming of the protective layer, which covers at least the side wall of the chip to be analyzed, comprises:
forming a first protective layer on the side wall of the chip to be analyzed, wherein the first protective layer covers the side wall of the chip to be analyzed and comprises a hot melt adhesive layer;
and forming a second protective layer on the exposed surface of the first protective layer, wherein the second protective layer covers the exposed surface of the first protective layer and comprises a UV adhesive layer.
7. The method of making a failure analysis structure according to claim 1, wherein the removing the carrier substrate using an etching solution comprises:
dripping the corrosive liquid to the upper surface of the bearing substrate for reaction;
washing the upper surface of the bearing substrate after reaction;
repeating the steps until the bearing substrate is completely removed.
8. The method of manufacturing a failure analysis structure according to claim 7,
the bearing substrate comprises a silicon substrate; the corrosive liquid comprises a potassium hydroxide solution; the temperature of the corrosive liquid is 80-100 ℃; before each flushing, the reaction time of the corrosive liquid and the bearing substrate is 20-60 s;
the washing the upper surface of the reacted carrier substrate comprises: and washing the upper surface of the bearing substrate after reaction by using alcohol.
9. The method for preparing a failure analysis structure according to claim 7, wherein after forming the protective layer and before removing the carrier substrate with an etching solution, the method further comprises:
and roughening the upper surface of the bearing substrate.
10. A method of failure analysis, comprising:
preparing the failure analysis structure using the method for preparing a failure analysis structure according to any one of claims 1 to 9;
and carrying out layer-by-layer failure analysis on the chip to be analyzed.
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