JP2000133620A - Method for working device to be observed - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for working a device to be observed for easily specifying the defective place of a semiconductor device. SOLUTION: This method is for working a silicon substrate 2 on whose surface a semiconductor integrated circuit formation area 34a in which a semiconductor integrated circuit is formed is provided so that this can be observed from the back face. At first, the back face of the silicon substrate 2 is ground so that one part of the back face of the silicon substrate 2 can be cut. Then, a hole H1 is started to be opened from the back face of the silicon substrate 2, and continued to be opened until an object 4 to be observed in the semiconductor circuit formation area 34a is exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an EB (Electoro)
The present invention relates to an observed device processing method for processing a semiconductor device so that the inside of the semiconductor device can be easily observed by a tester or the like.

[0002]

2. Description of the Related Art In recent years, in the failure analysis technology for semiconductor devices such as LSIs, the speeding up of failure analysis identification has become an important factor. Increasingly diverse, high-density, large-scale, multi-layer, and high-performance semiconductor device failure points are identified by not only information such as electrical signals output from inside the semiconductor device to the outside, but also It is also necessary to check information such as electric signals generated inside the semiconductor device.

As one of testing devices for examining information such as electric signals generated inside a semiconductor device, a potential waveform of a metal wiring of an internal circuit of the semiconductor device in a non-contact manner by using an electron beam as a probe. EB (Electoron Bea) for observing potential contrast images
m) There is a tester.

[0004]

An EB tester is now indispensable in order to specify a fault location inside a semiconductor device. In order to find a detailed failure location of a defective semiconductor device, it is necessary to observe a potential state of a circuit inside the semiconductor device and track a defective wiring while using a tool such as CAD navigation. However, with the diversification of semiconductor devices and the like, it has become impossible to observe the wiring, MOS transistor, and the like to be observed from the surface of the semiconductor device using an EB tester. As a result, a problem has arisen in that it is difficult to specify a failure location of a semiconductor device. Especially multilayer wiring devices, LOC
(Lead On Chip) and Flip Chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a method for processing a device to be observed for facilitating identification of a faulty portion of a semiconductor device.

[0006]

Means for Solving the Problems According to a first aspect of the present invention, there is provided a semiconductor integrated circuit having a semiconductor integrated circuit forming region formed on a front surface thereof. A method of processing, wherein: (a) polishing a back surface of the semiconductor substrate to remove a part of the back surface of the semiconductor substrate; and (b) after the step (a), a back surface of the semiconductor substrate. From first
Starting drilling and continuing to drill the first hole until the observation target in the semiconductor integrated circuit formation region is exposed.

[0007] The means for solving the problem according to claim 2 of the present invention is:
(C) Between steps (a) and (b),
A step of newly removing a part of the back surface of the semiconductor substrate by wet etching, wherein the semiconductor substrate prevents erosion of the semiconductor integrated circuit formation region by the wet etching at a boundary with the semiconductor integrated circuit formation region And a layer functioning as an etching stopper for performing the etching.

[0008] In the means for solving problems according to claim 3 of the present invention, the semiconductor substrate is made of silicon, and the layer functioning as the etching stopper is a silicon epitaxial layer.

According to a fourth aspect of the present invention, the semiconductor substrate, the layer functioning as an etching stopper, and the semiconductor integrated circuit forming region constitute an SOI structure, and the layer functioning as the etching stopper comprises: This is a buried oxide film having the SOI structure.

[0010] Means for solving the problems according to claim 5 of the present invention is:
(D) Between steps (c) and (b),
The method may further include performing wet etching for removing the buried oxide film.

[0011] The problem solving means according to claim 6 of the present invention is:
(E) forming a mark on the back surface of the semiconductor substrate to indicate a point in the semiconductor integrated circuit formation region for use as a position reference for forming the first hole.

According to a seventh aspect of the present invention, in the step (e), the step (e-1) starts forming a second hole as the mark from the back surface of the semiconductor substrate, Continuing to drill said second hole until an area is exposed.

In the means for solving problems according to claim 8 of the present invention, the step (e) comprises: (e-1) starting to make a second hole as the mark from the front surface of the semiconductor substrate; And continuing to make said second hole until it penetrates through.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following first to sixth embodiments, an observed device processing method for processing a semiconductor device so that the inside of the semiconductor device can be easily observed from the back surface using, for example, an EB tester will be described. .

Embodiment 1 The method for processing a device under observation according to the first embodiment of the present invention will be described with reference to FIGS.
First, the semiconductor device of FIG. 1 is prepared. The semiconductor device shown in FIG. 1 includes a semiconductor chip 1a, a package 5 for sealing the semiconductor chip 1a, and leads 6 electrically connected to the semiconductor chip 1a.

The semiconductor chip 1a is a silicon substrate (semiconductor substrate) 2 having on its surface a semiconductor integrated circuit formation region 34a on which a semiconductor integrated circuit is formed.

The semiconductor integrated circuit formation region 34a is formed of a MOS
(Metal Oxide Semiconductor) Includes elements such as transistor 3 and metal wiring. Reference numeral 4 denotes a part of a metal wiring, which is an observation target for which an EB tester wants to observe a potential waveform and a potential contrast image.

First, the package 5 is opened from the back surface of the semiconductor device by mechanical processing and chemical processing (FIG. 2).

Next, the back surface of the silicon substrate 2 is mechanically polished, whereby a part of the back surface of the silicon substrate 2 is scraped off. As a result, the silicon substrate 2 is reduced from several μm to several tens μm.
m so as to reduce the processing load of the next FIB (FIG. 3).

Next, a hole H1 (first hole) is locally formed from the back surface to the front surface of the silicon substrate 2 using FIB (Focused Ion Beam). Then, the hole H1 is continuously opened until the observation target 4 is exposed (FIG. 4). The hole H1 needs to be provided in the empty area 100 near the observation target 4. The free area is an area where elements such as the MOS transistor 3 are not formed or an area where elements that are not used for operation are present. Therefore, it is necessary to identify the position of the observation target 4 before drilling the hole H1. Identification of the four positions of the observation target
For example, it may be performed as in a fifth or sixth embodiment described later.

As described above, processing the back surface of the semiconductor device has the following effects. That is, the observation target 4 can be exposed from the back surface of the semiconductor device. Therefore, the potential waveform and the potential contrast image of the observation target 4 can be observed even from the back surface of the semiconductor device. Therefore, in particular, it is difficult to observe the observation target 4 from the surface of the semiconductor device by the EB tester.
When applied to a semiconductor device such as C or a flip chip, a potential waveform and a potential contrast image of the observation target 4 can be easily observed as compared with the related art. This makes it easy to specify the failure location of the semiconductor device.

Embodiment 2 FIG. A method for processing a device under observation according to the second embodiment of the present invention will be described with reference to FIGS.
First, the semiconductor device of FIG. 5 is prepared. In the semiconductor device of FIG. 5, the semiconductor chip 1a of FIG.
b.

The semiconductor chip 1b is a silicon substrate 2 having on its surface a semiconductor integrated circuit forming region 34b on which a semiconductor integrated circuit is formed. The silicon substrate 2 has a silicon epitaxial layer 7 at the boundary with the semiconductor integrated circuit formation region 34b. Other structures of the semiconductor chip 1b are the same as those of the semiconductor chip 1a.

Next, the package 5 is opened from the back surface of the semiconductor device by mechanical processing and chemical processing (FIG. 6).

Next, a part of the back surface of the silicon substrate 2 is scraped off by mechanically polishing the back surface of the silicon substrate 2. As a result, the silicon substrate 2 is reduced from several μm to several tens μm.
m to reduce the burden of processing by the FIB later (FIG. 7).

Next, by utilizing the difference in impurity concentration between the silicon substrate 2 and the epitaxial layer 7, a new silicon substrate 2 is formed.
Is selectively removed by wet etching. Thus, the epitaxial layer 7 is exposed (FIG. 8). This wet etching is performed on the epitaxial layer 7.
Apply something that does not erode. Thereby, the epitaxial layer 7 functions as an etching stopper for preventing erosion of the semiconductor integrated circuit formation region 34b due to wet etching. Performing this wet etching can further reduce the burden of processing by the next FIB.

Next, in the same manner as in the first embodiment, a hole H1 for exposing the observation target 4 is provided therein (FIG. 9).

The effect of the second embodiment is the same as that of the first embodiment. In particular, the back surface of the semiconductor device can be easily processed using the epitaxial layer 7.

Embodiment 3 Third Embodiment A method of processing a device under observation according to a third embodiment of the present invention will be described with reference to FIGS. First, the semiconductor device of FIG. 10 is prepared. FIG.
In the semiconductor device of FIG. 1, the semiconductor chip 1a of FIG.
This is replaced with a semiconductor chip 1c having a structure.

The semiconductor chip 1c is a silicon substrate 2 having on its surface a semiconductor integrated circuit formation region 34c on which a semiconductor integrated circuit is formed. The silicon substrate 2 has a buried silicon oxide film 9 at a boundary with the semiconductor integrated circuit formation region 34c. The semiconductor integrated circuit forming region 34c includes the SOI layer 8 formed on the buried silicon oxide film 9,
On the OI layer 8, elements such as the MOS transistor 3 and metal wiring are formed. The buried silicon oxide film 9
It serves to electrically insulate the semiconductor integrated circuit formation region 34c from the silicon substrate 2. Other structures of the semiconductor chip 1c are the same as those of the semiconductor chip 1a.

Next, the package 5 is opened from the back surface of the semiconductor device by mechanical processing and chemical processing (FIG. 11).

Next, a part of the back surface of the silicon substrate 2 is scraped off by mechanically polishing the back surface of the silicon substrate 2. As a result, the silicon substrate 2 is reduced from several μm to several tens μm.
m so as to reduce the burden of processing by the FIB later (FIG. 12).

Next, a part of the back surface of the silicon substrate 2 is selectively removed by wet etching. Thereby, the buried silicon oxide film 9 is exposed (FIG. 1).
3). In this wet etching, one that does not erode the buried silicon oxide film 9 is applied. Thereby, the buried silicon oxide film 9 functions as an etching stopper for preventing erosion of the semiconductor integrated circuit formation region 34c by wet etching. Performing this wet etching can further reduce the burden of processing by the next FIB.

Next, as in the first embodiment, a hole H1 for exposing the observation target 4 is provided inside (FIG. 14).

The effect of the third embodiment is the same as that of the first embodiment. In particular, the back surface of the semiconductor device can be easily processed using the SOI structure.

Embodiment 4 FIG. Fourth Embodiment A method for processing a device under observation according to a fourth embodiment of the present invention will be described with reference to FIGS. First, the structure of FIG. 13 is obtained as in the third embodiment.

Next, only the buried silicon oxide film 9 is selectively removed by wet etching. Thus, the SOI layer 8 is exposed (FIG. 15).

Next, a hole H1 is locally formed from the back surface to the front surface of the semiconductor chip 1c using FIB. Hole H
The observation target 4 is exposed in 1 (FIG. 16).

As described above, the buried silicon oxide film 9
By performing a wet etching to remove
The processing load of the next FIB can be further reduced. When the buried silicon oxide film 9 is removed, the layout pattern of the semiconductor integrated circuit formation region 34c can be confirmed from the back surface of the semiconductor device. Therefore, the position of the observation target 4 can be identified.

Embodiment 5 In the first to third embodiments, when drilling the hole H1, it is necessary to identify the position of the observation target 4. Further, in the fourth embodiment, even if the layout pattern of the semiconductor integrated circuit formation region 34c can be confirmed from the back surface of the semiconductor device by removing the buried silicon oxide film 9, for example, when the layout pattern is the same pattern repetition, it is observed. It is difficult to identify the subject 4. Therefore, in the fifth embodiment and a later-described sixth, a semiconductor device is processed as follows.

First, the structure shown in FIG. 3 is obtained, for example, as in the first embodiment.

Next, the position of the vacant area 100 is determined from the rear surface of the semiconductor chip 1a by approximate registration. For example, the position of the empty area 100 may be found based on the corner of the semiconductor chip 1a using CAD data or the like used when designing the layout of the semiconductor integrated circuit formation area 34a. Next, the hole H2 (the second
Start drilling holes). Then, the semiconductor integrated circuit formation region 3
The hole H2 is continuously opened until the metal wiring 41 of 4a is exposed (FIG. 17).

The hole H2 is provided perpendicular to the main surface of the semiconductor chip 1a in order to increase the accuracy of identification of the observation target 4. Hole H2 perpendicular to the main surface of semiconductor chip 1a
For example, alignment is performed at three or four corners of the semiconductor chip 1a from the back surface to check the parallelism.

The observation target 4 only needs to be exposed in the hole H2. If not, first, the shape of the metal wiring 41 exposed in the hole H2 is first determined based on the shape of the semiconductor integrated circuit formation region 3.
The position of the metal wiring 41 with respect to 4a is identified, and the distance L1 from the hole H2 to the observation target 4 is obtained. The distance L1 may be obtained from, for example, CAD data. Since the hole H2 is perpendicular to the main surface of the semiconductor chip 1a, the observation target 4 exists at a position separated by a distance L1 from the hole H2 on the back surface of the semiconductor device.

As described above, the position of the observation target 4 can be identified. After that, the first embodiment starts at a position separated by a distance L1 with respect to the hole H2 on the back surface of the semiconductor device.
As described above, the hole H1 is started to be opened using the FIB. Then, the hole H1 is continuously opened until the observation target 4 is exposed (FIG. 18). Exposed semiconductor chip 1 of FIG.
The back surface of a is simply shown in FIG.

Although the case where the present invention is applied to the first embodiment has been described, the present invention may be applied to the second to fourth embodiments.

As described above, first, the position of the observation object 4 is determined by roughly determining the position of the observation object 4, and then the position of the observation object 4 is identified using the hole H2 as a position reference. The position of the observation target 4 can be accurately identified by the two-stage narrowing. In particular, the fifth embodiment is particularly effective for a semiconductor device such as a LOC or a flip chip, which cannot be processed from the surface of the semiconductor device at all.

Embodiment 6 FIG. In the sixth embodiment, a semiconductor device is processed as follows.

First, as in the first embodiment, for example, the package 5 on the back surface of the semiconductor device is opened and mechanically polished, and then the package 5 on the front surface of the semiconductor device is opened to obtain the structure shown in FIG. . The opening of the front surface of the package 5 may be performed, for example, when opening the back surface of the package 5. The semiconductor chip 1d in FIG. 20 includes the metal wiring 42 in the upper layer of the observation target 4. Other configurations of the semiconductor chip 1d are the same as those of the semiconductor chip 1a of the first embodiment.

Since the surface of the semiconductor device was opened, the position of the empty area 200 near the observation target 4 was changed to the position of the semiconductor chip 1.
It can be easily identified from the surface of d.

Next, in the identified empty area 200,
The hole H3 (second hole) starts to be opened from the surface of the semiconductor chip 1d toward the empty area 200. Then, the hole H3 is continuously opened until it penetrates the back surface of the semiconductor chip 1d (FIG. 2).
1).

The hole H3 is provided perpendicular to the main surface of the semiconductor chip 1d in the same manner as in the fifth embodiment in order to increase the accuracy of identification of the observation object 4.

Next, the distance L2 from the hole H3 on the surface of the semiconductor device to the observation object 4 is determined. The distance L2 may be obtained from, for example, CAD data. Since the hole H3 is perpendicular to the main surface of the semiconductor chip 1d, the observation target 4 is located at a position on the back surface of the semiconductor device at a distance L2 from the hole H3.

As described above, the position of the observation target 4 can be identified. After that, the first embodiment starts from a place separated by a distance L2 with respect to the hole H3 on the back surface of the semiconductor device.
As described above, the hole H1 is started to be opened using the FIB. Then, the hole H1 is continuously opened until the observation target 4 is exposed (FIG. 22). Exposed semiconductor chip 1 of FIG.
FIG. 23 schematically shows the back surface of d.

Although the case where the present invention is applied to the first embodiment has been described, the present invention may be applied to the second to fourth embodiments.

As described above, first, the position of the vacant area 200 is identified and the hole H3 is provided, and then the position of the observation target 4 is identified based on the position of the hole H3. The position of the observation target 4 can be accurately identified by the two-stage narrowing.

Furthermore, as the elements such as the MOS transistors 3 are densely packed, that is, as the empty area is narrower, it becomes more difficult to form a hole avoiding the elements such as the MOS transistors 3. Therefore, the method of the fifth embodiment in which the position of a free area is determined by approximate registration cannot be dealt with as the free area is narrow. On the other hand, in the sixth embodiment, since the surface of the semiconductor device is opened, the position of the empty region 200 in the semiconductor integrated circuit formation region 34d can be confirmed from the surface of the semiconductor device, and the hole H3 can be started to be opened from that position. That is, the position of the empty area 200 near the observation target 4 can be determined with high accuracy from the surface of the semiconductor chip 1d.
Therefore, the hole H is avoided by avoiding the element such as the MOS transistor 3.
3 can be easily provided.

The sixth embodiment is particularly effective for a semiconductor device in which the observation target 4 is covered or adjacent to the metal wiring 42 or the like and cannot be observed from the surface but can be processed from the surface.

Modified example. In the fifth and sixth embodiments, a mark other than the holes H2 and H3 of the fifth and sixth embodiments may be used as a mark indicating a certain point in the semiconductor integrated circuit formation region. Also,
The timing of opening the holes H2 and H3 may be any time before the opening of the hole H1, but it is preferable because the burden of processing the holes H2 and H3 by the FIB can be reduced and the hole H1 can be opened following the holes H2 and H3. Is performed immediately before opening the hole H1.

The semiconductor substrate may be other than the silicon substrate 2.

[0061]

According to the first aspect of the present invention, the observation target can be exposed from the back surface of the semiconductor substrate. Therefore, the observation target can be observed even from the back surface of the semiconductor substrate. Therefore, it is easy to specify a failure portion of the semiconductor substrate where it is difficult to observe the observation target from the surface.

According to the second aspect of the present invention, the back surface of the semiconductor substrate can be removed up to the etching stopper.

According to the third aspect of the present invention, the epitaxial layer can be used as an etching stopper.

According to the present invention, the buried oxide film having the SOI structure can be used as an etching stopper.

According to the fifth aspect of the present invention, by removing the buried oxide film of the SOI structure, the layout pattern of the semiconductor integrated circuit formation region can be confirmed from the back surface of the semiconductor substrate, so that the position of the observation target can be more accurately determined. Can be identified.

According to the sixth aspect of the present invention, when exposing the observation target, the position of the observation target can be identified based on the mark.

According to the seventh aspect of the present invention, a mark can be easily provided by opening the second hole.

According to the eighth aspect of the present invention, a mark can be easily provided by drilling the second hole. Further, it is possible to confirm a position where no element is formed from the surface of the semiconductor substrate, and start drilling the second hole from that position. Therefore, holes can be easily formed by avoiding elements in the semiconductor integrated circuit formation region.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a device-under-observation processing method according to Embodiment 1 of the present invention;

FIG. 2 is a cross-sectional view for explaining the device-under-observation processing method according to the first embodiment of the present invention;

FIG. 3 is a cross-sectional view for explaining the device-under-observation processing method according to the first embodiment of the present invention;

FIG. 4 is a cross-sectional view for explaining the device-under-observation processing method according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view for explaining the device-under-observation processing method according to the second embodiment of the present invention;

FIG. 6 is a cross-sectional view for explaining the device-under-observation processing method according to the second embodiment of the present invention;

FIG. 7 is a cross-sectional view for explaining the device-under-observation processing method according to the second embodiment of the present invention;

FIG. 8 is a cross-sectional view for explaining the device-under-observation processing method according to the second embodiment of the present invention;

FIG. 9 is a cross-sectional view for explaining the device-under-observation processing method according to the second embodiment of the present invention;

FIG. 10 is a cross-sectional view for explaining the device-under-observation processing method according to the third embodiment of the present invention;

FIG. 11 is a cross-sectional view for explaining the device-under-observation processing method according to the third embodiment of the present invention;

FIG. 12 is a cross-sectional view for explaining the device-under-observation processing method according to the third embodiment of the present invention;

FIG. 13 is a cross-sectional view for explaining the device-under-observation processing method according to the third embodiment of the present invention;

FIG. 14 is a cross-sectional view for explaining the device-under-observation processing method according to the third embodiment of the present invention;

FIG. 15 is a cross-sectional view for explaining the device-under-observation processing method according to the fourth embodiment of the present invention;

FIG. 16 is a cross-sectional view for explaining the device-under-observation processing method according to the fourth embodiment of the present invention;

FIG. 17 is a cross-sectional view for explaining the device-under-observation processing method according to the fifth embodiment of the present invention;

FIG. 18 is a cross-sectional view for explaining the device-under-observation processing method according to the fifth embodiment of the present invention;

FIG. 19 is a plan view for explaining the device-under-observation processing method according to the fifth embodiment of the present invention;

FIG. 20 is a cross-sectional view for explaining the device-under-observation processing method according to the sixth embodiment of the present invention;

FIG. 21 is a cross-sectional view for explaining the device-under-observation processing method according to the sixth embodiment of the present invention;

FIG. 22 is a cross-sectional view for explaining the device-under-observation processing method according to the sixth embodiment of the present invention;

FIG. 23 is a plan view for explaining the device-under-observation processing method according to the sixth embodiment of the present invention;

[Explanation of symbols]

1a, 1b, 1c, 1d Semiconductor chip, 2 silicon substrate, 3 MOS transistor, 4 observation target, 5 package, 6 lead, 7 silicon epitaxial layer, 8 SOI layer, 9 buried silicon oxide film.

Claims (8)

[Claims] 1. A method of processing a semiconductor substrate having a semiconductor integrated circuit formation region on a front surface on which a semiconductor integrated circuit is formed, in order to observe the semiconductor substrate from a back surface side, wherein: (a) polishing the back surface of the semiconductor substrate (B) removing a part of the back surface of the semiconductor substrate; and (b) starting the first hole from the back surface of the semiconductor substrate after the step (a). Continuing the drilling of the first hole until the observation target is exposed. 2. The method according to claim 1, further comprising: (c) newly removing a part of the back surface of the semiconductor substrate by wet etching between the steps (a) and (b). 2. The method according to claim 1, further comprising a layer functioning as an etching stopper for preventing erosion of the semiconductor integrated circuit formation region due to the wet etching at a boundary with the integrated circuit formation region. 3. The method for processing an observed device according to claim 2, wherein the semiconductor substrate is made of silicon, and the layer functioning as the etching stopper is a silicon epitaxial layer. 4. The semiconductor substrate, the layer functioning as the etching stopper, and the semiconductor integrated circuit formation region form an SOI structure, and the layer functioning as the etching stopper includes the SOI layer.
3. The method for processing a device under observation according to claim 2, wherein the device is a buried oxide film having an I structure. 5. The method according to claim 4, further comprising the step of: (d) performing a wet etching for removing the buried oxide film between the steps (c) and (b). . 6. The method according to claim 1, further comprising the step of: (e) forming, on a rear surface of the semiconductor substrate, a mark indicating a certain point in the semiconductor integrated circuit formation region, for use as a position reference for forming the first hole. 6. The method for processing a device under observation according to any one of claims 1 to 5. 7. The step (e) comprises: (e-1) opening a second hole as the mark from the back surface of the semiconductor substrate, and opening the second hole until the semiconductor integrated circuit formation region is exposed. 7. The method for processing an observed device according to claim 6, further comprising the step of continuing. 8. The step (e) includes: (e-1) starting to form a second hole as the mark from the front surface of the semiconductor substrate, and continuing to form the second hole until the second hole penetrates the back surface of the semiconductor substrate. 7. The method for processing a device under observation according to claim 6, comprising a step.