JPH1174267A - Semiconductor device and method for analyzing wiring of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a multilayered interconnection structure and a method for analyzing the wiring of the semiconductor device, wherein a lower layer wiring formed under the topmost layer wiring can be analyzed directly. SOLUTION: In a semiconductor device having a multilayered interconnection structure, on a Vcc wiring 3 as the topmost layer wiring exposed from a chip 1 and on an GND wiring 4, an opening 6 or an opening 8 having a through-hole contact inside is formed. A lower layer wiring, which is formed under the Vcc wiring 3, i.e., the topmost layer wiring, and under the GND wiring 4 and will not even be structurally formed once on the chip 1 as the topmost wiring, is exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for analyzing wiring of a semiconductor device, and more particularly to a semiconductor device formed with a multilayer wiring structure and a method for analyzing wiring of a semiconductor device formed with a multilayer wiring structure. About.

[0002]

2. Description of the Related Art At present, a semiconductor device having a multi-layer wiring structure is frequently used in a semiconductor device in order to achieve high integration.

In a semiconductor device formed with a multilayer wiring structure, wiring connected to a power supply voltage Vcc, a ground GND, or the like is generally formed as an uppermost wiring exposed on the semiconductor device.

In a semiconductor device having a multilayer wiring structure, circuit blocks are formed below these uppermost wiring layers by being connected by lower wiring layers.

[0005] Due to the structure of the semiconductor device, such a lower-layer wiring may be connected without appearing as the uppermost-layer wiring at all, and without being exposed on the semiconductor device.

As described above, in the conventional semiconductor device, even if the lower wiring does not appear as the uppermost wiring, it is necessary to analyze the lower wiring formed in the lower wiring layer. However, if the lower wiring is formed without ever appearing as the uppermost wiring, there is no connection terminal for connecting the lower wiring and detecting a signal transmitted through the lower wiring. There is a drawback that it is impossible to analyze such lower wiring.

Further, as described above, in order to carry out circuit correction in a semiconductor device having a structure in which a lower wiring does not appear as an uppermost wiring at all, an experimental sample to which a correction experimental mask is applied is manufactured and characteristics are adjusted. Then, a procedure of determining an optimum correction value after evaluating the above is required. For this reason, TAT (Tuning from defect analysis to mass production mask correction)
rn Around Time) had the disadvantage of taking a long time.

In order to solve the above-mentioned drawbacks, a semiconductor device having the following structure has been proposed.

First, there is a "multilayer wiring structure semiconductor device" described in Japanese Patent Application Laid-Open No. 2-178942 as a first prior art for solving the above-mentioned disadvantages.

A semiconductor device having a multilayer wiring structure described in Japanese Patent Application Laid-Open No. 2-178942 will be described with reference to FIG. FIG. 4A shows a part of the layout of the semiconductor device having the multilayer wiring structure, and FIG. 4B shows a cross-sectional view of the semiconductor device having the multilayer wiring structure.

As shown in FIG. 4A, a semiconductor device having a multilayer wiring structure has a first aluminum layer 100.
, A second aluminum layer 101, a polycrystalline silicon layer 102 for forming a wiring with polycrystalline silicon, and an opening 103. This polycrystalline silicon layer 1
02 is a layer which never becomes the uppermost layer wiring in this semiconductor device.

The opening 103 shown in FIG.
It is formed to expose the polycrystalline silicon layer 102. Therefore, by providing the opening 103 on the insulating film on the surface of the semiconductor device, the polycrystalline silicon layer 102 as the lower wiring layer is exposed.

This state of exposure will be described with reference to FIG. 4B, which is a cross-sectional view of the semiconductor device shown in FIG. 4A taken along the line YY '. FIG. 4 (b)
FIG. 4 shows a cross-sectional view of the semiconductor device shown in FIG.

According to the sectional view shown in FIG.
This semiconductor device includes a first insulating layer 105 on a substrate 106.
Is formed, a polycrystalline silicon layer 102 is formed in the same layer as the first insulating layer 105, a second insulating layer 104 is formed on the first insulating layer 105, and the second insulating layer 10 is formed.
4, a first aluminum layer 100 is formed in the same layer as the first aluminum layer 100, and a second aluminum layer 101 is formed on the first aluminum layer 100 as the uppermost layer.

As shown in FIG. 4B, the opening 1
03 reaches the substrate 106 through the second insulating layer 104, exposing the polycrystalline silicon layer 102.

As described above, even if the polycrystalline silicon layer 102 never becomes the uppermost layer in the structure of the semiconductor device,
The polycrystalline silicon layer 102 can be analyzed because it is exposed by forming the opening 103.

Next, as a second prior art, Japanese Patent Laid-Open Publication No.
The "semiconductor integrated circuit device" disclosed in JP-A-212744 will be described.

FIG. 5 shows a part of the semiconductor integrated circuit device, FIG. 5A shows a layout diagram of a part of the semiconductor integrated circuit device, and FIG. 1 shows a cross-sectional view of the device.

Referring to FIG. 5A, in this semiconductor integrated circuit device, a second aluminum layer (referred to as a second AL layer in FIG. 5A) is used as an uppermost layer wiring. ) 207 are formed.

Next, FIG. 5B is a cross-sectional view of the semiconductor integrated circuit device shown in FIG. 5A taken along the line XX ′ shown in FIG. This will be described with reference to FIG. FIG. 5B is a cross-sectional view of the semiconductor integrated circuit device shown in FIG.

As shown in FIG. 5B, in this semiconductor integrated circuit device, a base layer 201 is formed on a substrate 200, and a first insulating layer 20 is formed on the base layer 201.
2 is formed, a second insulating layer 204 is formed on the first insulating layer 202, and a polycrystalline silicon layer 203 is formed in the same layer as the second insulating layer 204.

This polycrystalline silicon layer 203 constitutes a wiring which never becomes the uppermost layer due to the structure of the semiconductor device described above.

On the second insulating layer 204, a third insulating layer 204 is formed.
Of the insulating layer 206 is formed. Further, a through hole 209 is formed in the second insulating layer 204, and the first AL layer 205 is provided in the through hole 209.

Further, a through hole 208 is formed in the third insulating layer 206, and a second AL layer 207 is provided in the through hole 208.

Therefore, according to the semiconductor integrated circuit device shown in FIG. 5, by being covered with the insulating layer,
The polycrystalline silicon layer 203, which never becomes the uppermost layer, is drawn out to the uppermost layer via the first AL layer 205 and the second AL layer 207 by forming the through holes 208 and 209. The analysis of the polycrystalline silicon layer 203 can be easily performed.

Here, the first prior art and the second
The common point of the prior arts is that the lower wiring formed in the lower wiring layer can be analyzed only on a specific insulating layer where the uppermost wiring is not arranged.

[0027]

However, in the above-mentioned first prior art, the opening for analyzing the lower-layer wiring can be opened only on the insulating layer.
In the prior art of the above, a contact structure using a through hole is used, but even in this case, since a through hole can be formed only on the insulating layer, the lower wiring arranged under the uppermost wiring is analyzed. There is a problem that cannot be performed.

The present invention has been made in view of the above circumstances, and in a semiconductor device having a multilayer wiring structure, a semiconductor device and a semiconductor device capable of directly analyzing a lower wiring formed below an uppermost wiring. It is an object of the present invention to provide a method for analyzing wiring.

[0029]

According to the first aspect of the present invention,
In a semiconductor device formed by a multilayer wiring structure, an opening for exposing a lower wiring formed in a lower wiring layer below the uppermost layer to an uppermost wiring formed in an uppermost layer of the multilayer wiring structure. Is formed.

Therefore, according to the present invention, the lower wiring formed under the uppermost wiring never appears as the uppermost wiring due to the structure of the semiconductor device, and therefore is not exposed on the semiconductor device. However, since the opening for exposing the lower wiring is formed in the uppermost wiring, the lower wiring can be analyzed through the opening.

Furthermore, since the lower wiring is exposed through the opening, the lower wiring is directly analyzed to
In addition to improving the reliability of the analysis results, it is also possible to perform delay time adjustment using FIB equipment (Focused Ion Beam) for lower layer wiring and wiring change correction experiments such as logic changes, and from failure analysis The time required for resuming diffusion can be shortened.

According to a second aspect of the present invention, in the first aspect of the present invention, a through-hole contact for contacting an analysis probe is formed in the opening.

Therefore, according to the present invention, the effect of the first aspect of the present invention can be obtained, and a through-hole contact for contacting a probe for analysis is formed in the opening. When the contact is a stud pad for contact with the probe, the probe can be easily brought into contact with the semiconductor device when analyzing a defect of the semiconductor device.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the opening is formed so as not to cut the uppermost layer wiring.

Therefore, according to the present invention, the effect of the invention described in claim 1 or 2 can be obtained, and the opening is formed to have a size that does not cut the uppermost layer wiring. An analysis of the lower layer wiring can be performed without damaging the relationship.

According to a fourth aspect of the present invention, in the semiconductor device formed by the multilayer wiring structure, the semiconductor device is formed on the uppermost wiring formed on the uppermost layer of the multilayer wiring structure, and on the lower wiring layer below the uppermost layer. An opening for forming an opening for exposing the lower wiring, and an analyzing step for analyzing the lower wiring exposed by the opening.

Therefore, according to the present invention, the lower wiring formed under the uppermost wiring never appears as the uppermost wiring due to the structure of the semiconductor device, and therefore is not exposed on the semiconductor device. However, since the uppermost wiring has an opening forming step of forming an opening for exposing the lower wiring, the lower wiring can be analyzed through this opening.

Further, since the lower wiring is exposed through the opening, the lower wiring is directly analyzed to obtain
In addition to improving the reliability of the analysis results, it is also possible to perform delay time adjustment using FIB equipment (Focused Ion Beam) for lower layer wiring and wiring change correction experiments such as logic changes, and from failure analysis The time required for resuming diffusion can be shortened.

According to a fifth aspect of the present invention, in the semiconductor device formed by the multilayer wiring structure, the semiconductor device is formed on the uppermost wiring formed on the uppermost layer of the multilayer wiring structure, and on the lower wiring layer below the uppermost layer. Forming an opening for exposing the lower wiring, and forming a through-hole contact for contacting a probe for analysis with the opening; And analyzing the lower wiring exposed by the portion through the through-hole contact.

Therefore, according to the present invention, the lower wiring formed under the uppermost wiring never appears as the uppermost wiring due to the structure of the semiconductor device, and therefore is not exposed on the semiconductor device. However, since the uppermost wiring has an opening forming step of forming an opening for exposing the lower wiring, the lower wiring can be analyzed through this opening.

Since the lower wiring is exposed through the opening, the reliability of the analysis result can be improved by directly analyzing the lower wiring, and the FIB device (Focused Ion) can be used for the lower wiring. Beam) can be used to carry out delay time adjustments and wiring change correction experiments such as logic changes, thereby shortening the time required from failure analysis to resumption of diffusion.

Further, since the method has a through-hole contact forming step of forming a through-hole contact for contacting an analysis probe with the opening, for example, the through-hole contact can be replaced with the probe contact probe. By using the vertical pad, the probe can be easily brought into contact with the semiconductor device when analyzing a defect of the semiconductor device.

According to a sixth aspect of the present invention, in the semiconductor device formed by the multilayer wiring structure, the semiconductor device is formed on the uppermost wiring formed on the uppermost layer of the multilayer wiring structure, and on the lower wiring layer below the uppermost layer. Forming an opening for exposing the lower wiring, the opening having a size that does not cut the uppermost wiring, and a through-hole contact for contacting a probe for analysis with the opening. Forming a through-hole contact; and analyzing the lower-layer wiring exposed through the opening through the through-hole contact.

Therefore, according to the present invention, the lower layer wiring formed under the uppermost layer wiring never appears as the uppermost layer wiring due to the structure of the semiconductor device, and thus is not exposed on the semiconductor device. However, since the uppermost wiring has an opening forming step of forming an opening for exposing the lower wiring, the lower wiring can be analyzed through this opening.

Since the lower wiring is exposed through the opening, the reliability of the analysis result can be increased by directly analyzing the lower wiring, and the FIB device (Focused Ion) can be used for the lower wiring. Beam) can be used to carry out delay time adjustments and wiring change correction experiments such as logic changes, thereby shortening the time required from failure analysis to resumption of diffusion.

Further, since a through-hole contact forming step for forming a through-hole contact for bringing an analysis probe into contact with the opening is provided, for example, the through-hole contact can be replaced with a probe contact probe. By analyzing the failure of the semiconductor device by using the vertical pad,
The probe can be easily brought into contact.

Further, since the opening is formed so as not to cut the uppermost wiring, the analysis of the lower wiring can be executed without damaging the wiring relation of the semiconductor device.

[0048]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method of analyzing wiring of the semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a layout diagram of an embodiment of a semiconductor device according to the present invention. In the semiconductor device shown in FIG. 1, the V
cc wiring 3, similarly exposed GND wiring 4, and V
It comprises a cc wiring 3 and a pad 2 which is a contact terminal of the GND wiring 4. Also, as shown in FIG.
An opening 6 is formed in the cc wiring 3, and an opening 8 is formed in the GND wiring 4.

Next, FIG. 2 is an enlarged view of the vicinity of the openings 6 and 8 of the semiconductor device shown in FIG. FIG. 2 is an enlarged view of the semiconductor device shown in FIG.

As shown in FIG. 2, under the Vcc wiring 3 and the GND wiring 4, due to the structure of the semiconductor device, the lower wiring 7, which never appears as the uppermost wiring and is not exposed on the semiconductor device. And a circuit block 5 interconnected by the lower wiring 7 is formed.

As shown in FIG. 2, the opening 6 is formed at a position where the lower wiring 7 is exposed, and the lower wiring 7 is exposed.

The opening 8 is formed at a position where the lower wiring 7 is exposed, and a through-hole contact 9 is formed inside the opening 8 to draw out the lower wiring 7.

Next, referring to FIGS. 1, 2 and 3,
A more detailed structure of the semiconductor device according to the present invention will be described.

FIG. 1 is an overall image showing an example of the layout of the uppermost wiring as described above. The Vcc wiring 3 and the GND wiring 4 are formed of the uppermost wiring layer of aluminum, have a width of about 20 to 40 μm, and are thicker wirings than normal wirings.

FIG. 2 is an enlarged view of the Vcc wiring 3 and the GND wiring 4 shown in FIG. Vcc wiring 3, G
A circuit block 5 is formed below the ND wiring 4 and has a wiring width of 1.0 to 2.0.
It is connected by a lower wiring 7 of about μm. The lower wiring layer that forms the lower wiring 7 is preferably formed of aluminum, tungsten, or the like.

Vc, which is the upper wiring, directly above the lower wiring 7
An opening 6 having a side of about 5 μm is provided on the c wiring 3,
The lower wiring 7 is exposed to enable a contact probe of the lower wiring 7. By directly conducting a contact probe on the lower wiring 7, it is possible to perform waveform analysis, level analysis, and the like of a signal transmitted through the lower wiring 7.

As shown in FIG. 2, on the GND wiring 4 as the uppermost wiring formed of aluminum,
An opening 8 having a side of about 5 μm is provided, and a through-hole contact 9 having a side of about 0.9 μm is formed inside the opening 8.

Next, referring to FIG. 3, the opening 8 having the through-hole contact 9 shown in FIG. 2 will be described in further detail. FIG. 3 is a sectional view of the opening 8 of the semiconductor device shown in FIG.

Referring to FIG. 3, in this semiconductor device, a base layer 12 is formed, a lower wiring 7 is formed on the base layer 12, and an interlayer insulating film 11 is formed on the lower wiring 7. Is formed, and a GND wiring 4 as an upper wiring is formed on the interlayer insulating film 11.

As shown in FIG. 3, the opening 8 is
The lower wiring 7 is exposed through the D wiring 4 and the interlayer insulating film 11. Inside the opening 8, a through-hole contact 9 whose upper part is exposed to the surface of the semiconductor device and whose lower part is connected to the lower wiring 7 is formed.

Accordingly, by forming the through-hole contact 9 as, for example, a pad for a stylus for contacting a probe,
The probe can be easily brought into contact when analyzing a defect.

Further, by using the through-hole contact 9, a processing experiment for wiring change correction of the lower wiring 7 can be easily executed.

Here, in the above embodiment, FIG.
As described above, the case where the openings 6 and 8 are square is described as an example, but the gist of the present invention is that Vc
The openings 6 and 8 are formed to expose the lower wiring 7 formed below the upper wiring such as the c wiring 3 and the GND wiring 4.
Is formed, the shape of the opening to be formed is not particularly limited to a square, and any other shape such as a circle or a triangle can be used.

In the above-described embodiment, each side of the opening 6 and the opening 8 is about 5 μm. However, the size of the opening 6 and the opening 8 damages the wiring relation of the semiconductor device. In order to prevent this, the size should be within a range that does not cut the upper layer wiring, and is not particularly limited to the above numerical value. Further, the size of the through-hole contact 9 may be arbitrarily changed according to the size of the opening 8.

In the description shown in FIGS. 1 and 2, the opening 6 and the opening 8 in which the through-hole contact 9 is formed are provided in one semiconductor device. To avoid redundant description, FIG.
As shown in FIG. 2, on the uppermost layer wiring of one semiconductor device, an opening 6 and a through-hole contact 9 therein are formed.
Are formed. In the present invention, it is not particularly necessary to use these two types of openings simultaneously in one semiconductor device.
Either one or both may be used depending on the embodiment of the method for analyzing the wiring. It is clear that the effect of the present invention described above can be obtained even in this case.

Next, an embodiment of a method for analyzing wiring of a semiconductor device according to the present invention will be described with reference to FIGS.

First, as shown in FIG. 1, the lower wiring is exposed on the Vcc wiring 3 as the upper wiring so that the lower wiring is exposed.
An opening 6 is formed. Then, the exposed lower wiring is analyzed through the opening 6.

Similarly, an opening 8 is formed on the GND wiring 4 as an upper wiring so that the lower wiring is exposed, and a through hole contact is formed inside the opening 8 as shown in FIG. 9 is formed.

Then, the lower wiring 7 is analyzed by bringing an analysis probe or the like into contact with the through-hole contact 9, for example.

Therefore, according to the wiring analysis method of the semiconductor device, even if the lower wiring 7 is formed below the upper wiring and is not the uppermost wiring due to its structure, By providing the opening 6 or 8, the analysis can be performed.

[0072]

As is apparent from the above description, according to the present invention, the lower layer wiring hidden under the uppermost layer wiring by providing an opening on the uppermost layer wiring can be used for the probe contact or the like. In the semiconductor device formed by the multi-layer wiring structure, it is possible to directly analyze the failure, and to analyze the failure of the lower layer wiring formed below the uppermost layer wiring. It is possible to provide a semiconductor device and a method of analyzing wiring of the semiconductor device, which can shorten the period required for restarting.

Further, the effect of shortening the construction period described above has many correction points, and the more complicated the correction, the greater the effect.

Further, by forming a through-hole contact in the opening provided on the uppermost wiring, a mask modification experiment involving wiring change is performed on the lower wiring hidden under the uppermost wiring. Therefore, it is easy to bring an analysis probe or the like into contact with the through-hole contact, and the reliability of the analysis result can be increased. In addition, in a semiconductor device formed by a multilayer wiring structure, the uppermost wiring A semiconductor device and a method for analyzing wiring of a semiconductor device capable of easily and accurately performing an analysis experiment for confirming a defect correction using a wiring change correction or the like for a lower wiring formed under the semiconductor device. Can be provided.

[Brief description of the drawings]

FIG. 1 is a layout diagram of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is an enlarged view of the semiconductor device shown in FIG.

FIG. 3 is a sectional view of the semiconductor device shown in FIG. 2;

FIG. 4 is a diagram showing a structure of a conventional semiconductor device;
(A) is a layout diagram, and (b) is a sectional view.

FIG. 5 is a diagram showing a structure of a conventional semiconductor device;
(A) is a layout diagram, and (b) is a sectional view.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Chip 2 Pad 3 Vcc wiring 4 GND wiring 5 Circuit block 6 Opening 7 Lower wiring 8 Opening 9 Through hole contact 11 Interlayer insulating film 12 Underlayer

Claims (6)

[Claims] 1. A semiconductor device formed by a multilayer wiring structure, wherein an uppermost layer wiring formed on an uppermost layer of the multilayer wiring structure includes:
Lower wiring formed in a lower wiring layer below the uppermost layer,
A semiconductor device, wherein an opening for exposing the semiconductor device is formed. 2. The semiconductor device according to claim 1, wherein a through-hole contact for contacting a probe for analysis is formed in said opening. 3. The semiconductor device according to claim 1, wherein the opening has a size that does not cut the uppermost layer wiring. 4. In a semiconductor device formed by a multilayer wiring structure, a lower wiring formed on a lower wiring layer below the uppermost layer is exposed on an uppermost wiring formed on an uppermost layer of the multilayer wiring structure. Forming an opening for forming an opening, and analyzing the lower wiring exposed by the opening. 5. In a semiconductor device formed by a multilayer wiring structure, a lower wiring formed on a lower wiring layer below the uppermost layer is exposed on an uppermost wiring formed on an uppermost layer of the multilayer wiring structure. Forming an opening for forming a through hole; forming a through hole contact for making a probe for analysis come into contact with the opening; and forming a lower layer exposed by the opening. An analysis step of analyzing the wiring via the through-hole contact. 6. In a semiconductor device formed by a multilayer wiring structure, a lower wiring formed on a lower wiring layer below the uppermost layer is exposed on an uppermost wiring formed on an uppermost layer of the multilayer wiring structure. Forming an opening having a size that does not cut the uppermost layer wiring, and forming a through-hole contact for contacting an analysis probe with the opening. A method for analyzing wiring of a semiconductor device, comprising: analyzing the lower wiring exposed through the opening through the through-hole contact.