JPH04369849A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable the potential of wirings located lower than the uppermost wiring to be measured as accurately as in the case of the uppermost wiring. CONSTITUTION:The potential of an aluminum wiring 2 located under an oxide film 5 is measured through such a manner that the aluminum wiring 2 is connected to the dummy pad 8 formed of the uppermost aluminum wiring through the intermediary of a dummy through-hole 9.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which potential analysis inside a chip can be easily performed.

0002

2. Description of the Related Art FIG. 3 is a plan view of a conventional semiconductor integrated circuit device, showing two layers of aluminum wiring. In the figure, 1 and 2 are first layer aluminum interconnections, 3 is a second layer aluminum interconnection, and 4 is a through hole connecting the first layer aluminum interconnection 1 and the second layer aluminum interconnection 3. Further, FIG. 4 is a cross-sectional view taken along the line AA' in FIG.
2 is an oxide film insulating the second layer aluminum wiring 3, 6 is a glass coat, and 7 is a PIX coat.

Next, the functions and effects will be explained. An oxide film 5 is formed between the layer where the first layer aluminum wirings 1 and 2 exist and the layer where the second layer aluminum wiring 3 exists for electrical insulation. Further, the glass coat 6 and the PIX coat 7 are provided to protect the chip surface from moisture and foreign substances, and are often made of nitride, polyimide, etc., respectively.

[0004] When analyzing the internal potential of the chip, the PI
When the X coat 7 and the glass coat 6 are removed by plasma etching or the like, the second layer of aluminum wiring 3 is exposed. However, the oxide film 5 existing between the aluminum wiring layers cannot be removed. Therefore, the first layer aluminum wiring 1 is
An electron beam tester (hereinafter referred to as
The potential is measured using a device such as an EB tester.

[0005]

[Problem to be Solved by the Invention] Since the conventional semiconductor integrated circuit device is constructed as described above, the wiring existing in the layer below the top layer cannot be exposed because it is covered with an oxide film, so it is difficult to accurately There were problems such as difficulty in measuring potential.

[0006] This invention was made to solve the above problems, and by removing the PIX coat and the glass coat, not to mention the uppermost wiring layer.
It is an object of the present invention to obtain a semiconductor integrated circuit device capable of measuring the potential of wiring existing in the lower layer with the same accuracy as that of the wiring in the uppermost layer.

[0007]

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention includes a dummy through hole for use in potential analysis in the wiring existing in the lower layer, and a wiring in the uppermost layer on the dummy through hole. A dummy pad is provided on the same layer as the dummy pad.

[0008]

[Operation] In the present invention, the potential of the wiring in the lower layer is transmitted to the dummy pad formed by the wiring in the uppermost layer via the dummy through hole.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, 1 and 2 are the first
Layer aluminum wiring, 3 is second layer aluminum wiring, 4
is a through hole connecting the first layer aluminum wiring 1 and the second layer aluminum wiring 3; 8 is a dummy pad made of second layer aluminum provided on the first layer aluminum wiring 2; 9 is a first layer aluminum This is a dummy through hole that connects the wiring 2 and the dummy pad 8 of the second layer aluminum.

FIG. 2(a) is a sectional view taken along the line AA' in FIG. 1, and FIG. 2(b) is a sectional view taken along the line BB' in FIG. and an oxide film insulating the second layer aluminum wiring 3, 6 a glass coat, and 7 a PIX coat.

Next, the functions and effects will be explained. When analyzing the potential inside the chip, first, the PIX coat 7 and the glass coat 6 are removed using plasma etching or the like. At this point, the second layer aluminum wiring 3, which is the top layer, is exposed. However, the oxide film 5 existing between the aluminum wiring layers cannot be removed. Therefore, the potential of the first layer aluminum wiring 2 under the oxide film 5 cannot be accurately measured.

Therefore, the aluminum wiring (first layer aluminum wiring) 2 in the lower layer is connected to the dummy pad 8 made of aluminum (second layer aluminum) in the top layer through the dummy through hole 9. Then, by probing the dummy pad 8 with an EB tester or the like, it becomes possible to accurately measure the potential of the aluminum wiring 2 under the oxide film 5.

As described above, according to this embodiment, since the dummy pad made of the same aluminum as the dummy through hole and the second layer aluminum wiring is provided in the first layer aluminum wiring, it is easy to analyze the potential inside the chip. This also improves the accuracy of measuring the potential of the aluminum wiring existing under the oxide film, making it easier and more accurate to estimate or determine the location of a defect such as failure analysis.

[0014] The size of this top layer dummy pad made of aluminum needs to be the minimum area that can be probed by the potential measuring device.
When probing with a B tester, the beam diameter of the irradiated primary electrons is generally 1 μm or less, so the dummy pad may be very small. Therefore, the increase in wiring capacitance due to the aluminum of the dummy pad is negligible.

Furthermore, in the above embodiment, a dummy pad is provided directly above the lower layer aluminum wiring, but if another signal line exists directly above and a dummy pad cannot be provided, the lower layer Aluminum wiring may be routed to another location and connected to the dummy pad there, producing the same effect as in the above embodiment.

Further, in the above embodiment, the case of aluminum wiring was explained, but the wiring formed of aluminum alloy or polysilicon may be used, and the same effects as in the above embodiment can be obtained.

[0017]

As described above, according to the semiconductor integrated circuit device of the present invention, the potential of the wiring existing under the oxide film can be transferred to the dummy pad formed in the same layer as the top layer through the dummy through hole. Since it is configured to transmit the information, when analyzing the internal potential of the chip, just by removing the PIX coat and the glass coat, it is possible to measure not only the potential of the wiring in the top layer but also the potential of the wiring existing under the oxide film. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the AA' plane and the BB' plane in FIG. 1;

FIG. 3 is a plan view showing a conventional semiconductor integrated circuit device.

FIG. 4 is a sectional view taken along line A-A' in FIG. 3;

[Explanation of symbols]

1 First layer aluminum wiring 2 First layer aluminum wiring 3 Second layer aluminum wiring 4 Through hole 5 Oxide film 6 Glass coat 7 PIX coat 8 Second layer aluminum dummy pad 9 Dummy through hole

Claims (1)

[Claims] Claim 1: In a semiconductor integrated circuit device having a multilayer wiring structure, the wiring existing in the layers below the top layer wiring is
1. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is connected to a dummy pad formed in the same layer as the uppermost layer wiring through dummy through holes provided at required locations.