JPH08236593A - Evaluating method of wiring state on a semiconductor substrate - Google Patents
Evaluating method of wiring state on a semiconductor substrateInfo
- Publication number
- JPH08236593A JPH08236593A JP4146495A JP4146495A JPH08236593A JP H08236593 A JPH08236593 A JP H08236593A JP 4146495 A JP4146495 A JP 4146495A JP 4146495 A JP4146495 A JP 4146495A JP H08236593 A JPH08236593 A JP H08236593A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- wiring
- simulated
- semiconductor substrate
- standard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子における配
線パターン形状の評価方法及び下地段差構造の平坦度の
評価方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating a wiring pattern shape in a semiconductor device and a method for evaluating the flatness of an underlying step structure.
【０００２】[0002]
【従来の技術】従来の配線パターン形状の良否の評価
は、光学顕微鏡や電子顕微鏡及び欠陥検査機による直接
観察によっていた。また、従来の下地段差構造の平坦度
評価方法は、断面形状を直接観察したり、段差部に針や
レーザー、電子ビームを直接当てて高さを測定する方法
であった。2. Description of the Related Art Conventionally, the quality of a wiring pattern shape is evaluated by direct observation with an optical microscope, an electron microscope, and a defect inspection machine. Further, the conventional flatness evaluation method of the underlying step structure is a method of directly observing the cross-sectional shape or measuring the height by directly applying a needle, a laser or an electron beam to the step part.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、以上述
べた従来のいずれの評価方法であっても、評価時間が多
大であり、サンプル数の不足による評価結果の誤差成分
が大きいため、最適条件設定の信頼性が得られなかっ
た。すなわち、従来は満足なサンプル数が得られず、評
価結果の信頼性がないため、最適条件の見直し作業を繰
り返し行う必要があり、製品開発やトラブル対処の時間
と工数が大きかった。However, in any of the conventional evaluation methods described above, the evaluation time is long and the error component of the evaluation result is large due to the insufficient number of samples. The reliability was not obtained. That is, in the past, a satisfactory sample number could not be obtained, and the evaluation results were not reliable, so it was necessary to repeat the work of revising the optimum conditions, resulting in a large amount of time and man-hours for product development and troubleshooting.
【０００４】また、従来のパターン形状の評価方法は、
形状の直接評価であり、下地の組み合わせ等により、複
雑に変化する形状の良否判定において、定量的判断基準
の設定が困難であった。本発明は、以上述べた評価結果
の信頼性が低いことと、定量的判断基準の設定が困難で
あるという問題点を除去するため、同一基板上に標準パ
ターンと模擬パターンを作製し、標準パターンの電気抵
抗値と模擬パターンとの電気抵抗値とをそれぞれ求め、
前記標準パターンの電気抵抗値と前記模擬パターンとの
電気抵抗値とを比較し、定量化することにより、迅速、
かつ的確な配線状態の評価が可能な半導体基板上におけ
る配線状態の評価方法を提供することを目的とする。The conventional pattern shape evaluation method is as follows:
This is a direct evaluation of the shape, and it has been difficult to set a quantitative judgment standard in the quality judgment of the shape that changes intricately due to the combination of the base. In order to eliminate the above-mentioned problems that the reliability of the evaluation result is low and that it is difficult to set the quantitative judgment standard, the standard pattern and the simulated pattern are formed on the same substrate, and the standard pattern is prepared. And the electric resistance value of the simulated pattern,
By comparing and quantifying the electric resistance value of the standard pattern and the electric resistance value of the simulated pattern, rapid,
An object of the present invention is to provide a method for evaluating a wiring state on a semiconductor substrate, which enables an accurate evaluation of the wiring state.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目的を達
成するために、半導体基板上における配線状態の評価方
法において、 （１）同一基板上に標準パターンと模擬パターンを作製
し、標準パターンの電気抵抗値と模擬パターンとの電気
抵抗値とをそれぞれ求め、前記標準パターンの電気抵抗
値と前記模擬パターンとの電気抵抗値とを比較し、定量
化するようにしたものである。In order to achieve the above object, the present invention provides a method for evaluating a wiring state on a semiconductor substrate, comprising: (1) preparing a standard pattern and a simulated pattern on the same substrate, And the electric resistance value of the simulated pattern are respectively obtained, and the electric resistance value of the standard pattern and the electric resistance value of the simulated pattern are compared and quantified.
【０００６】（２）上記（１）記載の半導体基板上にお
ける配線状態の評価方法において、前記標準パターンは
下地段差を有しない配線パターンであり、前記模擬パタ
ーンは下地段差模擬パターン上に形成される配線パター
ンであり、該配線パターンの形状を評価するようにした
ものである。 （３）上記（１）記載の半導体基板上における配線状態
の評価方法において、前記標準パターンは下地段差を有
しない配線パターンであり、前記模擬パターンは下地段
差配線パターンであり、下地の平坦度を評価するように
したものである。(2) In the wiring state evaluation method on a semiconductor substrate described in (1) above, the standard pattern is a wiring pattern having no underlying step, and the simulation pattern is formed on the underlying step simulation pattern. It is a wiring pattern, and the shape of the wiring pattern is evaluated. (3) In the method of evaluating a wiring state on a semiconductor substrate according to the above (1), the standard pattern is a wiring pattern having no underlying step, and the simulated pattern is an underlying step wiring pattern, and the flatness of the underlying layer is determined. The evaluation is made.
【０００７】[0007]
【作用】本発明によれば、上記したように、同一基板上
に標準パターンと模擬パターンを作製し、標準パターン
の電気抵抗値と模擬パターンとの電気抵抗値とをそれぞ
れ求め、前記標準パターンの電気抵抗値と前記模擬パタ
ーンとの電気抵抗値とを比較し、定量化し、配線の形
状、例えば、細りの程度を評価する。According to the present invention, as described above, the standard pattern and the simulated pattern are formed on the same substrate, the electric resistance value of the standard pattern and the electric resistance value of the simulated pattern are respectively obtained, and the standard pattern and the simulated pattern are obtained. The electric resistance value and the electric resistance value of the simulated pattern are compared and quantified, and the shape of the wiring, for example, the degree of thinning is evaluated.
【０００８】また、下地段差上の配線パターンの評価方
法において、下地段差がない理想状態での標準配線パタ
ーンと実際の模擬配線パターンを同一基板上に複数作製
し、その相対的な抵抗値を比較評価することにより、パ
ターン形状の複雑な変化を観察によらず電気抵抗によ
り、定量化するようにしたものである。更に、同一基板
上に必要十分な模擬パターンを作製し、電気的特性を測
定機で測定するという簡便な手法を用いることで、評価
時間の短縮とデータ解析の信頼性を向上させることを可
能としたものである。In addition, in the method of evaluating a wiring pattern on a base step, a plurality of standard wiring patterns in an ideal state with no base step and an actual simulated wiring pattern are prepared on the same substrate, and their relative resistance values are compared. By evaluating, the complicated change of the pattern shape is quantified by the electric resistance without observing it. Furthermore, it is possible to shorten the evaluation time and improve the reliability of data analysis by using the simple method of creating necessary and sufficient simulated patterns on the same substrate and measuring the electrical characteristics with a measuring machine. It was done.
【０００９】[0009]
【実施例】以下、本発明の実施例について図を参照しな
がら詳細に説明する。 （Ａ）まず、配線パターン細りの評価方法について説明
する。図１は本発明の第１実施例を示す半導体基板上に
おける配線状態の評価を行う対象となる配線を示す図で
あり、図１（ａ）はその模擬段差パターンの平面図、図
１（ｂ）は標準模擬配線パターンの平面図である。Embodiments of the present invention will be described in detail below with reference to the drawings. (A) First, a method of evaluating the wiring pattern thinness will be described. 1A and 1B are diagrams showing a wiring which is an object of evaluation of a wiring state on a semiconductor substrate showing a first embodiment of the present invention. FIG. 1A is a plan view of a simulated step pattern thereof, and FIG. ) Is a plan view of a standard simulated wiring pattern.
【００１０】半導体製造フローと設計基準に基づいて、
図１に示すように、酸化膜、ポリシリコン、ポリサイ
ド、配線メタル等または、その組み合わせによって構成
された模擬段差パターン１１を作製する。段差横及び段
差上に形成された模擬配線パターン１２の抵抗値ＲA と
同一基板１０上の平坦部に形成されたマスク上同じ大き
さ、形の標準模擬配線パターン１４の抵抗値ＲB との比
較において、パターン細り１３がある部分の抵抗値ＲA2
は、標準模擬配線パターン１４の同一箇所の抵抗値ＲB2
に対して、パターン細り１３の部分の断面積の変化に応
じて、既知の断面積Ｓと配線長ｌと抵抗値の関係式は以
下のようになる。Based on the semiconductor manufacturing flow and design criteria,
As shown in FIG. 1, a simulated step pattern 11 made of an oxide film, polysilicon, polycide, wiring metal or the like or a combination thereof is produced. The resistance value R A of the simulated wiring pattern 12 formed on the side of the step and on the step and the resistance value R B of the standard simulated wiring pattern 14 of the same size and shape on the mask formed on the flat portion of the same substrate 10. In comparison, the resistance value R A2 of the portion having the pattern thinness 13
Is the resistance value R B2 of the same portion of the standard simulated wiring pattern 14.
On the other hand, the relational expression of the known cross-sectional area S, the wiring length 1 and the resistance value according to the change of the cross-sectional area of the pattern thin portion 13 is as follows.
【００１１】 抵抗値Ｒ＝ρ・ｌ／Ｓ （ρ：比抵抗、ｌ：配線長、Ｓ：断面積） …（１） この（１）式より、ＲA2＞ＲB2となるため、ＲA ＞ＲB
となる。従って、パターン細り１３の形状が複雑に変化
しても、抵抗値ＲA 、ＲB を測定し、比較することで、
パターン細りの程度を定量化することが可能となる。ま
た、電気抵抗値の測定は、簡便なため、短時間で必要十
分なデータが収集可能であり、評価結果の信頼性を向上
させることができる。Resistance value R = ρ · l / S (ρ: specific resistance, 1: wiring length, S: cross-sectional area) (1) From this equation (1), R A2 > R B2, and thus R A > R B
Becomes Therefore, even if the shape of the pattern thinning 13 changes intricately, by measuring and comparing the resistance values R A and R B ,
It becomes possible to quantify the degree of pattern thinning. Since the measurement of the electric resistance value is simple, necessary and sufficient data can be collected in a short time, and the reliability of the evaluation result can be improved.
【００１２】図２は本発明の第１実施例を示す半導体基
板上における配線状態の評価を行う対象となる配線の概
略測定回路例図である。この図において、模擬配線パタ
ーン１２のパッド１５と標準模擬配線パターン１４のパ
ッド１７には同一の定電流ＩT を印加し、模擬配線パタ
ーン１２のパッド１６と標準模擬配線パターン１４のパ
ッド１８はともに接地する。そして、模擬配線パターン
１２のパッド１５と標準模擬配線パターン１４のパッド
１７はそれぞれコンパレータ１９に接続する。つまり、
標準模擬配線パターン１４のパッド１７の電位を基準電
圧として、模擬配線パターン１２のパッド１５の電位を
比較することにより、電気抵抗が高いと電圧降下が大き
くなるので、その接地間の電位を検出することにより、
半導体基板上における配線状態の評価、ここでは、模擬
配線パターン１２の細りの状態の評価を行うことができ
る。FIG. 2 is a diagram showing an example of a schematic circuit for measuring the wiring to be evaluated on the semiconductor substrate according to the first embodiment of the present invention. In this figure, the same constant current I T is applied to the pad 15 of the simulated wiring pattern 12 and the pad 17 of the standard simulated wiring pattern 14, and the pad 16 of the simulated wiring pattern 12 and the pad 18 of the standard simulated wiring pattern 14 are both Ground. The pad 15 of the simulated wiring pattern 12 and the pad 17 of the standard simulated wiring pattern 14 are connected to the comparator 19, respectively. That is,
By comparing the potential of the pad 15 of the simulated wiring pattern 12 with the potential of the pad 17 of the standard simulated wiring pattern 14 as a reference voltage, the voltage drop becomes large when the electric resistance is high, so the potential between the grounds is detected. By
It is possible to evaluate the wiring state on the semiconductor substrate, here, the thin state of the simulated wiring pattern 12.
【００１３】（Ｂ）次に、下地段差の評価方法について
説明する。図３は本発明の第２実施例を示す半導体基板
上における段差形状の評価を行う対象となる配線を示す
図であり、図３（ａ）はその模擬段差パターンの平面
図、図３（ｂ）は図３（ａ）のＡ−Ａ線断面図、図３
（ｃ）は標準模擬配線パターンの平面図である。(B) Next, a method of evaluating the step difference of the base will be described. 3A and 3B are diagrams showing a wiring which is a target for evaluating a step shape on a semiconductor substrate showing a second embodiment of the present invention, and FIG. 3A is a plan view of the simulated step pattern, and FIG. ) Is a sectional view taken along the line AA of FIG.
(C) is a plan view of a standard simulated wiring pattern.
【００１４】半導体製造フローと設計基準に基づいて、
図３に示すように、酸化膜、ポリシリコン、ポリサイ
ド、配線メタルなどまたは、その組み合わせによって構
成された模擬段差パターン２１を作製し、その上に層間
膜２２を形成する。さらに、その上に形成された模擬配
線パターン２３の抵抗値ＲA ′と同一基板２０上の平坦
部に形成されたマスク上同一寸法、同一形状の標準模擬
配線パターン２５の抵抗値ＲB ′との比較において、模
擬段差パターン２１上の模擬配線パターン２３の配線長
ｌA は、標準模擬配線パターン２５の配線長ｌB に対し
て段差の程度に応じて、長くなる。Based on the semiconductor manufacturing flow and design criteria,
As shown in FIG. 3, a simulated step pattern 21 made of an oxide film, polysilicon, polycide, wiring metal or the like or a combination thereof is formed, and an interlayer film 22 is formed thereon. Further, the resistance value R A ′ of the simulated wiring pattern 23 formed thereon and the resistance value R B ′ of the standard simulation wiring pattern 25 having the same size and shape on the mask formed on the flat portion of the same substrate 20. In comparison, the wiring length l A of the simulated wiring pattern 23 on the simulated step pattern 21 becomes longer than the wiring length l B of the standard simulated wiring pattern 25 according to the degree of the step.
【００１５】従って、（１）式よりＲA ′＞ＲB ′とな
る。従って、段差形状を断面観察による破壊試験等を用
いずに、電気抵抗を測定することで簡便に必要十分なデ
ータ収拾が可能なため、評価結果の信頼性を向上させる
ことができる。なお、本発明は上記実施例に限定される
ものではなく、本発明の趣旨に基づき種々の変形が可能
であり、それらを本発明の範囲から排除するものではな
い。Therefore, from the equation (1), R A ′> R B ′. Therefore, the necessary and sufficient data can be collected easily by measuring the electric resistance without using a fracture test or the like by observing the cross-section of the step shape, so that the reliability of the evaluation result can be improved. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.
【００１６】[0016]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 （１）配線パターン細りや、下地段差形状の評価を同一
基板上に形成される標準模擬配線パターンとの電気抵抗
値により比較するようにしたので、複雑に変化するパタ
ーン細りの程度を定量化できる。また、段差評価を同様
にして評価を非破壊の状態で可能にすることができる。As described in detail above, according to the present invention, the following effects can be achieved. (1) Since the evaluation of the wiring pattern thinning and the underlying step shape is compared by the electric resistance value with the standard simulated wiring pattern formed on the same substrate, it is possible to quantify the degree of pattern thinning that changes in a complicated manner. . Further, the step evaluation can be similarly performed in a non-destructive state.
【００１７】更に、電気測定という簡便な方法を用いる
ため、必要十分なデータ収集が可能となり、評価結果の
信頼性を向上させることができる。 （２）また、実際の抵抗値を測定することは、回路設計
段階でのパラメータにも転用できるため、その利用的効
果は著大である。Furthermore, since a simple method of electrical measurement is used, necessary and sufficient data can be collected and the reliability of the evaluation result can be improved. (2) In addition, measuring the actual resistance value can be diverted to a parameter at the circuit design stage, so that its practical effect is significant.
【図１】本発明の第１実施例を示す半導体基板上におけ
る配線状態の評価を行う対象となる配線を示す図であ
る。FIG. 1 is a diagram showing a wiring which is an object of evaluation of a wiring state on a semiconductor substrate showing a first embodiment of the present invention.
【図２】本発明の第１実施例を示す半導体基板上におけ
る配線状態の評価を行う対象となる配線の概略測定回路
例図である。FIG. 2 is a diagram showing an example of a schematic measurement circuit for a wiring which is a target for evaluating a wiring state on a semiconductor substrate according to the first embodiment of the present invention.
【図３】本発明の第２実施例を示す半導体基板上におけ
る段差形状の評価を行う対象となる配線を示す図であ
る。FIG. 3 is a diagram showing a wiring which is a target for evaluating a step shape on a semiconductor substrate according to a second embodiment of the present invention.
１０，２０ 同一基板 １１，２１ 模擬段差パターン １２，２３ 模擬配線パターン １３ パターン細り １４，２５ 標準模擬配線パターン １５，１６，１７，１８ パッド １９ コンパレータ ２２ 層間膜 10, 20 Same substrate 11, 21 Simulated step pattern 12, 23 Simulated wiring pattern 13 Pattern thinning 14, 25 Standard simulated wiring pattern 15, 16, 17, 18 Pad 19 Comparator 22 Interlayer film
Claims (3)
ターンを作製し、（ｂ）前記標準パターンの電気抵抗値
と前記模擬パターンとの電気抵抗値とをそれぞれ求め、
（ｃ）前記標準パターンの電気抵抗値と前記模擬パター
ンとの電気抵抗値とを比較し、定量化することを特徴と
する半導体基板上における配線状態の評価方法。1. A standard pattern and a simulated pattern are produced on the same substrate, and an electric resistance value of the standard pattern and that of the simulated pattern are respectively obtained.
(C) A method for evaluating a wiring state on a semiconductor substrate, characterized by comparing and quantifying the electric resistance value of the standard pattern and the electric resistance value of the simulated pattern.
線状態の評価方法において、前記標準パターンは下地段
差を有しない配線パターンであり、前記模擬パターンは
下地段差模擬パターン上に形成される配線パターンであ
り、該配線パターンの形状を評価することを特徴とする
半導体基板上における配線状態の評価方法。2. The wiring state evaluation method on a semiconductor substrate according to claim 1, wherein the standard pattern is a wiring pattern having no underlying step, and the simulation pattern is a wiring pattern formed on the underlying step simulation pattern. A method for evaluating a wiring state on a semiconductor substrate, characterized in that the shape of the wiring pattern is evaluated.
線状態の評価方法において、前記標準パターンは下地段
差を有しない配線パターンであり、前記模擬パターンは
下地段差配線パターンであり、下地の平坦度を評価する
ことを特徴とする半導体基板上における配線状態の評価
方法。3. The method for evaluating a wiring state on a semiconductor substrate according to claim 1, wherein the standard pattern is a wiring pattern having no underlying step, and the simulation pattern is an underlying step wiring pattern, and the flatness of the underlying layer. A method for evaluating a wiring state on a semiconductor substrate, which comprises:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4146495A JPH08236593A (en) | 1995-03-01 | 1995-03-01 | Evaluating method of wiring state on a semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4146495A JPH08236593A (en) | 1995-03-01 | 1995-03-01 | Evaluating method of wiring state on a semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08236593A true JPH08236593A (en) | 1996-09-13 |
Family
ID=12609106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4146495A Withdrawn JPH08236593A (en) | 1995-03-01 | 1995-03-01 | Evaluating method of wiring state on a semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08236593A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002286780A (en) * | 2001-03-23 | 2002-10-03 | Nippon Sheet Glass Co Ltd | Inspection method of metal wiring and structure of semiconductor device suitable for inspection |
-
1995
- 1995-03-01 JP JP4146495A patent/JPH08236593A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002286780A (en) * | 2001-03-23 | 2002-10-03 | Nippon Sheet Glass Co Ltd | Inspection method of metal wiring and structure of semiconductor device suitable for inspection |
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