JPH1126343A - Semiconductor device and method for measuring deviated dimension in mask alignment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately and rapidly measure deviated amount in mask alignment. SOLUTION: An electron beam is radiated vertically on a silicon substrate 1 comprising a mask alignment deviation measurement pattern, with a gate electrode 11 and a contact hole 12, which constitute the pattern scanned in their array direction at a constant speed. Here, a voltage is supplied to the silicon substrate 1 from its rear surface, so that a current electrified in the silicon substrate 1 is detected. Only when the electron beam is radiated on the silicon substrate 1 where a bottom part of the contact hole 12 is exposed, a current is made to flow. The position of electron beam is found from its scanning speed and time, so that the deviated amount in mask alignment is obtained from the waveform of a detected current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for measuring the size of a semiconductor device, and more particularly, to a semiconductor device having a pattern for measuring a mask misalignment and a method for measuring the size of a mask misalignment of the semiconductor device.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, high precision is required even in mask positioning between different steps. Therefore, it is very important to accurately measure the amount of mask misalignment.

Conventionally, a mask readout is measured by a human using a microscope to read a caliper pattern (a pattern forming a scale), or by performing image processing using a dedicated mask printout measurement pattern. Was. When a human reads the amount of deviation, individual differences often occur and measurement takes time. In the case of measurement by image processing, it takes time to detect a pattern, which may result in erroneous detection.

As a method of detecting a pattern for image processing with an optimum threshold value, Japanese Patent Application Laid-Open No. 8-298091 proposes a pattern detection method as shown in FIG. Hereinafter, this measuring method will be briefly described.

FIG. 16 is a flowchart showing an example of a conventional pattern detection method. The registration procedure of the measurement position and the reference pattern will be described with reference to FIG.

First, an intended measurement pattern is displayed,
The position and the image data are taken as a reference pattern.
Next, an image is fetched again to evaluate the registered pattern, and compared with the image data in the memory to determine the similarity s.
Find 1 At this time, the positions and similarities sn (n = 1, 2,...) Of a plurality of patterns similar to the reference pattern
・) Further, based on the similarity s1 of the reference pattern itself and the similarity s2 of the pattern having the next highest similarity, a threshold value th at the time of detecting the reference pattern represented by the following equation and an evaluation value q for the reference pattern registration screen are obtained.

[0007]

## EQU1 ## th = (s1 + s2) / 2, q = (s1-s)
2) / s1 Here, the user can determine the validity of the reference pattern from the evaluation value q. For example, when the evaluation value q is low, the user can determine that the registered reference pattern is not appropriate, perform the registration procedure again, and repeat this until the evaluation value q becomes a high value.

The detection is performed by setting a threshold value th and comparing it with a reference pattern. At this time, only the reference pattern has a similarity greater than or equal to the threshold value th, and a pattern with a similarity lower than that is not a candidate for a detection pattern, so that only a target pattern is detected.

[0009]

A problem with the conventional method is that it takes time to detect a reference pattern for image processing. The reason for this is that it takes time to capture the image itself for image processing.

An object of the present invention is to improve the productivity by accurately and quickly measuring and grasping the mask misalignment dimension in a semiconductor manufacturing process, and by reducing contact opening defects and short-circuits between contact wirings.

[0011]

According to the present invention, there is provided a semiconductor device having a measurement pattern for measuring a mask alignment deviation in a manufacturing process, wherein the measurement pattern comprises: A first pattern serving as a reference for measuring a mask misalignment, and a second pattern arranged to partially overlap the first pattern and serving as a measurement object of the mask misalignment with respect to the first pattern. And only the region of the first pattern or the second pattern excluding the overlapping portion between the first pattern and the second pattern, or the first pattern and the first pattern Only the region of the second pattern overlapping with the pattern of the second pattern can pass a charged particle beam, which is irradiated perpendicularly to the semiconductor substrate, to the semiconductor substrate. Including those you have.

In the above semiconductor device, the first pattern is a stripe pattern formed by arranging elongated rectangular patterns at a first pitch, and the second pattern is a stripe pattern different from the first pitch. A stripe pattern in which elongated rectangular patterns are arranged at a pitch of 2. The first pattern and the second pattern are partially overlapped with each other in the same arrangement direction of the elongated rectangular patterns. Applicable.

The first pattern and the second pattern
It is conceivable that one of the patterns is a conductive layer serving as a wiring of an integrated circuit, and the other is a contact hole connecting between wirings of different layers of the integrated circuit or connecting the wiring to the semiconductor substrate.

Further, according to the present invention, there is provided a first pattern which is used as a reference for measuring a mask alignment shift, and is arranged so as to partially overlap the first pattern, and the mask alignment shift with respect to the first pattern is determined. A mask alignment misalignment measurement pattern composed of a second pattern to be measured and the first pattern or the second pattern;
Of the first pattern and the second pattern overlapping the first pattern, or only the region portion excluding the overlapping portion of the first pattern and the second pattern. Using a semiconductor device that allows a charged particle beam that is irradiated perpendicularly to the semiconductor substrate to flow through the semiconductor substrate only in a region of the semiconductor device, the mask alignment misalignment is performed while a voltage is supplied to the semiconductor device. Provided is a method of measuring a mask alignment displacement dimension of a semiconductor device, wherein the charged particle beam is scanned at a constant speed so as to pass through a measurement pattern, and a mask alignment displacement dimension is obtained from a waveform change of a current flowing through the semiconductor device. .

In such a method of measuring a mask misalignment dimension of a semiconductor device, a position of a measurement portion of the semiconductor device is detected as a scanning position of the charged particle beam by associating a scanning time of the charged particle beam with a current change time. Preferably, the voltage supplied to the semiconductor device is changed periodically. Further, at least one of secondary electrons and reflected electrons emitted from the semiconductor device by the irradiation of the charged particle beam is detected, and a position of a measurement portion of the semiconductor device is detected as a scanning position of the charged particle beam. It is also possible.

(Operation) In the invention as described above, a mask misalignment measurement pattern is formed on a semiconductor substrate during a semiconductor device manufacturing process. The mask misalignment measurement pattern included in the semiconductor device is disposed so as to partially overlap the first pattern serving as a reference for the mask misalignment measurement, and the first pattern. And a second pattern to be measured for mask misalignment. Then, the first pattern or the second pattern,
Only a region portion excluding an overlapping portion between the first pattern and the second pattern, or only a region portion of both the first pattern and the second pattern overlapping the first pattern is a semiconductor. The semiconductor substrate can be supplied with a charged particle beam which is irradiated perpendicularly to the substrate.

Therefore, the semiconductor substrate having the mask misalignment measurement pattern is irradiated with a charged particle beam vertically to pass the mask misalignment measurement pattern while a voltage is supplied to the semiconductor substrate. When the charged particle beam is scanned at a constant speed in one direction, the first pattern or the second pattern, an area portion excluding the overlapping portion of the first pattern and the second pattern, or The current flowing from the semiconductor substrate to the semiconductor device is detected only when the charged particle beam is applied to both the region of the first pattern and the region of the second pattern overlapping the first pattern.

From the detected current waveform corresponding to the scanning time of the charged particle beam and the scanning speed of the charged particle beam, the first pattern of the first pattern or the second pattern is detected. Width in the beam scanning direction of a region portion excluding an overlapping portion between the first pattern and the second pattern, or both a region of the first pattern and a region of the second pattern overlapping the first pattern. Thus, the mask misalignment dimension can be obtained.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 7 is a schematic plan view showing a mask misalignment measurement pattern of a semiconductor device in a manufacturing process, which is an embodiment of FIG. The mask misalignment measurement pattern is usually located in the scribe line area. In FIG. 1, reference numeral 10 denotes an elongated rectangular element region constituting a stripe pattern arranged at a first pitch as a first pattern serving as a reference of a mask misalignment measurement, and reference numeral 11 denotes a first pattern. The figure shows an elongated rectangular gate electrode forming a stripe pattern arranged at a second pitch as a second pattern to be measured for mask misalignment with respect to FIG. The pattern for measuring mask misalignment is composed of the first pattern and the second pattern described above, and includes a plurality of rows of element regions 10 as the first pattern and a plurality of rows of gate electrodes 11 as the second pattern. Are partially overlapped in the same arrangement direction.

Here, the manufacturing process of the mask misalignment measurement pattern in this embodiment will be described. FIG.
FIG. 2 is a cross-sectional view of the semiconductor device having a mask misalignment measurement pattern according to the first embodiment of the present invention in a manufacturing process, which corresponds to a cross section taken along line AA ′ of FIG. 1. In FIG. 2, first, a silicon oxide film 2 serving as an element isolation region is formed on a P-type silicon substrate 1 by a selective oxidation method to isolate an element region 10. Subsequently, a gate insulating film 3 of, for example, 15 nm, which is a thin insulating film, is formed on the element region 10 by a thermal oxidation method, and a conductive film having a two-layer structure of N-type polycrystalline silicon and tungsten silicide is formed of, for example, 200 n.
It is formed over the entire surface with a thickness of m. Next, the gate electrode 11 is formed by selectively etching the conductive film by a photolithography method and a dry etching technique.

At this time, as can be seen from FIGS. 1 and 2, the same number of the gate electrodes 11 and the element regions 10 are formed, but the gate electrodes 11 have a pitch different from that of the element regions 10. It is formed with. As a result, the gate electrode 11 partially overlaps the element region 10, so that the element region 10 and the gate electrode 11
Only the region excluding the overlapped portion with the above allows the silicon substrate 1 to be supplied with an electron beam which is irradiated perpendicularly to the P-type silicon substrate 1. In this case, the element region 10
The gate oxide film (insulating film) 3 exists on the region except for the overlap between the element region 10 and the gate electrode 11, but this is a very thin film. The electron beam can pass through it.

The state shown in FIGS. 1 and 2 is a case where a mask alignment shift has occurred in the right direction in the figure in a gate electrode forming step which is a subsequent step. Originally, it is designed such that the mask misalignment amount becomes zero when both (the element region 10 and the gate electrode 11) overlap exactly at the center of the mask misalignment measurement pattern.

In the present embodiment, the amount of mask misalignment is measured by scanning the mask misalignment measuring pattern while irradiating it with an electron beam (EB) and measuring the current. More specifically, an electron beam is irradiated perpendicularly to the silicon substrate 1 having the mask misalignment measurement pattern, and is directed in the direction in which the element region 10 and the gate electrode 11 constituting the mask misalignment measurement pattern are arranged. Scan at a constant speed. At this time, a voltage of, for example, +3 V is supplied from the back surface of the silicon substrate 1, and a current flowing through the silicon substrate 1 is detected.
Then, since the electron beam can pass through the gate oxide film 3 which does not overlap with the gate electrode 11, the silicon substrate is irradiated only when the electron beam is irradiated on the exposed surface of the gate oxide film 3 on the element region 10. 1 is supplied with current.

FIG. 3 shows the state of FIG.
This is the current value with respect to the time when scanning was performed. Thus, it can be readily understood from the waveform of the current that the mask alignment in the subsequent gate electrode forming step has shifted to the right in the drawing. Further, by comparing the respective pulse widths of the current waveforms on the left and right, it is possible to calculate the shift amount with higher accuracy. Since this method only monitors the current flowing through the silicon substrate, the time required for one measurement is short, and is suitable for measurement at many locations on the wafer.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 7 is a schematic plan view showing a mask misalignment measurement pattern of a semiconductor device in a manufacturing process, which is an embodiment of FIG. In FIG. 4, reference numeral 11 denotes an elongated rectangular gate electrode forming a stripe pattern arranged at a first pitch as a first pattern serving as a reference of a mask misalignment measurement, and reference numeral 12 denotes a first pattern. The figure shows an elongated rectangular contact hole forming a stripe pattern arranged at a second pitch as a second pattern to be measured for mask misalignment with respect to. The mask misalignment measurement pattern includes the first pattern and the second pattern described above, and includes a plurality of rows of gate electrodes 11 as the first pattern and a plurality of rows of contact holes 12 as the second pattern. Are partially overlapped in the same arrangement direction.

Here, the manufacturing process of the mask misalignment measuring pattern in this embodiment will be described. FIG.
FIG. 9 is a cross-sectional view of a semiconductor device in a manufacturing process having a mask misalignment measuring pattern according to a second embodiment of the present invention, and corresponds to a cross section taken along line BB ′ of FIG. 4.

First, a silicon oxide film 2 is formed on a P-type silicon substrate 1 by a thermal oxidation method, and then a conductive film having a two-layer structure of N-type polycrystalline silicon and tungsten silicide is formed on the silicon oxide film 2. For example, it is formed over the entire surface with a thickness of 200 nm. Next, the gate electrode 11 is formed by selectively etching the conductive film by a photolithography method and a dry etching technique.

After the gate electrode 11 is formed, a CV
According to the D (chemical vapor deposition) method,
An interlayer insulating film 4 made of a silicon oxide film BPSG (boron / phosphorus / glass) is deposited on the entire surface with a thickness of, for example, 600 nm. Next, the interlayer insulating film 4 is selectively etched by a photolithography method and a dry etching technique to form a contact hole 12. At this time, the contact hole 12 constituting the second pattern group reaches the silicon substrate 1 through the silicon oxide film 2 serving as an element isolation region for over-etching where the gate electrode 11 is not provided.

As can be seen from FIGS. 4 and 5, the same number of the gate electrodes 11 and the contact holes 12 are formed, but the contact holes 12 are formed at a pitch different from that of the gate electrodes 11. ing. This allows
The contact hole 12 has a silicon oxide film (insulating film) 2
Are partially overlapped with the gate electrode 11 on which the P-type silicon substrate 1 is provided, and only the region of the contact hole 12 excluding the overlapping portion between the contact hole 12 and the gate electrode 11 is irradiated perpendicularly to the P-type silicon substrate 1. An electron beam can be supplied to the silicon substrate 1.

The state shown in FIGS. 4 and 5 is a case where a mask misalignment has occurred to the right in the drawing in a contact hole forming step which is a subsequent step. Originally, it is designed such that when both of them (the gate electrode 11 and the contact hole 12) overlap exactly at the center of the mask misalignment measurement pattern, the mask misalignment becomes zero.

In this embodiment, similarly to the first embodiment, the mask alignment deviation measurement pattern is scanned while irradiating the electron beam (EB) with the electron beam (EB), and the current is measured. Measure the amount. More specifically, an electron beam is irradiated perpendicularly to the silicon substrate 1 having the mask misalignment measurement pattern, and is irradiated in the direction of arrangement of the gate electrode 11 and the contact hole 12 constituting the mask misalignment measurement pattern. Scan at a constant speed. At this time, a voltage of, for example, +3 V is supplied from the back surface of the silicon substrate 1, and a current flowing through the silicon substrate 1 is detected. Then, current is supplied only when the electron beam is irradiated on the silicon substrate 1 exposed at the bottom of the contact hole 12.

FIG. 6 shows the state of FIG.
This is the current value with respect to the time when scanning was performed. In this case as well, it can be immediately understood from the waveform of the current that the mask alignment in the subsequent contact hole forming step has been shifted to the right in the drawing. Further, by comparing the respective pulse widths of the current waveforms on the left and right, it is possible to calculate the shift amount with higher accuracy.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
FIG. 7 is a schematic plan view showing a mask misalignment measurement pattern of a semiconductor device in a manufacturing process, which is an embodiment of FIG. In FIG. 7, reference numeral 12 denotes an elongated rectangular contact hole forming a stripe pattern arranged at a first pitch as a first pattern serving as a reference for measurement of mask misalignment, and reference numeral 13 denotes a first pattern. In the figure, an elongated rectangular aluminum wiring forming a stripe pattern arranged at a second pitch is shown as a second pattern to be measured for mask misalignment with respect to. The mask misalignment measurement pattern includes the first pattern and the second pattern described above, and includes a plurality of rows of contact holes 12 as the first pattern and a plurality of rows of aluminum wirings 13 as the second pattern. Are partially overlapped in the same arrangement direction.

Here, the manufacturing process of the mask misalignment measurement pattern in this embodiment will be described. FIG.
FIG. 13 is a cross-sectional view of a semiconductor device having a mask misalignment measurement pattern according to a third embodiment of the present invention in a manufacturing process, which corresponds to a cross section taken along line CC ′ of FIG. 7.

First, a silicon oxide film 2 is formed on a P-type silicon substrate 1 by a thermal oxidation method, and then a silicon oxide film is formed on the entire surface of the silicon oxide film 2 by a CVD (chemical vapor deposition) method. The interlayer insulating film 4 made of BPSG (boron phosphorus glass) is formed, for example, by 600
It is deposited over the entire surface with a thickness of nm. Next, the contact holes 12 are formed by selectively etching the silicon oxide film 2 and the interlayer insulating film 4 by a photolithography method and a dry etching technique.

After the contact holes 12 are formed, aluminum is deposited on the entire surface to a thickness of, for example, 500 nm by sputtering. Next, the aluminum is selectively etched by a photolithography method and a dry etching technique to form an aluminum wiring 13.

At this time, as can be seen from FIGS. 7 and 8, the same number of the contact holes 12 and the aluminum wirings 13 are formed, but the pitch of the aluminum wirings 13 is different from that of the contact holes 12. It is formed with. As a result, the aluminum wiring 13 and the contact hole 12 partially overlap, so that only the contact hole 12 and both regions of the aluminum wiring 13 overlapping the contact hole 12 are perpendicular to the P-type silicon substrate 1. The irradiation of the electron beam to the silicon substrate 1 is enabled.

The state shown in FIGS. 7 and 8 is a case where a mask misalignment has occurred in the right direction in the figure in an aluminum wiring forming step which is a subsequent step. Originally, the mask misalignment is designed so that the mask misalignment amount becomes zero when both (the contact hole 12 and the aluminum wiring 13) overlap at the center of the mask misalignment measurement pattern.

In the present embodiment, similarly to the first and second embodiments, the pattern is measured while irradiating the electron beam (EB) on the mask misalignment measurement pattern, and the current is measured. Measure the amount of misalignment. More specifically, an electron beam is irradiated perpendicularly to the silicon substrate 1 having the mask misalignment measurement pattern, and is irradiated in the direction of arrangement of the contact holes 12 and the aluminum wiring 13 constituting the mask misalignment measurement pattern. Scan at a constant speed. At this time, a voltage of, for example, +3 V is supplied from the back surface of the silicon substrate 1, and a current flowing through the silicon substrate 1 is detected. Then, a current flows when the electron beam is irradiated on the bottom of the contact hole 12 or the aluminum wiring 13 connected to the silicon substrate 1 through the contact hole 12.

FIG. 9 shows the state of FIG.
This is the current value with respect to the time when scanning was performed. In this case, unlike the first and second embodiments, the current is conducted at any position of each pattern group constituting the mask misalignment measurement pattern, but the respective pulse widths of the current waveforms are different. Thus, the displacement amount can be accurately calculated.

(Fourth Embodiment) FIG. 10 is a schematic plan view showing a mask misalignment measuring pattern of a semiconductor device in a manufacturing process according to a fourth embodiment of the present invention.
In FIG. 10, reference numeral 11 denotes a gate electrode in a previous process which is a first pattern serving as a reference of a mask alignment deviation measurement, and reference numeral 12 denotes a second target which is a mask alignment deviation measurement target with respect to the first pattern. 3 shows a contact hole in a post-process, which is the pattern shown in FIG. The mask misalignment measurement pattern is composed of the first pattern and the second pattern, and the gate electrode 11 as the first pattern and the contact hole 12 as the second pattern partially overlap each other. I have.

Here, the manufacturing process of the mask misalignment measurement pattern in this embodiment will be described. FIG.
11 is a cross-sectional view of a semiconductor device having a mask misalignment measurement pattern according to a fourth embodiment of the present invention in a manufacturing process, which corresponds to a cross section taken along line DD 'of FIG. FIG.
First, a silicon oxide film 2 is formed on a P-type silicon substrate 1 by a thermal oxidation method, and then a conductive film having a two-layer structure of N-type polycrystalline silicon and tungsten silicide is formed on the silicon oxide film 2. For example, it is formed over the entire surface with a thickness of 200 nm. Next, the gate electrode 11 is formed by etching using a photolithography method and a dry etching technique while leaving a part of the conductive film.

After the gate electrode 11 is formed, a CV
According to the D (chemical vapor deposition) method,
An interlayer insulating film 4 made of a silicon oxide film BPSG (boron / phosphorus / glass) is deposited on the entire surface with a thickness of, for example, 600 nm. Next, the interlayer insulating film 4 deposited on and around the gate electrode 11 is etched by photolithography and dry etching to form the contact hole 1.
Form 2 At this time, the contact hole 12 as the second pattern penetrates through the silicon oxide film 2 to reach the silicon substrate 1 for over-etching where the gate electrode 11 is not present.

The mask misalignment measurement pattern is designed such that the misalignment amount becomes zero when the gate electrode 11 in the previous process is located exactly at the center of the contact hole 12 in the subsequent process. Then, the contact hole 12
The region except for the overlapping portion between the gate electrode 11 and the contact hole 12 allows the electron beam radiated perpendicularly to the P-type silicon substrate 1 to flow through the silicon substrate 1.

In this embodiment, similarly to the above-described embodiment, the mask alignment displacement measurement pattern is scanned while irradiating the electron beam (EB) with the electron beam (EB), and the current is measured. Measure the amount of displacement. More specifically, an electron beam is irradiated perpendicularly to the silicon substrate 1 having the mask misalignment measurement pattern, and is passed in one direction so as to pass over the gate electrode 11 constituting the mask misalignment measurement pattern. Scan at high speed. At this time, for example, +
By supplying a voltage of 3 V, a current flowing through the silicon substrate 1 is detected. Then, only when the electron beam is irradiated on the silicon substrate 1 at the bottom of the contact hole 12, the current is supplied.

FIG. 12 shows current values with respect to time when the electron beam is irradiated and scanned in the state of FIG. Since the position of the electron beam is known from the time and the scanning speed of the electron beam, the dimensions a and b shown in FIG. 10 can be obtained from the two pulse widths of the current waveform shown in FIG. If these a and b are used, the shift amount is (ab)
/ 2. Alternatively, when the dimensions a and b are not necessary and only the mask misalignment amount is required,
By multiplying the difference (t ₁ −t ₂ ) between the two pulse widths by the scanning speed (v) and dividing by 2, the mask misalignment amount can be calculated.

In this embodiment, as is apparent from FIG. 10, each shift in two axial directions (X direction and Y direction) orthogonal to each other in the plane is defined as one mask alignment shift measurement pattern. Can be measured. Also,
Here, the case where the pre-process is a gate electrode and the post-process is a contact hole has been described. It goes without saying that the quantity can be measured.

(Fifth Embodiment) FIG. 13 is a schematic plan view showing a mask misalignment measurement pattern in a semiconductor device according to a fifth embodiment of the present invention. In FIG. 13, reference numeral 12 denotes a contact hole in a previous process which is a first pattern serving as a reference for measurement of mask misalignment,
Reference numeral 13 denotes an aluminum wiring in a post-process, which is a second pattern to be measured for mask misalignment with respect to the first pattern. The mask misalignment measurement pattern is composed of the first pattern and the second pattern, and the contact hole 12 as the first pattern and the aluminum wiring 13 as the second pattern partially overlap each other. I have.

FIG. 14 is a sectional view of a semiconductor device having a mask misalignment measuring pattern according to the fourth embodiment of the present invention, and corresponds to a section taken along line EE ′ of FIG. Since the manufacturing process of the mask misalignment measurement pattern in the present embodiment is the same as that of the third embodiment, detailed description will be omitted.

The mask misalignment measurement pattern is
As in the case of the fourth embodiment, the center contact hole 12 in the previous step is replaced with the ring-shaped aluminum wiring 1 in the later step.
It is designed such that the shift amount becomes 0 when it is exactly at the center of 3. Then, only the contact hole 12 and the region of the aluminum wiring 13 overlapping the contact hole 12 are allowed to pass an electron beam, which is irradiated perpendicularly to the P-type silicon substrate 1, to the silicon substrate 1. I have.

In the present embodiment, similarly to the above-described embodiment, the mask alignment displacement measurement pattern is scanned while irradiating the electron beam (EB) with the electron beam (EB), and the current is measured. Measure the amount of displacement. More specifically, an electron beam is irradiated perpendicularly to the silicon substrate 1 having the mask misalignment measurement pattern, and is passed in one direction so as to pass over the contact holes 12 constituting the mask misalignment measurement pattern. Scan at high speed. At this time, a voltage of, for example, +3 V is supplied from the back surface of the silicon substrate 1, and a current flowing through the silicon substrate 1 is detected. Then, similarly to the case of the third embodiment, a current flows when the electron beam is irradiated to the bottom of the contact hole 12 or the aluminum wiring 13 connected to the silicon substrate 1 through the contact hole 12.

FIG. 15 shows current values with respect to time when the electron beam is irradiated and scanned in the state of FIG. Since the position of the electron beam can be determined by the time and the scanning speed of the electron beam, the dimensions c and d shown in FIG. 13 can be obtained from the three pulse widths of the current waveform shown in FIG. If these c and d are used, the shift amount is (cd)
/ 2. Alternatively, when the dimensions c and d are not required and only the mask misalignment amount is required,
To calculate the mask misalignment amount by multiplying the difference (t ₁ −t ₂ ) between two valley widths (time periods during which no current is applied) in the three pulse widths by the scanning speed (v) and dividing by 2 Can be.

In each of the above-described embodiments, secondary electrons and reflected electrons are emitted when irradiating and scanning an electron beam. Therefore, the same as a commonly used scanning electron microscope (SEM). As described above, it is possible to detect the position of the measurement portion of the semiconductor device as the scanning position of the electron beam by detecting the secondary electrons and the reflected electrons. In addition, the scanning by irradiating the electron beam has been exemplified.
For example, an ion beam may be used.

The present invention is not limited to the above embodiments, but allows various modifications without departing from the scope of the invention. For example, in each of the embodiments described above, the application of a constant voltage from the back surface of the silicon substrate has been described as an example. However, this voltage can be changed periodically.

In other words, if a thin oxide film is formed on the back surface of the silicon substrate or a contact hole is formed in an n-type or p-type well, and a DC current is not applied to the semiconductor device, it is applied. By periodically changing the voltage as an alternating current or a pulse voltage, the amount of misalignment of the mask can be measured from the change in the current inside the silicon substrate as in the case described above.

[0057]

As described above, the present invention provides a semiconductor device having a measurement pattern for measuring a mask misalignment dimension in a semiconductor integrated circuit manufacturing process. The mask alignment dimension measurement pattern includes a first pattern serving as a reference for mask alignment displacement measurement,
A second pattern, which is arranged so as to partially overlap the first pattern, and is a target of measurement of a mask misalignment with respect to the first pattern, wherein the first pattern or the second pattern The first of the patterns
Only a region portion excluding an overlapping portion between the first pattern and the second pattern, or only a region portion of both the first pattern and the second pattern overlapping the first pattern is a semiconductor. An electron beam irradiated perpendicular to the substrate can be supplied to the semiconductor substrate. Therefore, using a semiconductor device in such a manufacturing process, the semiconductor device is irradiated with an electron beam perpendicularly to the substrate surface and passes through the mask misalignment measurement pattern in a state where a voltage is supplied to the semiconductor substrate. The electron beam is scanned in one direction at a constant speed, so that an area portion of the first pattern or the second pattern, excluding an overlapping portion between the first pattern and the second pattern. Or measuring the width in the beam scanning direction of both the area of the first pattern and the area of the second pattern overlapping the first pattern as a current waveform corresponding to the scanning time of the beam. And the amount of mask misalignment can be determined from the above width dimension.

As described above, according to the present invention, the amount of misalignment of the mask can be easily grasped by a very simple technique of measuring the current, so that the amount of misalignment of the mask can be measured accurately and at high speed.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a mask misalignment measurement pattern in a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device having a mask misalignment measurement pattern according to the first embodiment of the present invention.

FIG. 3 is a waveform diagram showing a current value with respect to a time when an electron beam is irradiated and scanned in the manufacturing state shown in FIG.

FIG. 4 is a schematic plan view showing a mask misalignment measurement pattern in a second embodiment of the semiconductor device of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor device having a mask misalignment measurement pattern according to a second embodiment of the present invention.

FIG. 6 is a waveform diagram showing current values with respect to time when an electron beam is irradiated and scanned in the manufacturing state shown in FIG.

FIG. 7 is a schematic plan view showing a mask misalignment measurement pattern in a third embodiment of the semiconductor device of the present invention.

FIG. 8 is a sectional view of a semiconductor device having a mask misalignment measurement pattern according to a third embodiment of the present invention.

FIG. 9 is a waveform diagram showing a current value with respect to a time when an electron beam is irradiated and scanned in the manufacturing state shown in FIG. 8;

FIG. 10 is a schematic plan view showing a mask misalignment measurement pattern in a semiconductor device according to a fourth embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor device having a mask misalignment measurement pattern according to a fourth embodiment of the present invention.

FIG. 12 is a waveform diagram showing current values with respect to time when an electron beam is irradiated and scanned in the manufacturing state shown in FIG.

FIG. 13 is a schematic plan view showing a mask misalignment measurement pattern in a fifth embodiment of the semiconductor device of the present invention.

FIG. 14 is a cross-sectional view of a semiconductor device having a mask misalignment measurement pattern according to a fifth embodiment of the present invention.

FIG. 15 is a waveform diagram showing current values with respect to time when an electron beam is irradiated and scanned in the manufacturing state shown in FIG.

FIG. 16 is a flowchart for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxide film 3 Gate oxide film 4 Interlayer insulating film 10 Element region 11 Gate electrode 12 Contact hole 13 Aluminum wiring

Claims (7)

[Claims] 1. A semiconductor device in a manufacturing process having a measurement pattern for measuring a mask alignment shift in a semiconductor manufacturing process, wherein the measurement pattern is a first reference which is a mask alignment shift measurement standard. Is arranged so as to partially overlap the first pattern,
A second pattern to be measured for a mask misalignment with respect to the first pattern, wherein the first pattern and the second pattern of the first pattern or the second pattern are Only a region portion excluding an overlap portion, or only a region portion of both the first pattern and the second pattern overlapping the first pattern is charged perpendicularly to the semiconductor substrate. A semiconductor device, wherein a particle beam can be supplied to the semiconductor substrate. 2. The first pattern is a stripe pattern in which elongated rectangular patterns are arranged at a first pitch, and the second pattern is formed at a second pitch different from the first pitch. A stripe pattern formed by arranging elongated rectangular patterns, wherein the first pattern and the second pattern partially overlap each other in the same arrangement direction of the elongated rectangular patterns. Item 2. The semiconductor device according to item 1. 3. One of the first pattern and the second pattern is a conductive layer serving as a wiring of an integrated circuit;
3. The semiconductor device according to claim 1, wherein the other is a contact hole for connecting between wirings of different layers of the integrated circuit or connecting the wiring to the semiconductor substrate. 4. A first pattern serving as a reference for measuring mask misalignment, and the first pattern is arranged so as to partially overlap with the first pattern, and becomes a measurement object of the mask misalignment with respect to the first pattern. A mask alignment misalignment measurement pattern composed of the second pattern and
Only the region of the first pattern or the second pattern excluding the overlapping portion between the first pattern and the second pattern, or the region overlapping the first pattern and the first pattern Using only a semiconductor device in a manufacturing process in which only the two regions of the second pattern are capable of supplying a charged particle beam that is irradiated perpendicularly to the semiconductor substrate to the semiconductor substrate, In a state where a voltage is supplied, the charged particle beam is scanned at a constant speed so as to pass through the mask misalignment measurement pattern, and a mask misalignment dimension is obtained from a waveform change of a current flowing through the semiconductor device.
A method for measuring a mask misalignment dimension of a semiconductor device. 5. The apparatus according to claim 4, wherein the position of the measurement portion of the semiconductor device is detected as the scanning position of the charged particle beam by making the scanning time of the charged particle beam correspond to the change time of the current. 3. The method for measuring a mask misalignment dimension of a semiconductor device according to item 1. 6. The method according to claim 4, wherein a voltage supplied to the semiconductor device is periodically changed. 7. A method for detecting at least one of secondary electrons and reflected electrons emitted from the semiconductor device by the irradiation of the charged particle beam, and detecting a position of a measurement portion of the semiconductor device as a scanning position of the charged particle beam. The method for measuring a mask misalignment dimension of a semiconductor device according to any one of claims 4 to 6, wherein: