JP2587614B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly to an alignment pattern for reduction projection exposure of a semiconductor device.

[Conventional technology]

In the prior art, as shown in the plan view of FIG. 4, one alignment pattern (3) is arranged corresponding to one semiconductor device (1). In such a case, the scribe region (2) is almost occupied by the alignment pattern. For example, when measuring the electric characteristics of the semiconductor device, the device for measuring the electric characteristics detects the scribe region and When performing automatic measurement by aligning the layout of the semiconductor devices arranged in a matrix on a semiconductor substrate, a conventional technique,
As shown in the figure, since the scribe area is occupied by the alignment pattern, the scribe area is not detected, and the measurement becomes impossible.

In addition, an etching process is performed when manufacturing the semiconductor device. In this etching, particularly in recent microfabrication, plasma etching is used. The wavelength emitted by the plasma gas is detected.
When etching is in progress, the wavelength of the reaction product of the material to be etched and removed is large, but the wavelength of the reaction product is reduced when the etching of the material to be removed is completed. In detecting the end of etching by detecting the degree of decrease in the wavelength, in the area of the material to be etched, when the area occupied by the scribe region is large, if an alignment pattern is arranged in the scribe region, the detection of the end of etching In addition, the absolute amount of the wavelength generated by the reaction product is reduced, and the wavelength cannot be accurately detected, resulting in excessive etching and the production of a defective product.

Furthermore, when a test pattern such as a monitor element pattern for checking the electrical characteristics of the semiconductor device, a pattern for measuring the alignment accuracy, and a pattern for measuring the dimensional accuracy is put in the scribe area, the scribe area is occupied by the alignment pattern. Therefore, it is not possible to sufficiently arrange patterns necessary for producing and evaluating the characteristics of the semiconductor device, and it becomes impossible to manufacture a semiconductor device with good performance.

Further, when the size of the semiconductor device is reduced, the size of the alignment pattern necessary for manufacturing the semiconductor device becomes larger, and the semiconductor device cannot be arranged.

[Problems and objects to be solved by the invention]

The problems to be solved by the present invention are, as described in the section of the related art, that the alignment of the device for measuring the electrical characteristics is not disabled, the detection of the end of the etching is not disabled, and the scribe region is not disabled. That is, the various patterns and the like necessary for fabricating the semiconductor device in addition to the alignment pattern are sufficiently arranged, and further, it is possible to sufficiently cope with a small semiconductor device.

An object of the present invention is to solve the above-mentioned problems, and to provide a useful means capable of coping with a semiconductor device of any size.

[Means for solving the problem]

The semiconductor device of the present invention comprises: (a) a plurality of chips individually separated by a plurality of scribe lines provided on a substrate and extending in a row direction and a column direction; and (b) scribe lines in a predetermined column direction. And the first, second, third, and fourth chips that are in contact with the first scribe line in the first row direction are formed continuously on the first scribe line sandwiched between the chips, and One end on the first row direction scribe line sandwiched between the first and second chips, and another end on the first row direction scribe line sandwiched between the third and fourth chips. An alignment pattern having an end; and (c) a second row direction having no alignment pattern and sandwiching the first scribe line sandwiched between the first to fourth chips. A scribe line and a third line scribe line.

(Operation)

According to the present invention, since one alignment pattern is provided for two or more adjacent chips, the ratio of the alignment pattern in the entire scribe area can be reduced.

Example 1 A plan view when one alignment pattern 3 was arranged in a scribe region in four semiconductor devices close to FIG. 1 was shown. As a result, the occupation ratio of the alignment pattern in the scribe area was reduced to one fourth.

Embodiment 2 FIG. 2 shows a plan view of an example in a scribe area in the Y direction. This example is a 5: 1 reduction projection type exposure apparatus which needs to arrange a die-by-die alignment pattern in a Y-direction scribe area. By doing so, the ratio of the alignment pattern occupying the scribe area in the Y direction also became 1/4.

〔The invention's effect〕

According to the present invention, as shown in the first and second embodiments, the number of alignment patterns to be arranged in the scribe area is reduced to one for two or more adjacent semiconductor devices.
It could be greatly reduced by a factor of 1/4. As a result, the area occupied by the alignment pattern in the scribe area is immediately reduced. For this reason, the monitor element pattern for checking the electrical characteristics of the semiconductor device, the pattern for measuring the alignment precision, and the pattern for measuring the dimensional precision are provided in the scribe area. Etc. can be arranged sufficiently. Further, all the problems to be solved, such as easy detection of the scribe region and automatic measurement of the electrical characteristics, accurate detection of the etching in the etching process, and sufficient support for a small semiconductor device. Has a great effect on

In addition, for each manufacturing apparatus (aligner) to be used, it is arranged at a position in the scribe area where the alignment accuracy can be optimized, so that the alignment accuracy can be improved.

As described above, the effect of the present invention is not influenced by the device used, but is to bring out the performance of the device sufficiently. In addition, the characteristics in etching have been improved, and it has become possible to manufacture a semiconductor device having good performance. Also, the yield is improved. In addition, the electrical characteristics, alignment accuracy, and dimensional accuracy can be sufficiently measured, thereby improving the performance and reliability of the semiconductor device.

Further, according to the method of the present invention, the size of the semiconductor device is
If the size is smaller than the required size of the alignment pattern, it has not been possible to manufacture the device in the past, but this is also possible, and the present invention is completely unaffected by the size of the semiconductor device.

Further, according to the present invention, various patterns arranged in the scribe area are reduced, and as a result, an area in the scribe area having no pattern is increased. As a result, the cross-sectional structure of the scribe region adheres more faithfully to the structure capable of obtaining the long-term reliability of the semiconductor device, and the reliability increases.

The effect of the present invention is a useful technique even when manufacturing semiconductor devices having different sizes. In addition, the standardization of the alignment pattern greatly improves the efficiency of design. For example, the effects of the present invention can be obtained over a wide range and are very effective.

[Brief description of the drawings]

 FIG. 1 is a plan view of a first embodiment according to the present invention. FIG. 2 is a plan view of a second embodiment according to the present invention. FIG. 3 is a plan view of the prior art. DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Scribe area 3 ... Alignment pattern 4 ... Electrical characteristic measurement pattern 5 ... Dimensional accuracy measurement pattern 6 ... Alignment accuracy measurement pattern

Claims (1)

(57) [Claims] (A) a plurality of chips provided on a substrate and separated by a plurality of scribe lines extending in a row direction and a column direction; and (b) a plurality of scribe lines in a predetermined column direction. The first, second, third, and fourth chips that are in contact with a one-row scribe line are formed continuously on the first scribe line sandwiched between the chips, and One end is located on the first row scribe line sandwiched between the second chips, and the other end is located on the first row scribe line sandwiched between the third and fourth chips. (C) a second row direction scriber that is located so as to sandwich the first row direction scribe line sandwiched between the first to fourth chips and does not have an alignment pattern. A semiconductor device having a line and third row direction scribe line, the.