JP2003023022A - Continuity test structure for bump electrode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect in advance the high output impedance defect of an output terminal before a probing test, and to perform speedy countermeasures. SOLUTION: A continuity testing structure for gold bump electrodes, which has a lower electrode 22 formed on a semiconductor substrate 21, a protective film 23 coating the lower electrode 22, a pair of opening parts H1 and H2 arranged in the protective film 23 above the lower electrode 22 and a pair of bump electrodes for continuity test 25A and 25B, which are formed on the exposed lower electrode 22 via UBM layers 24A, 24B in a pair of the opening parts H1 and H2, is installed in an LSI chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a continuity test structure for a bump electrode structure.

[0002]

2. Description of the Related Art Gold bump electrodes and solder bump electrodes are known as one of high-density mounting techniques. This kind of electrode is
For example, it is often used when an LSI having a multi-bit output terminal such as an LCD driver or an organic EL driver is mounted on a printed circuit board or the like at a high density.

FIG. 5 shows an example of a gold bump electrode structure. 5A is a plan view of the gold bump electrode structure, and FIG. 5B is a sectional view taken along line XX in FIG. 5A.

On the integrated circuit chip 1 (silicon substrate or the like) on which a desired semiconductor integrated circuit (not shown) is formed, Al which is responsible for connection between the semiconductor integrated circuit and external connection terminals (not shown)
A connection electrode (also called a pad electrode) 2 made of an (aluminum) thin film is formed.

The peripheral portions of the integrated circuit chip 1 and the connecting electrodes 2 are covered with a protective film 3 made of a silicon nitride film (Si3N4 film) or the like. As a result of the protective film 3 being partially removed from the central portion of the connecting electrode 2, the opening H is provided. A UBM (Under Bump) that functions as a barrier metal for the connection electrode 2 exposed in the opening H
The gold bump electrode 6 is formed via the (Metal) layer 4A.

A plurality of the above-described gold bump electrode structures are provided on the integrated circuit chip 1, and the integrated circuit chip 1 has a high-density mounting structure in which the gold bump electrodes 6 are pressure-bonded onto predetermined wirings on the printed circuit board. Is possible.

FIG. 6 is a block diagram showing an output section of an LCD driver LSI, for example. 51a, 51b, 51
c are a plurality of output terminal portions of the gold bump electrode structure described above. The output electrodes 52a, 52b are connected to the connection electrodes 2 of the output terminal portions 51a, 51b, 51c, respectively.
b and 52c are connected. Output buffers 52a, 5
2b and 52c include output control circuits 53a, 53b and 53c.
The data from is applied.

Next, a method of forming the above-mentioned gold bump electrode structure will be described with reference to FIGS. 7 to 12.
As shown in FIG. 7, a connection electrode 2 (also called a pad electrode) made of Al (aluminum) is formed on an integrated circuit chip 1 on which a desired integrated circuit (for example, LCD driver) is formed.

The connecting electrode 2 has a thickness of about 1 μm. Next, a protective film 3 made of a silicon nitride film (Si3N4 film) is formed on the entire surface by the CVD method. The thickness of the protective film 3 is 0.8
About 1 μm to 1 μm is suitable. Here, instead of the silicon nitride film (Si3N4 film), the silicon nitride film (Si3N4 film)
You may form the laminated film of this and a silicon oxide film (SiO2 film).

Then, an opening H is formed in the central portion of the protective film 3 by the photolithography method. That is, by forming a photoresist (not shown) on the protective film 3 and exposing and developing the photoresist using a photomask having a mask pattern corresponding to the opening, the opening is formed in the photoresist. To do. Then, dry etching is performed using the photoresist as a mask to etch the protective film 3 to form an opening H.

The dry etching conditions at this time are as follows: when the protective film 3 is made of a silicon nitride film, a chemical dry etching (Chemical Dry Etchin) using CF4 + 02 gas is used.
g) is suitable. When the protective film 3 is composed of a laminated film of a silicon nitride film (Si3N4 film) and a silicon oxide film (SiO2 film), reactive ion etching (Reactive Ion Etching) using CHF3 + 02 gas may be used. Appropriate. After this dry etching, the photoresist is removed.

Next, as shown in FIG. 8, a plating electrode 4 is formed on the entire surface. Since this plating electrode 4 is located under the gold bump electrode in a later process, UBM (Under Bump Meta
Also called l). The plated electrode 4 is an Au / TiW layer formed by sequentially sputtering titanium-tungsten alloy (TiW) and gold (Au), for example. Here, it is appropriate that the upper Au layer has a thickness of 100 nm to 200 nm, and the lower TiW layer has a thickness of about 200 nm.

Next, as shown in FIG. 9, a photoresist 5 is applied on the plating electrode 4 and a predetermined exposure and development are performed to form an opening of the photoresist 5 in the gold bump electrode formation region. Here, as the photoresist, it is appropriate to use a negative resist having a film thickness of 25 μm to 32 μm.

Then, as shown in FIG. 10, gold bump electrodes 6 are formed on the plating electrodes 4 exposed in the openings of the photoresist 5 by electrolytic plating. At this time, it is appropriate that the height of the gold bump electrode 6 is about 15 μm.

Next, as shown in FIG. 11, the photoresist 5 is removed. Then, as shown in FIG. 12, the unnecessary portion of the plating electrode 4 is removed by chemical treatment using the gold bump electrode 6 as a mask. Here, the upper layer of the plating electrode 4
Aqua regia is used to etch the Au layer, and hydrogen peroxide solution H2O2 is used to etch the lower TiW layer.
As a result, the plated electrode 4 remains only under the gold bump electrode 6 and literally becomes a UBM (Under Bump Metal) layer. The UBM layer 4A functions as a barrier metal layer.

[0016]

However, according to the method of forming the gold bump electrode structure described above, the plating electrode 4
In some cases, the high resistance layer 7 was formed at the interface between the (UBM) and the gold bump electrode 6 due to the bump forming process. Therefore, in the probing test using the LSI tester after completion of the gold bump electrode structure, the output terminals 51a, 5a of FIG.
The output impedance of 1b, 51c, ... Is abnormally high, and the LSI is defective.

Since this defect cannot be identified without a probing test after the gold bump electrode structure is completed, there has been a problem that the response to the occurrence of the defect is delayed.

Further, this type of defect is caused not only by the gold bump electrode structure but also by the solder bump process in the solder bump structure.

Therefore, an object of the present invention is to detect a high output impedance defect of an output terminal in advance by performing a simple continuity test in a process before a probing test, and to enable quick response. To do.

[0020]

SUMMARY OF THE INVENTION A bump electrode continuity test structure of the present invention comprises a lower electrode formed on an integrated circuit chip, a protective film for covering the lower electrode, and a protective film on the lower electrode. It is characterized by having a pair of openings provided and a pair of bump electrodes for a continuity test formed on the lower layer electrodes exposed in the pair of openings via a UBM layer.

In the normal bump electrode structure, as described above, the opening H is provided on the connecting electrode 2 and the U is formed on the connecting electrode 2.
Although one gold bump electrode 6 was formed via the BM layer 4A, in the present invention, a pair of bump electrodes for continuity test are provided on the lower layer electrode in order to enable the continuity test of the bump electrode.

Therefore, a voltage is applied between the pair of continuity test bump electrodes to test whether or not they are conductive. If they are not conductive, a high output impedance failure due to the formation of the high resistance layer 7 described above occurs. It turns out that you did.

Therefore, by performing this continuity test immediately after the bump process, a high output impedance defect can be detected in advance, so that it is possible to promptly take measures such as discarding the defective product and improving the process. In the case of a solder bump electrode structure, it is preferable to carry out before solder reflow or immediately after solder reflow in order to detect defects early.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described with reference to FIG. 1A and 1B are views showing a continuity test structure of a gold bump electrode. In FIG. 1, FIG. 1A is a plan view thereof, and FIG. 1B is a sectional view taken along line YY in FIG.

Lower layer electrode 2 formed on semiconductor substrate 21
2 has a rectangular pattern shape in a plane. Since this gold bump electrode continuity test structure is a test structure for the continuity test, the output buffer 5 of the LSI shown in FIG.
2a, 52b, 52c are not connected. However, the lower layer electrode 22 is formed at the same time as the connection electrode 2 of FIG. 5 and is made of an Al layer (aluminum layer).

A protective film 23 for covering the lower layer electrode 22.
Is a silicon nitride film (Si3N4 film) or a silicon nitride film (Si3N4 film).
It consists of a laminated film of N4 film) and silicon oxide film (SiO2 film).
The openings H1 and H2 of the protective film 23 are provided at both ends of the lower layer electrode 22 along the longitudinal direction. The method of forming the protective film 23 and the openings H1 and H2 is the same as the method described in the conventional example.

Then, in the openings H1 and H2, UBM layers 24A and 24 made of Au / TiW layers are formed on the lower electrode 22.
B is formed. These UBM layers 24A, 24B
Gold bump electrodes 25A and 25B are formed thereon. The UBM layers 24A, 24B and the gold bump electrodes 25A, 2
The method of forming 5B is similar to the method described in the conventional example.

According to the above structure, the pair of gold bump electrodes 25A and 25B are connected to each other through the UBM layers 24A and 24B and the lower layer electrode 22. Therefore, the probe needles 26, 26 are brought into contact with the gold bump electrodes 25A, 25B, respectively, and a predetermined voltage is applied between the probe needles 26, 26 by the voltage source 27.
By measuring the current flowing between 6 and 26, the continuity test between the gold bump electrodes 25A and 25B can be performed. As a result, when there is no conduction, it is found that the high output impedance failure has occurred due to the formation of the high resistance layer 7 described above. Therefore, by performing this continuity test immediately after the bump process, a high output impedance defect can be detected in advance, so that it is possible to take prompt action such as discarding a defective product or improving the process.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing a continuity test structure of a solder bump electrode. In FIG. 2, (A) is a plan view thereof and (B) is a sectional view taken along line ZZ in (A).

The structures of the lower electrode 32, the protective film 33, and the openings H1 and H2 of the protective film 33 are the same as those in the first embodiment, and therefore their explanations are omitted.

Unlike the first embodiment, the UBM layers 34A and 34B are composed of Cu / Cr layers. And this UB
Solder bump electrodes 35A, 35B on the M layers 34A, 34B
Are formed by, for example, a vacuum adsorption method. After this, UB
Solder bump electrodes 35 placed on the M layers 34A and 34B
A and 35B are formed into a spherical shape by reflow processing.

A continuity test method using this solder bump electrode continuity test structure is performed in the same manner as in the first embodiment. That is, the probe needles 36, 36 are brought into contact with the solder bump electrodes 35A, 35B, respectively, and the probe needles 36, 36 are
By applying a predetermined voltage by the voltage source 37 and measuring the current flowing between the probe needles 36, 36, the conduction test between the gold bump electrodes 35A, 35B can be performed. As a result, when there is no conduction, it is found that the high output impedance failure has occurred due to the formation of the high resistance layer 7 described above.

FIG. 3 is a plan view showing a first arrangement example of the bump electrode continuity test structure according to the first and second embodiments described above. LSI chip 60 such as LCD driver
A large number of output terminals 51 are arranged in a row around the. Bump electrode continuity test structure 100 of the present embodiment
Are arranged in the empty area of the output terminal 51. As a result, the bump electrode continuity test structure 100 can be formed without affecting the area of the LSI chip 60.

Regarding the terminals for supplying the power supply voltage,
Two bump electrode terminals may be assigned in consideration of the current capacity. In this case, since the two bump electrode terminals have the same potential, there is no problem even if the terminal structure is the same as the bump electrode continuity test structure according to the first and second embodiments. Therefore, by sharing the bump electrode continuity test structure 100 with the bump electrode terminal for supplying the power supply voltage, it is not necessary to separately provide the bump electrode continuity test structure 100.

FIG. 4 is a plan view showing a second arrangement example of the bump electrode continuity test structure according to the first and second embodiments. A scribe area SL for dividing a plurality of LSI chips 60 in a scribe process is provided on the wafer. Therefore, the bump electrode continuity test structure 100 of the present embodiment is arranged in the scribe region SL of the output terminal 51. Bump electrode continuity test structure 10
Since the continuity test of 0 is performed before the scribing process, there are advantages that the scribe area SL is effectively used and the chip size of the LSI chip 60 is not affected.

[0036]

According to the bump electrode continuity test structure of the present invention, by performing a simple continuity test in a process before a probing test, a high output impedance defect of an output terminal is detected in advance, and a quick response is taken. It becomes possible to take

By forming the entire bump electrode continuity test structure in the scribe region, the continuity test can be conducted without affecting the area of the LSI chip.

Further, by sharing the pair of bump electrodes for the continuity test of the bump electrode continuity test structure with the bump electrodes for applying the power source potential or the ground potential, it is not necessary to separately provide the bump electrode continuity test structure. So LS
The design of I is simplified, and the continuity test can be performed without affecting the area of the LSI chip.

[Brief description of drawings]

FIG. 1 is a diagram showing a continuity test structure of a gold bump electrode according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a conduction test structure of a gold bump electrode according to a second embodiment of the present invention.

FIG. 3 is a plan view showing a first arrangement example of the bump electrode continuity test structure according to the first and second embodiments of the present invention.

FIG. 4 is a plan view showing a second arrangement example of the bump electrode continuity test structure according to the first and second embodiments of the present invention.

FIG. 5 is a diagram showing a gold bump electrode structure according to a conventional example.

FIG. 6 is a block diagram showing an output unit of an LCD driver LSI.

FIG. 7 is a cross-sectional view showing a method for forming a gold bump electrode structure.

FIG. 8 is a cross-sectional view showing a method for forming a gold bump electrode structure.

FIG. 9 is a cross-sectional view showing a method for forming a gold bump electrode structure.

FIG. 10 is a cross-sectional view showing a method for forming a gold bump electrode structure.

FIG. 11 is a cross-sectional view showing a method for forming a gold bump electrode structure.

FIG. 12 is a cross-sectional view showing a method for forming a gold bump electrode structure.

Claims (3)

[Claims] 1. A lower-layer electrode formed on an integrated circuit chip, a protective film covering the lower-layer electrode, a pair of openings provided in the protective film on the lower-layer electrode, and the pair of openings. A bump electrode continuity test structure comprising: a pair of continuity test bump electrodes formed on the exposed lower layer electrode via a UBM layer. 2. The bump electrode continuity test structure according to claim 1, wherein the entire structure is formed in a scribe region of the integrated circuit chip. 3. The bump electrode continuity test structure according to claim 1, wherein the pair of continuity test bump electrodes are also used as power source potential or ground potential application bump electrodes.