CN104037107B

CN104037107B - The failure analysis method of via chain structure

Info

Publication number: CN104037107B
Application number: CN201410253207.XA
Authority: CN
Inventors: 陈强
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2014-06-09
Filing date: 2014-06-09
Publication date: 2017-01-04
Anticipated expiration: 2034-06-09
Also published as: CN104037107A

Abstract

The failure analysis method of the present invention a kind of via chain structure, including: sample to be analyzed is provided, described sample to be analyzed has via chain structure, described via chain includes Semiconductor substrate, metal wire and contacts electrode between Semiconductor substrate with metal wire, and described Semiconductor substrate is with to contact electrical connection between electrode good；Described sample is cut so that the distance of the side that a side of the sample after cutting links with through hole is 1 10 microns；Sample after cutting is carried out plane lapping to the surface exposing metal wire；Depositing metal level at sample surfaces, described metal level covers the surface of metal wire；By metal level ground connection；Sample being put into focusing electron beam, utilizes the direction along the thickness being parallel to Semiconductor substrate that sample is carried out perpendicular cuts, the Semiconductor substrate that will be located in contacting base part is removed, and exposes the bottom of contact electrode；Voltage contrast inefficacy positioning analysis is carried out from bottom docking touched electrode and the metal wire of contact electrode.

Description

The failure analysis method of via chain structure

Technical field

The present invention relates to technical field of semiconductors, particularly relate to the failure analysis method of a kind of via chain structure.

Background technology

In order to find the technological problems in integrated circuit production process as early as possible, different tests is set on a semiconductor die Structure is tested in wafer acceptance test (WAT) to be arrived, and once finds test failure, will carry out failure analysis to confirm The processing step gone wrong, facilitates production line to make improvement in time.

Via chain (CT Chain) structure is a kind of very conventional test structure, is used for monitoring contact electrode and quasiconductor Substrate, and contact electrode contact electrode with this above metal wire between contact resistance size.Refer to Fig. 1, quasiconductor Substrate 11, contact electrode 12 and metal wire 13 constitute via chain structure.If when via chain ruptures, and there is the position of open circuit Semiconductor substrate 11 with contact between electrode 12, then prior art generally uses grinding technics to be removed by metal wire 13, By using the method for voltage contrast (VC) to position between contact electrode 12 and Semiconductor substrate 11, determine and rupture Position.But if it occur that fracture position metal wire 13 with contact between electrode 12, then cannot pass through existing voltage The method of contrast carries out location and the analysis of defect.

Accordingly, it would be desirable to the failure analysis method of a kind of via chain structure, it is possible to for metal wire with contact between electrode The failure analysis of fracture.

Summary of the invention

The present invention solve problem provide a kind of via chain structure failure analysis method, it is possible to for metal wire with contact The failure analysis of the fracture between electrode.

For solving the problems referred to above, the failure analysis method of the present invention a kind of via chain structure, including:

Thering is provided sample to be analyzed, have via chain structure in described sample to be analyzed, described via chain includes that quasiconductor serves as a contrast The end, metal wire and contact electrode between Semiconductor substrate with metal wire, described Semiconductor substrate with contact between electrode Electrical connection is good；

Described sample is cut so that the distance of the side that a side of the sample after cutting links with through hole is 1-10 micron；

Sample after cutting is carried out plane lapping to the surface exposing metal wire；

Depositing metal level at sample surfaces, described metal level covers the surface of metal wire；

By metal level ground connection；

Sample is put into focusing electron beam, utilizes the direction along the thickness being parallel to Semiconductor substrate that sample is carried out vertically Cutting, the Semiconductor substrate that will be located in contacting base part is removed, and exposes the bottom of contact electrode；

Voltage contrast inefficacy positioning analysis is carried out from bottom docking touched electrode and the metal wire of contact electrode.

Alternatively, described ground connection utilizes laser ground connection or conductive tape ground connection.

Alternatively, described metal level utilizes gilding machine to deposit.

Compared with prior art, the invention have the advantages that

The present invention is by the metal level by metal wire disposed thereon ground connection, and is removed by the substrate of contact base part, Contact electrode is exposed, it is achieved that thus contact electrode base docking touched electrode and metal wire carry out voltage contrast lost efficacy location point Analysis.

Accompanying drawing explanation

Fig. 1 is the structural representation of via chain structure；

Fig. 2-Fig. 5 is that the dead methods of the via chain structure of one embodiment of the invention analyzes schematic diagram；

Fig. 6-Fig. 9 is the plan structure schematic diagram of the Semiconductor substrate shown in Fig. 2-Fig. 5.

Detailed description of the invention

By metal level ground connection；

Below in conjunction with embodiment, technical scheme is described in detail.In order to better illustrate the present invention's Technical scheme, refer to the dead methods analysis schematic diagram that Fig. 2-Fig. 5 is the via chain structure of one embodiment of the invention.

First, refer to Fig. 2 and combine Fig. 6, Fig. 6 is the Semiconductor substrate plan structure schematic diagram shown in Fig. 2.Offer is treated Analyzing sample 100, have via chain structure in described sample 100 to be analyzed, described via chain includes Semiconductor substrate 101, gold Belong to line 103 and contact electrode 102 between Semiconductor substrate 101 with metal wire 103, described Semiconductor substrate 101 with connect Between touched electrode 102, electrical connection is good, does not finds to there occurs between electrode 102 with contacting in Semiconductor substrate 101 by analyzing Open circuit.

Then, referring still to Fig. 2 and combine Fig. 6, described sample 100 is cut so that the sample 100 after cutting Distance D of the side that one side links with through hole is 1-10 micron.The purpose carrying out cutting is so that this side and sample Side Distance Shortened, follow-up focusing electron beam carries out perpendicular cuts from this side to sample, and substrate 103 goes the most at last Remove, specifically will be described in detail follow-up.

Then, refer to Fig. 3 and combine Fig. 7, Fig. 7 is the plan structure schematic diagram of the Semiconductor substrate shown in Fig. 3.To cutting Sample 100 after cutting carries out plane lapping to the surface exposing metal wire 103.Described it is ground to cmp.

Then, reference Fig. 4 also combines Fig. 8, and Fig. 8 is the plan structure schematic diagram of the Semiconductor substrate shown in Fig. 4.At sample 100 surface deposition metal levels 104, described metal level 104 covers the surface of metal wire 103.Described metal level 104 utilizes gilding machine Deposition.Metal level 104 is completely covered sample in fig. 8, thus sample is owing to being positioned at below metal level 104, therefore not at figure Shown in.

Then, with continued reference to Fig. 4 and Fig. 8, by metal level 104 ground connection；Described ground connection can utilize laser ground connection or conduction Adhesive tape ground connection.As an embodiment, described ground connection utilizes conductive tape ground connection.

Then, reference Fig. 5 also combines Fig. 9, and Fig. 9 is the plan structure schematic diagram of the Semiconductor substrate shown in Fig. 5.By sample 100 put into focusing electron beam (FIB), utilize the direction along the thickness being parallel to Semiconductor substrate 101 to carry out sample 100 vertically Cutting, will be located in contacting the Semiconductor substrate 101 below electrode 102 and removes, expose the bottom of contact electrode 101.With reference to Fig. 9, Wherein dotted portion is the part having carried out perpendicular cuts, and the sample for this dotted portion is entered by follow-up inefficacy positioning analysis OK.

Finally, voltage contrast inefficacy location is carried out from bottom docking touched electrode 101 and the metal wire 103 of contact electrode 101 Analyze, after utilizing inefficacy positioning analysis, further with SEM or TEM method, sample can be carried out a step analysis.

To sum up, the present invention by depositing the conductive metal layer of ground connection by metal layer, and will contact base part Substrate is removed, and is exposed by contact electrode, it is achieved that thus contact electrode base and dock touched electrode and metal level and carry out voltage contrast Inefficacy positioning analysis.

Therefore, above-mentioned preferred embodiment is only technology design and the feature of the explanation present invention, its object is to allow and is familiar with this The personage of item technology will appreciate that present disclosure and implements according to this, can not limit the scope of the invention with this.All The equivalence change made according to spirit of the invention or modification, all should contain within protection scope of the present invention.

Claims

1. the failure analysis method of a via chain structure, it is characterised in that including:

Thering is provided sample to be analyzed, have via chain structure in described sample to be analyzed, described via chain includes Semiconductor substrate, gold Belong to line and contact electrode between Semiconductor substrate with metal wire, described Semiconductor substrate with contact electrical connection between electrode Well；

Described sample is cut so that a side and the distance of the side of via chain of the sample after cutting are that 1-10 is micro- Rice；

By metal level ground connection；

Sample is put into focusing electron beam, utilizes the direction along the thickness being parallel to Semiconductor substrate that sample is cut, will The Semiconductor substrate being positioned at contact base part is removed, and exposes the bottom of contact electrode；

2. the failure analysis method of via chain structure as claimed in claim 1, it is characterised in that described ground connection utilizes laser to connect Ground or conductive tape ground connection.

3. the failure analysis method of via chain structure as claimed in claim 1, it is characterised in that described metal level utilizes gold-plated Machine deposits.