KR100529630B1 - Semiconductor device with probe pad and method for fabricating the probe pad - Google Patents

Abstract

The present invention relates to a semiconductor device having a probe pad capable of locally inspecting whether there is a defect in a specific site or a defect estimating unit to be electrically inspected, and a method for manufacturing a probe pad of the device, wherein the probe pad includes ( A) removing the upper layer portion of the metal wiring layer by leaving a portion of the insulating film covering the metal wiring layer of the defect estimation part, (B) forming a fine hole in the insulating film to expose the metal wiring layer, and (C) And depositing a conductive material in the micro holes, and (D) depositing a probe pad that is energized with the conductive material.

Description

Semiconductor device having a probe pad and a manufacturing method of the pad {SEMICONDUCTOR DEVICE WITH PROBE PAD AND METHOD FOR FABRICATING THE PROBE PAD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a probe pad for defect inspection and a method of manufacturing the pad, and more particularly, to a probe pad capable of locally inspecting a defect in a specific region or defect estimation unit for which electrical inspection is desired. It relates to a semiconductor device having a and a method for producing a probe pad of the device.

In general, a semiconductor chip is composed of numerous individual elements and metal wires connecting the elements. The completed semiconductor chip has an abnormality through various electrical characteristics and various types of inspection using input / output pads manufactured on the outside of the chip. After the determination, if there is an abnormality, the problem in the manufacturing process is identified, and the action is taken so that no abnormality occurs in the semiconductor chip to be processed later.

However, the inspection of the semiconductor chip as described above focuses on the overall operation of the chip, and does not examine the characteristics of each individual device.

1 is a plan view of a general semiconductor chip, and FIG. 2 is a cross-sectional view illustrating an internal structure of a general semiconductor chip.

The semiconductor chip 100 includes a main cell 102, a guard ring 104 formed outside the cell 102 and serving as a ground, and exposed to the guard ring 104 and connected to circuits inside the chip. The main cell 102 includes a plurality of individual elements 102a provided on the semiconductor substrate W, and metal wires 102b connecting the elements 102a. And a contact 102c and a via 102d for selectively connecting the elements 102a and the metal wires 102b.

In FIG. 2, reference numeral 102e denotes an isolation region and 102f denotes an insulating film.

As described above, since the semiconductor chip is composed of a number of individual elements 102a, when a problem occurs in a specific portion A of some of the individual elements 102a, the semiconductor chip may be used by using an electrical test through the input / output pad 106. Accurately identifying the problem is virtually impossible.

The present invention has been proposed to solve such problems of the prior art, and the present invention provides a semiconductor device having a probe pad capable of inspecting characteristics of a specific portion or individual device of the semiconductor device, and a method of manufacturing the pad. The purpose.

In order to achieve the above technical problem, the present invention,

(A) removing an upper layer portion of the metal wiring layer, leaving a portion of the insulating film covering the metal wiring layer of the defect estimating part by a thickness;

(B) forming fine holes in the insulating film to expose the metal wiring layer;

(C) depositing a conductive material in the micro holes;

(D) depositing a probe pad in electrical communication with the conductive material;

It provides a method for manufacturing a probe pad of a semiconductor device comprising a.

According to a preferred embodiment of the present invention, the upper layer portion of the metal wiring layer in step (A) can be removed by a polishing or chemical etching method. In addition, in the step (B), the fine holes may be formed using focused ion beam equipment (FIB), and the conductive material and the probe pad may be electrochemical deposition, physical vapor deposition, chemical vapor deposition, or focused ion beam equipment. By vapor deposition.

A semiconductor device having a probe pad manufactured by the above method may be connected to an electrical terminal to the probe pad to measure electrical characteristics, thereby inspecting a defect. In addition, after electrically identifying whether a specific site is defective through the above method, it is possible to facilitate additional physical analysis by localizing the defective site.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the semiconductor chip of FIG. 2 in which a metal wiring layer is stacked in multiple layers, a defect of a specific layer suspected of a defect (A: hereinafter, referred to as a "defect estimation unit") is to be examined as shown in FIG. 3A. The insulating layer 102f covering the metal wiring layer 102b of the estimating unit A is partially left by a thickness t, and the upper layer (UL) of the metal wiring layer 102b is removed. In this case, the upper layer UL may be removed by a polishing or chemical etching method, and other methods may be used.

Subsequently, as shown in FIG. 3B, fine holes h are formed in the insulating film 102f to expose the metal wiring layer 102b. At this time, the fine hole (h) may be formed using a known focused ion beam (FIB) equipment.

The focused ion beam equipment (FIB) is a liquid metal ion source made of Ga or the like, a charged particle optical system that uses the ion beam generated from the ion source as a focused ion beam, and deflects the focused ion beam. It includes a deflection electrode and a sample stage on which the sample is placed. The ion beam drawn from the ion source is focused by the charged particle optical system, and the focused ion beam is irradiated onto the sample by the deflection electrode for processing.

After forming the fine holes h exposing the metal wiring layer 102b as described above, as shown in FIG. 3C, the conductive material 102g is deposited to fill the inside of the fine holes h.

In this case, the conductive material 102g may be a metal or a nonmetal. Preferably, for example, any one selected from platinum, gold, silver, copper, aluminum, tungsten, cobalt, nickel, iridium, palladium, rhenium, or alloys thereof may be used, and electrochemical deposition may be performed for the deposition of the conductive material 102g. The focused ion beam equipment used to process vapor deposition, physical vapor deposition, chemical vapor deposition or micro holes h can be used. The vapor deposition using the above-mentioned focused ion beam equipment can be performed by beam assisted CVD which provides a gas nozzle near a sample and supplies gas from the gas nozzle simultaneously with irradiation of the focused ion beam.

Subsequently, the probe pad 102h that conducts electricity to the conductive material 102g is deposited as shown in FIG. 3D by using the focused ion beam equipment. Here, the probe pad 102h may be formed by depositing any material selected from platinum, gold, silver, copper, aluminum, tungsten, cobalt, nickel, iridium, palladium, rhenium, or an alloy thereof, similarly to a conductive material. When the probe pad 102h is deposited on the insulating film 102f as described above, the metal wiring layer 102b is electrically connected to the pad 102h through the conductive material 102g, and thus the electrical terminal is connected to the pad 102h. It is possible to connect the 108 to measure the electrical properties.

As described above, according to the present invention, it is possible to inspect the electrical characteristics of the individual elements constituting the semiconductor chip, and also to inspect whether or not the defect estimation unit is defective, and when the defect occurrence of the defect estimation unit occurs, There is an effect that can be localized to facilitate additional physical analysis.

1 is a plan view of a general semiconductor chip,

2 is a cross-sectional view illustrating a main cell structure of a general semiconductor chip.

3A to 3D are flowcharts illustrating a method for manufacturing a probe pad according to the present invention.

Claims (8)

(A) removing the upper layer portion of the metal wiring layer, leaving a portion of the insulating film covering the metal wiring layer of the defect estimation part by a thickness; (B) forming fine holes in the insulating film using a focused ion beam to expose the metal wiring layer, (C) depositing a conductive material in the micro holes, and (D) depositing a probe pad on the insulating layer, the probe pad passing through the conductive material, using a focused ion beam Probe pad manufacturing method of a semiconductor device comprising a. The method of claim 1, wherein the upper layer portion of the metallization layer is removed by a polishing or chemical etching method in step (A). delete The method of claim 1, wherein the conductive material is deposited in step (C) using electrochemical deposition, physical vapor deposition, chemical vapor deposition, or focused ion beam equipment. delete The semiconductor device of claim 1, wherein the conductive material of step (C) comprises one of platinum, gold, silver, copper, aluminum, tungsten, cobalt, nickel, iridium, palladium, rhenium, or an alloy thereof. Probe pad manufacturing method. The semiconductor device of claim 1, wherein the probe pad of step (D) comprises one of platinum, gold, silver, copper, aluminum, tungsten, cobalt, nickel, iridium, palladium, rhenium, or an alloy thereof. Probe pad manufacturing method. The semiconductor element which has a probe pad manufactured by the method of any one of Claims 1-7.