CN104269391B - A kind of pad structure and preparation method thereof - Google Patents
A kind of pad structure and preparation method thereof Download PDFInfo
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- CN104269391B CN104269391B CN201410490029.2A CN201410490029A CN104269391B CN 104269391 B CN104269391 B CN 104269391B CN 201410490029 A CN201410490029 A CN 201410490029A CN 104269391 B CN104269391 B CN 104269391B
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- pad
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Abstract
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of pad structure and preparation method thereof；By forming enough openings in the fringe region of pad structure, to ensure the connection of pad metal and top metal, resistance capacitance (RC) delay is reduced simultaneously, and open the region without opening when etching the second passivation layer, so as to ensure that Banding PAD do not have residue and with enough flatnesses, enough testing times can be obtained in engineering test, and the oxide of the first passivation layer can be for stop PAD pierce throughs.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of pad structure and preparation method thereof.
Background technology
With continuing to develop for chip testing technology, WAT (Wafer Acceptance are required in processing procedure development
Test, wafer acceptance test) and the number of times of CP (Chip Probing, wafer sort) tests it is more and more, but from current
From the point of view of WAT PAD (pad) and CP PAD designs, it is easy to which, when test is to more than 3 times, PAD upper top metals just expose
Come, after aoxidizing in atmosphere, cause pin and the direct loose contacts of PAD, in turn result in the inaccuracy of test result.
Current PAD's is designed with two kinds of forms, as depicted in figs. 1 and 2, one kind be it is fully open, pad metal 2 directly with
Top metal (Top Metal, TM) 1 is connected, but after WAT/CP is tested more than 3 times, the top metal 1 on PAD can expose
Out.Another is that many through hole/openings (VIA) are opened on PAD, and pad metal 2 is connected by VIA with top metal 1, is pricked in pin
When PAD, PAS1 (Passivation layer1, the first passivation layer) oxide (Oxide, abbreviation OX) can stop pin
Continue to prevent PAD to getting off by pierce through, but this need during pad metal deposition to fill out hole ability, and VIA with certain
Side (Profile) it is not straight, and it is narrow to be open, and is etched in PAS2 (Passivation layer2, the second passivation layer)
When, the OX on VIA sides wall (Sidewall) is difficult that etching is clean, it is easy to cause PAD combine (Banding) not on, and
There are PAD residues (Residue) in OQA (Outgoing Quality Assurance, outgoing control) detection, this is ability
Field technique personnel are hated the sight of.
The content of the invention
For above-mentioned problem, the present invention discloses a kind of pad structure and preparation method thereof.
A kind of pad structure, wherein, including：
Metal layer at top；
First passivation layer, first passivation layer is located on the metal layer at top and with opening；
Pad metal layer, the pad metal layer is located above first passivation layer and by the opening and the top
Portion's metal level is connected；
Second passivation layer, the second passivation layer covering is located at the upper table of the pad metal layer on the opening
Face；
Wherein, fringe region of the opening positioned at the pad structure.
Above-mentioned pad structure, wherein, the pad structure is applied in wafer acceptance test or wafer sort technique.
Above-mentioned pad structure, wherein, the material of the pad metal layer is Al.
Above-mentioned pad structure, wherein, the material of the metal layer at top is Cu.
A kind of preparation method of pad structure, wherein, comprise the following steps：
There is provided one has the semiconductor structure of metal layer at top；
The first passivation layer is formed in the upper surface of the metal layer at top；
First passivation layer is etched, forms opening to be exposed positioned at the metal layer at top of fringe region；
Deposited pad metal level, the pad metal layer is connected by the opening with the metal layer at top；
The second passivation layer is continuously formed to cover the upper surface for the pad metal layer being located on the opening.
The preparation method of above-mentioned pad structure, wherein, the pad structure is applied to wafer acceptance test or wafer
In test technology.
The preparation method of above-mentioned pad structure, wherein, the material of the pad metal layer is Al.
The preparation method of above-mentioned pad structure, wherein, the material of the metal layer at top is Cu.
The preparation method of above-mentioned pad structure, wherein, methods described also includes：
Deposit after the pad metal layer, partial etching is located at the pad metal layer of the overthe openings；
In the passivation layer of disposed thereon second of the opening, and etch second passivation layer, remaining second passivation layer
Covering is located at the upper surface of the pad metal layer on the opening.
Foregoing invention has the following advantages that or beneficial effect：
Pad structure disclosed by the invention and preparation method thereof, by forming enough open in the fringe region of pad structure
Mouthful, to ensure the connection of pad metal and top metal, while reducing resistance capacitance (RC) delay, and etching the second passivation layer
When open the region without opening, so as to ensure that Banding PAD do not have residue and with enough flatnesses, surveyed in engineering
Enough testing times can be obtained in examination, and the oxide of the first passivation layer can be for stop PAD pierce throughs.
Specific brief description of the drawings
By reading the detailed description made with reference to the following drawings to non-limiting example, the present invention and its feature, outside
Shape and advantage will become more apparent.Identical mark indicates identical part in whole accompanying drawings.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is show the purport of the present invention.
Fig. 1 is the welding plate structure schematic that pad metal is directly connected with top metal in background of invention；
Fig. 2 is the welding plate structure schematic that many VIA are provided with background of invention；
Fig. 3 is welding plate structure schematic in the embodiment of the present invention；
Fig. 4-10 is the flowage structure schematic diagram that pad structure is prepared in the embodiment of the present invention.
Embodiment
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
As shown in figure 3, the invention provides a kind of pad structure, can be applied to wafer and be subjected to (WAT) test or wafer
Test in (CP) technique, including：Metal layer at top 101；On metal layer at top 101 and with opening the first passivation layer
1031；The pad metal layer 102 that is connected positioned at the top of the first passivation layer 1031 and by opening with metal layer at top 101 and cover
Lid is located at the second passivation layer 1032 of the upper surface of the pad metal layer 102 on opening；Wherein, opening is positioned at pad structure
Fringe region, specifically, pad structure is divided into intermediate region and the fringe region of the intermediate region is surrounded, wherein, it is middle
Region is the region for carrying out WAT/CP tests, and the present invention sets enough openings to ensure pad in the fringe region of pad structure
Metal and the connection of metal layer at top 101, while reducing RC.And in an embodiment of the present invention, the intermediate region, i.e. WAT/
The overlying regions of CP tests do not cover the second passivation layer 1032, therefore intermediate region is smooth, so as to utilize the first passivation layer
1031 oxide stops the pad structure by pierce through.
It is preferred that, the material of pad metal layer 102 is Al.
It is preferred that, the material of metal layer at top 101 is Cu.
The invention also discloses a kind of preparation method of pad structure, the pad structure prepared by this method can be applied to
Wafer is subjected in (WAT) test or wafer sort (CP) technique, specifically, as shown in figs. 4 through 10, comprising the following steps：
(the semiconductor structure metal layer at top is below 1 there is provided a semiconductor structure with metal layer at top 1 by step S1
Part do not shown in figure), it is preferred that the material of the metal layer at top 1 be Cu；In an embodiment of the present invention, should be partly
Conductor structure is the semiconductor structure for having prepared some semiconductor devices, and preparing the method for the semiconductor structure can use
Technology well-known to those skilled in the art, just it will not go into details herein；Structure as shown in Figure 4.
Step S2, forms the first passivation layer 31, specifically, using chemical vapor deposition in the upper surface of metal layer at top 1
Method in metal layer at top 1 upper surface formed the first passivation layer 31；Structure as shown in Figure 5.
Step S3, etches the first passivation layer 31, forms 4 (some openings) of opening to push up positioned at the part of fringe region 52
Portion's metal level 1 is exposed, structure as shown in Figure 6 a.
Specifically, the semiconductor structure can be divided into intermediate region 51 and the fringe region of the intermediate region 51 is surrounded
52, wherein, intermediate region 51 is the region for carrying out WAT/CP tests, and edge region 52 of the present invention forms enough openings to protect
The connection of pad metal and metal layer at top is demonstrate,proved, while RC is reduced, and in an embodiment of the present invention, the intermediate region 51,
That is the overlying regions of WAT/CP tests do not cover the second passivation layer, therefore intermediate region 51 is smooth, so that blunt using first
Change the oxide of layer to stop pad structure by pierce through, Fig. 6 b are the top view of structure in Fig. 6 a.
Step S4, the deposited pad metal in the upper surface of the first passivation layer 31 and opening 4, and the pad metal is carried out
Flatening process, forms full of opening 4 and covers the pad metal layer 2 of the upper surface of the first passivation layer 31, and the pad metal layer 2
It is connected by opening 4 with metal layer at top 1；It is preferred that, the material of the pad metal layer 2 is Al；Further, using physics
The method of vapour deposition deposits the pad metal；Structure as shown in Figure 7.
Step S5, partial etching is located at the pad metal layer 2 of the top of opening 4, in pad metal layer 2 above the opening
Middle formation groove；Structure as shown in Figure 8.
Step S6, in the second passivation layer of disposed thereon 32 of pad metal layer 2, the second passivation layer 32 is full of groove and covers
The upper surface of pad metal layer 2；Structure as shown in Figure 9.
Step S7, the second passivation layer of partial etching 32 is opened with make it that after etching that the covering of remaining second passivation layer 32 is located at
The upper surface of pad metal layer 2 on mouth 4；It can thus be seen that opening 4 is distributed in the region of the second passivation layer 32 covering；
Structure as shown in Figure 10.
It is seen that, the present embodiment is the embodiment of the method corresponding with the embodiment of above-mentioned pad structure, the present embodiment
Can be worked in coordination implementation with the embodiment of above-mentioned pad structure.The relevant technical details mentioned in the embodiment of above-mentioned pad structure
Still effectively in the present embodiment, in order to reduce repetition, repeat no more here.Correspondingly, the correlation mentioned in present embodiment
Ins and outs are also applicable in the embodiment of above-mentioned package-on-package structure.
To sum up, pad structure disclosed by the invention and preparation method thereof, foot is formed by the fringe region in pad structure
Enough openings, to ensure the connection of pad metal and top metal, while resistance capacitance (RC) delay is reduced, and in etching second
The region without opening is opened during passivation layer, so that ensure that Banding PAD do not have residue and have enough flatnesses,
Enough testing times (being more than 10 times) can be obtained in engineering test, and the oxide of the first passivation layer can be for stop
PAD pierce throughs.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and above-described embodiment can be with
Change case is realized, be will not be described here.Such change case has no effect on the substantive content of the present invention, will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this has no effect on the substantive content of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention still falls within the present invention to any simple modifications, equivalents, and modifications made for any of the above embodiments
In the range of technical scheme protection.
Claims (7)
1. a kind of pad structure, it is characterised in that including：
Metal layer at top；
First passivation layer, first passivation layer is located on the metal layer at top and with opening；
Pad metal layer, the pad metal layer is located above first passivation layer and by the opening and the top-gold
Belong to layer to be connected；The material of the pad metal layer is Al；
Second passivation layer, second passivation layer covers upper tables in the pad metal layer and positioned at the overthe openings
Face；
Wherein, fringe region of the opening positioned at the pad structure.
2. pad structure as claimed in claim 1, it is characterised in that the pad structure be applied to wafer acceptance test or
In wafer sort technique.
3. pad structure as claimed in claim 1, it is characterised in that the material of the metal layer at top is Cu.
4. a kind of preparation method of pad structure, it is characterised in that comprise the following steps：
There is provided one has the semiconductor structure of metal layer at top；
The first passivation layer is formed in the upper surface of the metal layer at top；
First passivation layer is etched, forms opening to be exposed positioned at the metal layer at top of fringe region；
Deposited pad metal level, the pad metal layer is connected by the opening with the metal layer at top；
The second passivation layer is continuously formed to cover the upper surface for the pad metal layer being located on the opening；
Also include：
Deposit after the pad metal layer, partial etching is located at the pad metal layer of the overthe openings；
In the passivation layer of disposed thereon second of the opening, and etch second passivation layer, remaining second passivation layer covering
Upper surfaces in the pad metal layer and positioned at the overthe openings.
5. the preparation method of pad structure as claimed in claim 4, it is characterised in that the pad structure can applied to wafer
In acceptance test or wafer sort technique.
6. the preparation method of pad structure as claimed in claim 4, it is characterised in that the material of the pad metal layer is
Al。
7. the preparation method of pad structure as claimed in claim 4, it is characterised in that the material of the metal layer at top is
Cu。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410490029.2A CN104269391B (en) | 2014-09-23 | 2014-09-23 | A kind of pad structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410490029.2A CN104269391B (en) | 2014-09-23 | 2014-09-23 | A kind of pad structure and preparation method thereof |
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| Publication Number | Publication Date |
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| CN104269391A CN104269391A (en) | 2015-01-07 |
| CN104269391B true CN104269391B (en) | 2017-08-04 |
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| CN201410490029.2A Active CN104269391B (en) | 2014-09-23 | 2014-09-23 | A kind of pad structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108281365A (en) * | 2018-01-24 | 2018-07-13 | 德淮半导体有限公司 | Pad and its manufacturing method for wafer acceptability test |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5700735A (en) * | 1996-08-22 | 1997-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bond pad structure for the via plug process |
| JP2004221417A (en) * | 2003-01-16 | 2004-08-05 | Casio Comput Co Ltd | Semiconductor device and its producing method |
| US9905520B2 (en) * | 2011-06-16 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solder ball protection structure with thick polymer layer |
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