CN104269391A - Bonding pad structure and manufacturing method thereof - Google Patents
Bonding pad structure and manufacturing method thereof Download PDFInfo
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- CN104269391A CN104269391A CN201410490029.2A CN201410490029A CN104269391A CN 104269391 A CN104269391 A CN 104269391A CN 201410490029 A CN201410490029 A CN 201410490029A CN 104269391 A CN104269391 A CN 104269391A
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- pad
- metal layer
- passivation layer
- pad structure
- opening
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a bonding pad structure and a manufacturing method of the bonding pad structure. A sufficient opening is formed in the edge region of the bonding pad structure so as to guarantee the connection between the bonding pad metal and the top metal; meanwhile the resistance-capacitance (RC) delay is reduced, and the region without the opening is opened when a second passivation layer is etched, so that it is guaranteed that no residual slag exists for Banding PAD and sufficient flatness is provided for the Banding PAD, sufficient test times can be obtained in the engineering test, and the oxide of a first passivation layer can be used for preventing the PAD from being penetrated.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of pad structure and preparation method thereof.
Background technology
Along with the development of chip testing technology, WAT (Wafer Acceptance Test is required in processing procedure development, wafer acceptance test) and CP (Chip Probing, wafer sort) number of times tested gets more and more, but design from current WAT PAD (pad) and CP PAD, be easy to when testing to more than 3 times, PAD upper top metal just comes out, in atmosphere after oxidation, cause pin and the direct loose contact of PAD, and then cause the inaccuracy of test result.
Current PAD is designed with two kinds of forms, and as depicted in figs. 1 and 2, one all opens, pad metal 2 directly and top metal (Top Metal, TM) 1 connects, but tests after more than 3 times at WAT/CP, and the top metal 1 on PAD can come out.Another kind PAD opens a lot of through hole/opening (VIA), pad metal 2 is connected with top metal 1 by VIA, when pinprick PAD, PAS1 (Passivation layer1, first passivation layer) oxide (Oxide, be called for short OX) can stop that pin continues to stop PAD to be worn by bundle to getting off, but this need to have during pad metal deposition certain fill out hole ability, and the side of VIA (Profile) is not straight, and opening is narrow, at PAS2 (Passivation layer2, second passivation layer) when etching, it is clean that OX on VIA sidewall (Sidewall) is difficult to etching, be easy to cause PAD to combine (Banding) do not go up, and OQA (Outgoing Quality Assurance, outgoing control) detect on have PAD residue (Residue), this is that those skilled in the art hated the sight of.
Summary of the invention
For above-mentioned Problems existing, the present invention discloses a kind of pad structure and preparation method thereof.
A kind of pad structure, wherein, comprising:
Metal layer at top;
First passivation layer, described first passivation layer to be positioned on described metal layer at top and to have opening;
Pad metal layer, described pad metal layer to be positioned at above described first passivation layer and to be connected with described metal layer at top by described opening;
Second passivation layer, described second passivation layer covers the upper surface of the described pad metal layer be positioned on described opening;
Wherein, described opening is positioned at the fringe region of described pad structure.
Above-mentioned pad structure, wherein, described pad structure is applied in wafer acceptance test or wafer sort technique.
Above-mentioned pad structure, wherein, the material of described pad metal layer is Al.
Above-mentioned pad structure, wherein, the material of described metal layer at top is Cu.
A preparation method for pad structure, wherein, comprises the steps:
The semiconductor structure that one has a metal layer at top is provided;
Upper surface in described metal layer at top forms the first passivation layer;
Etch described first passivation layer, form opening the described metal layer at top being positioned at fringe region to be exposed;
Pad metal deposition layer, described pad metal layer is connected with described metal layer at top by described opening;
Continue formation second passivation layer to cover the upper surface of the described pad metal layer be positioned on described opening.
The preparation method of above-mentioned pad structure, wherein, described pad structure is applied in wafer acceptance test or wafer sort technique.
The preparation method of above-mentioned pad structure, wherein, the material of described pad metal layer is Al.
The preparation method of above-mentioned pad structure, wherein, the material of described metal layer at top is Cu.
The preparation method of above-mentioned pad structure, wherein, described method also comprises:
After depositing described pad metal layer, partial etching is positioned at the pad metal layer of described overthe openings;
In disposed thereon second passivation layer of described opening, and etch described second passivation layer, remaining second passivation layer covers the upper surface of the described pad metal layer be positioned on described opening.
Foregoing invention tool has the following advantages or beneficial effect:
Pad structure disclosed by the invention and preparation method thereof, by forming enough openings at the fringe region of pad structure, to ensure the connection of pad metal and top metal, reduce resistance capacitance (RC) to postpone simultaneously, and open when etching the second passivation layer the region not having opening, thus ensure that Banding PAD does not have residue and has enough flatnesses, can obtain enough testing times in engineering test, and the oxide of the first passivation layer can be used for stopping that PAD bundle is worn.
Concrete accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawing indicates identical part.Proportionally can not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is the pad structure schematic diagram that in background technology of the present invention, pad metal is directly connected with top metal;
Fig. 2 is the pad structure schematic diagram being provided with a lot of VIA in background technology of the present invention;
Fig. 3 is pad structure schematic diagram in the embodiment of the present invention;
Fig. 4-10 is the flowage structure schematic diagrames preparing pad structure in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
As shown in Figure 3, the invention provides a kind of pad structure, can be applicable to wafer and can accept, in (WAT) test or wafer sort (CP) technique, to comprise: metal layer at top 101; To be positioned on metal layer at top 101 and there is the first passivation layer 1031 of opening; To be positioned at above the first passivation layer 1031 and the second passivation layer 1032 of the pad metal layer 102 be connected with metal layer at top 101 by opening and the upper surface that covers the pad metal layer 102 be positioned on opening; Wherein, opening is positioned at the fringe region of pad structure, concrete, pad structure is divided into the fringe region of zone line and this zone line of encirclement, wherein, zone line is the region of carrying out WAT/CP test, and the present invention arranges enough openings to ensure the connection of pad metal and metal layer at top 101 at the fringe region of pad structure, reduces RC simultaneously.And in an embodiment of the present invention, this zone line, i.e. the overlying regions of WAT/CP test does not cover the second passivation layer 1032, and therefore zone line is smooth, thus utilizes the oxide of the first passivation layer 1031 to stop that pad structure is worn by bundle.
Preferably, the material of pad metal layer 102 is Al.
Preferably, the material of metal layer at top 101 is Cu.
The invention also discloses a kind of preparation method of pad structure, the pad structure prepared by the method be can be applicable to wafer and can accept in (WAT) test or wafer sort (CP) technique, concrete, as shown in figs. 4 through 10, comprise the steps:
Step S1, provide the semiconductor structure (part of this semiconductor structure metal layer at top less than 1 is not in shown in figure) that has a metal layer at top 1, preferably, the material of this metal layer at top 1 is Cu; In an embodiment of the present invention, this semiconductor structure is prepared the semiconductor structure having some semiconductor device, and the method preparing this semiconductor structure can adopt technology well-known to those skilled in the art, and at this, just it will not go into details; Structure as shown in Figure 4.
Step S2, the upper surface in metal layer at top 1 forms the first passivation layer 31, concrete, adopts the method for chemical vapour deposition (CVD) to form the first passivation layer 31 in the upper surface of metal layer at top 1; Structure as shown in Figure 5.
Step S3, etches the first passivation layer 31, forms opening 4 (some openings) to be exposed by the atop part metal level 1 being positioned at fringe region 52, structure as shown in Figure 6 a.
Concrete, this semiconductor structure can be divided into the fringe region 52 of zone line 51 and this zone line 51 of encirclement, wherein, zone line 51 is the regions of carrying out WAT/CP test, edge region 52 of the present invention forms enough openings to ensure the connection of pad metal and metal layer at top, reduce RC simultaneously, and in an embodiment of the present invention, this zone line 51, namely the overlying regions of WAT/CP test does not cover the second passivation layer, therefore zone line 51 is smooth, thus utilize the oxide of the first passivation layer to stop that pad structure is worn by bundle, Fig. 6 b is the vertical view of structure in Fig. 6 a.
Step S4, pad metal deposition in the upper surface and opening 4 of the first passivation layer 31, and flatening process is carried out to this pad metal, formed and be full of opening 4 and the pad metal layer 2 covering the first passivation layer 31 upper surface, and this pad metal layer 2 is connected with metal layer at top 1 by opening 4; Preferably, the material of this pad metal layer 2 is Al; Further, the method for physical vapour deposition (PVD) is adopted to deposit this pad metal; Structure as shown in Figure 7.
Step S5, partial etching is positioned at the pad metal layer 2 above opening 4, forms groove in the pad metal layer 2 being arranged in overthe openings; Structure as shown in Figure 8.
Step S6, disposed thereon second passivation layer 32, second passivation layer 32 in pad metal layer 2 is full of groove and covers the upper surface of pad metal layer 2; Structure as shown in Figure 9.
Step S7, partial etching second passivation layer 32, to make to etch the upper surface that rear remaining second passivation layer 32 covers the pad metal layer 2 be positioned on opening 4; This shows, opening 4 is distributed in the region that the second passivation layer 32 covers; Structure as shown in Figure 10.
Be not difficult to find, the present embodiment is the embodiment of the method corresponding with the embodiment of above-mentioned pad structure, and the present embodiment can be worked in coordination with the embodiment of above-mentioned pad structure and be implemented.The relevant technical details mentioned in the embodiment of above-mentioned pad structure is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in present embodiment also can be applicable in the embodiment of above-mentioned package-on-package structure.
To sum up, pad structure disclosed by the invention and preparation method thereof, by forming enough openings at the fringe region of pad structure, to ensure the connection of pad metal and top metal, reduce resistance capacitance (RC) to postpone simultaneously, and open when etching the second passivation layer the region not having opening, thus ensure that Banding PAD does not have residue and has enough flatnesses, can obtain enough testing times (being greater than 10 times) in engineering test, and the oxide of the first passivation layer can be used for stopping that PAD bundle is worn.
It should be appreciated by those skilled in the art that those skilled in the art are realizing change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. a pad structure, is characterized in that, comprising:
Metal layer at top;
First passivation layer, described first passivation layer to be positioned on described metal layer at top and to have opening;
Pad metal layer, described pad metal layer to be positioned at above described first passivation layer and to be connected with described metal layer at top by described opening;
Second passivation layer, described second passivation layer covers the upper surface of the described pad metal layer be positioned on described opening;
Wherein, described opening is positioned at the fringe region of described pad structure.
2. pad structure as claimed in claim 1, it is characterized in that, described pad structure is applied in wafer acceptance test or wafer sort technique.
3. pad structure as claimed in claim 1, it is characterized in that, the material of described pad metal layer is Al.
4. pad structure as claimed in claim 1, it is characterized in that, the material of described metal layer at top is Cu.
5. a preparation method for pad structure, is characterized in that, comprises the steps:
The semiconductor structure that one has a metal layer at top is provided;
Upper surface in described metal layer at top forms the first passivation layer;
Etch described first passivation layer, form opening the described metal layer at top being positioned at fringe region to be exposed;
Pad metal deposition layer, described pad metal layer is connected with described metal layer at top by described opening;
Continue formation second passivation layer to cover the upper surface of the described pad metal layer be positioned on described opening.
6. the preparation method of pad structure as claimed in claim 5, it is characterized in that, described pad structure is applied in wafer acceptance test or wafer sort technique.
7. the preparation method of pad structure as claimed in claim 5, it is characterized in that, the material of described pad metal layer is Al.
8. the preparation method of pad structure as claimed in claim 5, it is characterized in that, the material of described metal layer at top is Cu.
9. the preparation method of pad structure as claimed in claim 5, it is characterized in that, described method also comprises:
After depositing described pad metal layer, partial etching is positioned at the pad metal layer of described overthe openings;
In disposed thereon second passivation layer of described opening, and etch described second passivation layer, remaining second passivation layer covers the upper surface of the described pad metal layer be positioned on described opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410490029.2A CN104269391B (en) | 2014-09-23 | 2014-09-23 | A kind of pad structure and preparation method thereof |
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| CN201410490029.2A CN104269391B (en) | 2014-09-23 | 2014-09-23 | A kind of pad structure and preparation method thereof |
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| CN104269391A true CN104269391A (en) | 2015-01-07 |
| CN104269391B CN104269391B (en) | 2017-08-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108281365A (en) * | 2018-01-24 | 2018-07-13 | 德淮半导体有限公司 | Pad and its manufacturing method for wafer acceptability test |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923088A (en) * | 1996-08-22 | 1999-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure for the via plug process |
| CN1698198A (en) * | 2003-01-16 | 2005-11-16 | 卡西欧计算机株式会社 | Semiconductor device and method of manufacturing the same |
| CN102832188A (en) * | 2011-06-16 | 2012-12-19 | 台湾积体电路制造股份有限公司 | Solder ball protection structure with thick polymer layer |
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2014
- 2014-09-23 CN CN201410490029.2A patent/CN104269391B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923088A (en) * | 1996-08-22 | 1999-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure for the via plug process |
| CN1698198A (en) * | 2003-01-16 | 2005-11-16 | 卡西欧计算机株式会社 | Semiconductor device and method of manufacturing the same |
| CN102832188A (en) * | 2011-06-16 | 2012-12-19 | 台湾积体电路制造股份有限公司 | Solder ball protection structure with thick polymer layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108281365A (en) * | 2018-01-24 | 2018-07-13 | 德淮半导体有限公司 | Pad and its manufacturing method for wafer acceptability test |
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| CN104269391B (en) | 2017-08-04 |
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