CN108630595A - The forming method of silicon hole - Google Patents
The forming method of silicon hole Download PDFInfo
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- CN108630595A CN108630595A CN201710157817.3A CN201710157817A CN108630595A CN 108630595 A CN108630595 A CN 108630595A CN 201710157817 A CN201710157817 A CN 201710157817A CN 108630595 A CN108630595 A CN 108630595A
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- 238000000034 method Methods 0.000 title claims abstract description 77
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 51
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 51
- 239000010703 silicon Substances 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 106
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 229910052751 metal Inorganic materials 0.000 claims abstract description 82
- 239000002184 metal Substances 0.000 claims abstract description 82
- 238000000227 grinding Methods 0.000 claims abstract description 47
- 230000008569 process Effects 0.000 claims abstract description 38
- 238000000137 annealing Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 178
- 230000004888 barrier function Effects 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 41
- 239000010409 thin film Substances 0.000 abstract description 3
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008707 rearrangement Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003701 mechanical milling Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000009172 bursting Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of forming methods of silicon hole, including：There is provided one has trench semiconductor substrate；Extra play and metal layer are formed in the institute's semiconductor substrate and side wall of groove and bottom；Using the metal layer in the first grinding technics removal semiconductor substrate；Annealing process is executed, to discharge the stress of the film layer in semiconductor substrate and semiconductor substrate；The second grinding technics is executed, the extra play is removed.I.e., pass through annealing process, so that the stress in thin film in semiconductor substrate and semiconductor substrate is released, to when executing grinding technics so that film layer to be thinned, it avoids generating an opposite stress in entire semiconductor structure, the phenomenon that improving semiconductor structure back-flexing, the problem of thus preventing the film layer in semiconductor substrate to be broken.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of silicon hole.
Background technology
Silicon hole (Through Silicon Via, TSV) technology realizes the function that the chip of stacking can interconnect, can
The signaling path more section for making total chip chamber of integrated circuit, so as to effectively improve the operation performance of the integrated circuit,
Therefore, more and more silicon hole techniques are applied in the making of semiconductor.
In the preparation process of silicon hole, it is usually formed with multiple film layers on substrate, and formed and passed through in multiple film layers
The groove of multiple film layers is worn, and fills metal layer in the trench, then by mechanical milling tech, planarizes the substrate,
To form silicon hole.However, before executing mechanical milling tech, the overall thickness of film layer formed on a substrate is larger, to
Cause to generate a larger stress in the substrate and on substrate in film layer, entire semiconductor structure is made to bend.Such one
Come, during subsequent execution mechanical lapping, with relatively thin and mechanical stress the effect of thicknesses of layers, easily causes whole
A semiconductor structure back-flexing, and then the film layer in substrate is caused to be broken.
Invention content
The purpose of the present invention is to provide a kind of forming methods of silicon hole, to solve the forming method of existing silicon hole
In, easily cause semiconductor structure to occur to find bending after executing grinding technics, and then the film layer in semiconductor substrate is made to send out
Raw fracture.
In order to solve the above technical problems, the present invention provides a kind of forming method of silicon hole, including：
Semi-conductive substrate is provided, a base is formed in the semiconductor substrate；
A groove is formed, the groove is through the base and extends in the semiconductor substrate；
An extra play is formed in the semiconductor substrate and side wall of the groove and bottom；
In forming a metal layer in the semiconductor substrate, the metal layer fills the groove；
The first grinding technics is executed, the metal layer in the semiconductor substrate is removed；
First time annealing process is executed, to discharge answering for the film layer in the semiconductor substrate and the semiconductor substrate
Power；
After executing the first time annealing process, the second grinding technics is executed, the extra play is removed.
Optionally, first grinding technics includes：
After removing partial metal layers using rough lapping process, recycle remaining in precision lapping process removal semiconductor substrate
Metal layer.
Optionally, before forming the groove, further include：
In a polish stop layer on the interlayer dielectric layer, the extra play covers the polish stop layer and the ditch
The side wall of slot and bottom.
Optionally, after removing the extra play, further include：
Second of annealing process is executed, to discharge the stress in the semiconductor substrate and make the metal layer being located in groove
Protrusion；
Third grinding technics is executed, the metal layer of the polish stop layer and protrusion is removed.
Optionally, the material of the polish stop layer is silicon nitride.
Optionally, the extra play includes a metal barrier.
Optionally, the material of the metal barrier is tantalum or tantalum nitride.
Optionally, the extra play further includes an insulating medium layer, and the forming method of the extra play includes：
In in the semiconductor substrate and insulating medium layer described in the side wall of the groove and bottom；
In forming the metal barrier on the insulating medium layer.
Optionally, the material of the insulating medium layer is silica.
Optionally, second grinding technics includes：
The first grinding is executed, metal barrier and SI semi-insulation dielectric layer are removed；
The second grinding is executed, the insulating medium layer in semiconductor substrate is removed.
Optionally, the material of the metal layer is copper or aluminium.
Optionally, the base includes a device layer and an interlayer dielectric layer.
Optionally, it is formed with transistor in the device layer.
In the forming method of silicon hole provided by the invention, by using annealing process, so that semiconductor substrate and half
Stress in thin film on conductor substrate is released, to when executing grinding technics so that film layer to be thinned, avoid entire half
The phenomenon that generating an opposite stress in conductor structure, improving semiconductor structure back-flexing, thus prevents semiconductor substrate
On film layer the problem of being broken.Also, it can also make the lattice rearrangement in metal layer by the annealing process, with shape
At more stable metal layer, in the subsequent high temperature process, the volume that can avoid the metal layer changes and right
Other film layers impact.Further, the metal layer on removing the semiconductor substrate and then execution annealing process,
The stress that not only can further discharge semiconductor structure can also be such that metal layer is formed after lattice rearrangement a large amount of recessed
Hole highlights, and is conducive to the removal to pit defect, improves the electric conductivity for being formed by silicon hole.
Description of the drawings
Fig. 1 a~1c are a kind of structural schematic diagram of forming method of silicon hole in its manufacturing process；
Fig. 2 is the flow diagram of the forming method of the silicon hole in one embodiment of the invention；
Fig. 3 a~3h are structural representation of the forming method of the silicon hole in one embodiment of the invention in its manufacturing process
Figure.
Specific implementation mode
As stated in the background art, in the forming method of silicon hole, stress changes when due to mechanical lapping in film layer with
And the effect of mechanical stress, the problem of easily film layer being caused to be broken.
A kind of forming method of silicon hole shown in Fig. 1 a~1c is specifically referred to, including：
First, semi-conductive substrate 11 is provided, a device layer 12 and one layer are sequentially formed in the semiconductor substrate 11
Between dielectric layer 13；
Then, a groove 14 is formed, the groove 14 is through the interlayer dielectric layer 13 and the device layer 12 and extends
To in the semiconductor substrate 11；
Then, in forming an extra play 15 and metal layer 16 in the semiconductor substrate 11, the attachment layer 15 covers institute
Side wall and the bottom of semiconductor substrate 11 and groove 14 are stated, the metal layer 16 fills the groove 14；
Metal layer 16 and extra play 15 in the semiconductor substrate 11 are removed using grinding technics, it is logical to form the silicon
Hole.
With reference to shown in figure 1b, grinding technics is being executed with before forming silicon hole, due to shape in the semiconductor substrate
At having device layer 12 and interlayer dielectric layer 13, keep the thickness of total film layer in semiconductor substrate 11 thicker, in entire semiconductor
A larger stress is generated in each film layer in substrate 11 and in semiconductor substrate, is eventually led to and is formed by semiconductor junction
Structure bends.With reference to shown in figure 1c, when executing grinding technics to form silicon hole, with metal layer 16 and the attachment layer
Thinned and mechanical stress the effect of 15 thickness makes to generate in the film layer in semiconductor substrate 11 and semiconductor substrate opposite
Stress, and then lead to be formed by structure back-flexing, and this will further result in the generation of the film layer in semiconductor substrate 11
Fracture, and the device for being formed in semiconductor substrate can be impacted.
For this purpose, the present invention provides a kind of forming method of silicon hole, including：
Semi-conductive substrate is provided, a base is sequentially formed in the semiconductor substrate；
A groove is formed, the groove is through the base and extends in the semiconductor substrate；
An attachment layer is formed in the semiconductor substrate and side wall of the groove and bottom；
In forming a metal layer in the semiconductor substrate, the metal layer fills the groove；
The first grinding technics is executed, the metal layer in the semiconductor substrate is removed；
First time annealing process is executed, to discharge answering for the film layer in the semiconductor substrate and the semiconductor substrate
Power；
After executing the first time annealing process, the second grinding technics is executed, the extra play is removed.
In the forming method of silicon hole provided by the invention, before using the second grinding technics removal extra play, first hold
One annealing process of row, by the annealing process to discharge answering for each film layer in the semiconductor substrate and semiconductor substrate
Power, to during executing the second grinding technics, influence of the mechanical stress to the semiconductor substrate be alleviated, avoid institute
It states semiconductor substrate and back-flexing occurs, and then the film layer in semiconductor substrate can be improved there is a phenomenon where being broken, prevent device
Component graphics in layer shift.
The forming method of silicon hole proposed by the present invention is made further specifically below in conjunction with the drawings and specific embodiments
It is bright.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of
Very simplified form and non-accurate ratio is used, only to mesh that is convenient, lucidly aiding in illustrating the embodiment of the present invention
's.
Fig. 2 is the flow diagram of the forming method of the silicon hole in one embodiment of the invention；Fig. 3 a~3h are the present invention
Structural schematic diagram of the forming method of silicon hole in one embodiment in its manufacturing process.Below in conjunction with Fig. 2 and Fig. 3 a~3h
It is shown, the forming method of the silicon hole in the present embodiment is described in detail.
First, it executes step S1 and provides semi-conductive substrate 110, the semiconductor substrate shown in Fig. 3 a
A base is formed on 110.In the present embodiment, the base includes the device layer being sequentially formed in semiconductor substrate 110
120 and an interlayer dielectric layer 130.
Specifically, transistor 121 is formed in the device layer 120, and the transistor 121 is via a conductive plunger
122 are connected with the semiconductor devices being subsequently formed；The interlayer dielectric layer 130 is formed on the device layer 120, so that described
Device layer 120 and the semiconductor devices for being subsequently formed side thereon are isolated.Wherein, the transistor 121 can pass through metal
It interconnects and realizes itself and the connection for being subsequently formed by semiconductor devices, such as shown in Fig. 3 a, the shape in the interlayer dielectric layer 130
At there is a more metal layers 131, and the metal layer 131 is electrically connected by the way that plug 132 is connected, to the transistor
121 can be electrically connected by the metal layer 132 in conductive plunger 122 connected to it and interlayer dielectric layer 130.To ensure device layer
120 can be effectively isolated with subsequent semiconductor devices, and the thickness of the interlayer dielectric layer 130 is usually thicker, thickness
It can be usually reached hundreds of microns.It can be seen that before forming silicon hole, thickness is already formed in the semiconductor substrate 110
Larger film layer is spent, and then causes to will produce certain answer in each film layer in semiconductor substrate and semiconductor substrate accordingly
Power induces entire semiconductor structure and generates bending.
Further include stopping in one grinding of formation on the interlayer dielectric layer 130 in step sl shown in Fig. 3 a
Layer 140.In the formation process of silicon hole, the metal layer and other films in semiconductor substrate need to be removed by grinding technics
Therefore layer by the way that the polish stop layer 140 is arranged, on the one hand can be improved grinding precision, be conducive to control amount of grinding
System；On the other hand the also film layer below can effectively protect, avoids being damaged.Specifically, the material of the polish stop layer 140
It can be silicon nitride.
Then, step S2 is executed, shown in Fig. 3 b, forms a groove 150, the groove 150 runs through the layer
Between dielectric layer 130 and the device layer 120 and extend in the semiconductor substrate 110.Existing shape can be used in the groove
At method, details are not described herein again.
Then, step S3 is executed, shown in Fig. 3 c, in the semiconductor substrate 110 and the groove 150
Side wall and bottom formed an extra play.Further, the extra play includes a metal barrier 170, the metal barrier
Side wall and the bottom of 170 covering of the layer semiconductor substrate 110 and groove 150.By the metal barrier 170, can keep away
Exempt from the metal layer being subsequently filled in groove 150 and metal ion occurs, the phenomenon that improve leakage current.Wherein, the metal resistance
The material of barrier 150 can be tantalum (Ta) or tantalum nitride (TaN).Further, the extra play further includes a dielectric
Layer 160.At this point, the forming method of the extra play includes：In in the semiconductor substrate 110 and side of the groove 150
Insulating medium layer 160 described in wall and bottom；In forming the metal barrier 170 on the insulating medium layer 160.By institute
It states and forms the insulating medium layer 160 on the side wall and bottom of groove 150, to which the anti-of the interlayer dielectric layer 130 can be improved
Stress ability improves the problem of trenched side-wall described in subsequent grinding technics is broken, to further avoid metal ion
It diffuses in the interlayer dielectric layer 130.
Then, step S4 is executed, shown in Fig. 3 d, in forming a metal layer 180, institute in the semiconductor substrate
It states metal layer 180 and fills the groove 150.The material of the metal layer 180 can be copper or aluminium.
Then, step S5 is executed, shown in Fig. 3 e, the first grinding technics is executed, removes the semiconductor substrate
On metal layer 180.Wherein, first grinding technics can be chemical mechanical milling tech.Preferably, first grinding
Technique includes rough lapping process and precision lapping process, that is, removes the part metal layer 180 by rough lapping process first；It connects
It, remaining metal layer 180 is removed using precision lapping process, the amount of grinding of metal layer 180 can be so more accurately controlled, keep away
Exempt to impact the film layer of 180 lower section of metal layer.
Then, step S6 is executed, first time annealing process is executed, to discharge the semiconductor substrate 110 and described partly lead
The stress of each film layer in body substrate 110.As described above, being formed with device layer 120 and interlayer on semiconductor substrate 110
Dielectric layer 130, and metal barrier and metal layer etc. are also formed on the interlayer dielectric layer 130, it is seen then that it is now placed in
Film layer overall thickness in the semiconductor substrate 110 is thicker, therefore, in the semiconductor substrate 110 and semiconductor substrate 110
Each film layer in will produce a stress, and then entire semiconductor structure is made to bend, and this passes through subsequent grinding work
Totally unfavorable influence can be generated to the semiconductor structure after skill.For semiconductor substrate and semiconductor substrate can be effectively relieved
The stress of upper each film layer, in the present embodiment, before removal metal layer 180 and grinding technics continuous after execution, preferentially
An annealing process is executed, to discharge the stress of each film layer in semiconductor substrate and semiconductor substrate, to avoid film layer
It is ground under conditions of with larger stress.
Then, step S7 is executed, shown in Fig. 3 f, the second grinding technics is executed, removes in semiconductor substrate
The metal barrier 170.In the present embodiment, by second grinding technics, the dielectric can be also further removed
Layer 160.Specifically, first, executing the first grinding, removing metal barrier 170 and SI semi-insulation dielectric layer 160；Then, it executes
Second grinding, removes the insulating medium layer 160 in semiconductor substrate 110.Due to the insulating medium layer 160 thickness usually compared with
Thickness, therefore the metal barrier 170 and insulating medium layer 160 are removed by two step process of lapping, it can ensure grinding quality.This
Outside, in the present embodiment, the lower section of the insulating medium layer 160 is also formed with the polish stop layer 140, to execute second
When grinding technics, can the polish stop layer 140 be grinding endpoint, cause to damage to avoid the film layer to lower section.
Then, step S8 is executed, second of annealing process is executed, shown in Fig. 3 g, to discharge the semiconductor
Stress in substrate 110 simultaneously makes 180 protrusion of the metal layer being located in groove 150.The metal layer 180 is by high-temperature thermal annealing
Later, internal lattice meeting rearrangement, and the volume of metal layer 180 is made to increase, therefore, the metal layer 180 can be from institute
It is projecting inward to state groove 150.
In general, after forming the silicon hole, also need to execute subsequent flow, including part high temperature process, warp
After crossing high temperature process, since the volume of metal layer 180 increases, it can usually make the film layer of 150 top of groove by bursting.Therefore, exist
When forming silicon hole, increase annealing process to remove the stress in metal layer 180, and make lattice in metal layer 180 preferentially into
The arrangement of row again, to form more stable lattice situation, thus, in the subsequent high temperature process, due to metal layer
180 be the state of stabilization, and the volume of metal layer 180 will not change again, and then can avoid causing shadow to other film layers
It rings.
In addition, after by high temperature process volume change, and the metal layer 180 can not only occur for metal layer 180
Upper surface on the defects of also will produce a large amount of pit, and then the performance of the silicon hole can be influenced.Therefore, the present embodiment
In, by annealing process so that metal layer 180 is raised, also, a large amount of pit can be formed accordingly on the surface of protrusion, rear
In continuous grinding technics, the protrusion is further removed, so as to eliminate the pit of 180 upper surface of metal layer, improves institute's shape
At silicon hole electric conductivity.
Then, step S9 is executed, shown in Fig. 3 h, third grinding technics is executed, removes the polish stop layer
140 and protrusion metal layer, to form silicon hole.That is, in the present embodiment, by secondary annealing process in third grinding technics
It carries out, is not only can get with the metal layer 180 for stablizing lattice arrangement and further release semiconductor substrate 110 and half before
The stress of film layer on conductor substrate 110, also, can also save a step process of lapping.
In conclusion in the forming method of silicon hole provided by the invention, by using annealing process, so that semiconductor serves as a contrast
Stress in thin film on bottom and semiconductor substrate is released, to when executing grinding technics so that film layer to be thinned, avoid
The phenomenon that generating an opposite stress in entire semiconductor structure, improve semiconductor structure back-flexing, partly leads so as to place
The problem of film layer in body substrate is broken.Also, by the annealing process lattice in metal layer can also arranged again
Cloth, to form more stable metal layer, to which in the subsequent high temperature process, the volume that can avoid the metal layer becomes
Change and other film layers are impacted.Further, the metal layer on removing the semiconductor substrate and then annealing is executed
Technique not only can further discharge the stress of semiconductor structure, also metal layer can be made to be formed after lattice rearrangement
A large amount of pits highlight, and are conducive to the removal to pit defect, improve the electric conductivity for being formed by silicon hole.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (12)
1. a kind of forming method of silicon hole, which is characterized in that including：
Semi-conductive substrate is provided, a base is formed in the semiconductor substrate；
A groove is formed, the groove is through the base and extends in the semiconductor substrate；
An extra play is formed in the semiconductor substrate and side wall of the groove and bottom；
In forming a metal layer in the semiconductor substrate, the metal layer fills the groove；
The first grinding technics is executed, the metal layer in the semiconductor substrate is removed；
First time annealing process is executed, to discharge the stress of the film layer in the semiconductor substrate and the semiconductor substrate；
After executing the first time annealing process, the second grinding technics is executed, the extra play is removed.
2. the forming method of silicon hole as described in claim 1, which is characterized in that before forming the groove, further include：
In a polish stop layer on the interlayer dielectric layer, the extra play covers the polish stop layer and the groove
Side wall and bottom.
3. the forming method of silicon hole as claimed in claim 2, which is characterized in that after removing the extra play, also wrap
It includes：
Second of annealing process is executed, to discharge the stress in the semiconductor substrate and keep the metal layer being located in groove convex
It rises；
Third grinding technics is executed, the metal layer of the polish stop layer and protrusion is removed.
4. the forming method of silicon hole as claimed in claim 2, which is characterized in that the material of the polish stop layer is nitridation
Silicon.
5. the forming method of silicon hole as described in claim 1, which is characterized in that the extra play includes a metal barrier
Layer.
6. the forming method of silicon hole as claimed in claim 5, which is characterized in that the material of the metal barrier be tantalum or
Tantalum nitride.
7. the forming method of silicon hole as claimed in claim 5, which is characterized in that the extra play further includes a dielectric
Layer, the forming method of the extra play include：
In in the semiconductor substrate and insulating medium layer described in the side wall of the groove and bottom；
In forming the metal barrier on the insulating medium layer.
8. the forming method of silicon hole as claimed in claim 7, which is characterized in that the material of the insulating medium layer is oxidation
Silicon.
9. the forming method of silicon hole as claimed in claim 7, which is characterized in that second grinding technics includes：
The first grinding is executed, metal barrier and SI semi-insulation dielectric layer are removed；
The second grinding is executed, the insulating medium layer in semiconductor substrate is removed.
10. the forming method of silicon hole as described in claim 1, which is characterized in that the material of the metal layer is copper or aluminium.
11. the forming method of silicon hole as described in claim 1, which is characterized in that the base includes a device layer and one
Interlayer dielectric layer.
12. the forming method of silicon hole as claimed in claim 11, which is characterized in that be formed with crystal in the device layer
Pipe.
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| CN201710157817.3A CN108630595A (en) | 2017-03-16 | 2017-03-16 | The forming method of silicon hole |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111207828A (en) * | 2019-12-31 | 2020-05-29 | 中国科学院微电子研究所 | Thermopile, preparation method thereof and detector |
| CN112201616A (en) * | 2020-09-21 | 2021-01-08 | 上海华力集成电路制造有限公司 | Method for improving copper hillock in copper interconnection process |
| CN112563194A (en) * | 2020-12-04 | 2021-03-26 | 武汉新芯集成电路制造有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465492A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of through-silicon via structure and manufacturing method of integrated circuit |
| CN104795355A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole structure manufacturing method |
| CN105575828A (en) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
-
2017
- 2017-03-16 CN CN201710157817.3A patent/CN108630595A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465492A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of through-silicon via structure and manufacturing method of integrated circuit |
| CN104795355A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole structure manufacturing method |
| CN105575828A (en) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111207828A (en) * | 2019-12-31 | 2020-05-29 | 中国科学院微电子研究所 | Thermopile, preparation method thereof and detector |
| CN112201616A (en) * | 2020-09-21 | 2021-01-08 | 上海华力集成电路制造有限公司 | Method for improving copper hillock in copper interconnection process |
| CN112563194A (en) * | 2020-12-04 | 2021-03-26 | 武汉新芯集成电路制造有限公司 | Semiconductor structure and manufacturing method thereof |
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