JP2009182133A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that can improve reliability and manufacturing yield. <P>SOLUTION: The method of manufacturing the semiconductor device includes the processes of: forming a transistor 33 having a gate electrode 24 and a source/drain diffusion layer 32 on a first principal surface of a semiconductor substrate 10; forming a first insulating film 38 on the first principal surface of the semiconductor substrate and on the transistor; forming a contact hole 40 reaching the gate electrode in the first insulating film; forming conductive films 42 and 44 by a plasma CVD method in the contact hole and on the first insulating film; and polishing the conductive films until a surface of the first insulating film is exposed and burying a conductor plug 44 including a conductive film in the contact hole. Further, the method of manufacturing the semiconductor device includes the process of etching away the portion of a second insulating film, present on a second principal surface on the opposite side from the first principal surface, at a peripheral edge of the second principal surface before the process of forming the conductive films. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of improving reliability and manufacturing yield.

  Recently, it has been proposed to use Cu as a wiring material in order to reduce wiring resistance.

  For wiring made of Cu, a groove for embedding the wiring is formed in the interlayer insulating film, a Cu film is formed on the interlayer insulating film by electroplating, and the Cu film is polished until the surface of the interlayer insulating film is exposed. As a result, it is embedded in the groove.

  When forming a Cu film by electroplating, the back surface of the semiconductor substrate is to prevent the Cu in the plating bath from diffusing into the semiconductor substrate from the back surface (second main surface) side of the semiconductor substrate. An insulating film is previously formed on the side. When Cu diffuses in the semiconductor substrate, the electrical characteristics of the transistor and the like may deteriorate due to the Cu diffused in the semiconductor substrate, but such an insulating film is formed on the back side of the semiconductor substrate. Then, Cu can be prevented from diffusing into the semiconductor substrate, so that it is possible to prevent deterioration of electrical characteristics of the transistor and the like.

In addition, as the background art of the present invention, there are the following.
JP 2005-93646 A JP 2002-334927 A

  However, when an insulating film is formed on the back surface side of the semiconductor substrate, the insulating film is insulated in the gate insulating film of the transistor when the conductive film is formed on the front surface (first main surface) side of the semiconductor substrate by plasma CVD or the like. In some cases, destruction may occur, and reliability and manufacturing yield may be lowered.

  An object of the present invention is to provide a semiconductor device manufacturing method capable of improving reliability and manufacturing yield.

  According to one aspect of the present invention, a step of forming a transistor having a gate electrode and a source / drain diffusion layer on a first main surface of a semiconductor substrate, and on the first main surface of the semiconductor substrate; Forming a first insulating film on the transistor; forming a contact hole reaching the gate electrode in the first insulating film; and in the contact hole and on the first insulating film, Forming a conductive film by a plasma CVD method; and polishing the conductive film until a surface of the first insulating film is exposed and embedding a conductor plug including the conductive film in the contact hole. And before the step of forming the conductive film, of the second insulating film existing on the second main surface, which is the surface opposite to the first main surface, the periphery of the second main surface The second insulating film present in the part The method of manufacturing a semiconductor device characterized by further comprising a step of etching removal is provided.

  According to the present invention, the second insulating film at the peripheral edge of the second main surface of the semiconductor substrate is removed by etching. For this reason, when the conductive film is formed by a plasma CVD method in a subsequent process, electric charges are supplied into the semiconductor substrate via the peripheral edge portion of the second main surface of the semiconductor substrate. Therefore, according to the present invention, even when a large amount of charge is accumulated in the gate electrode when the conductive film is formed by the plasma CVD method, the potential of the gate electrode is significantly higher than the potential of the semiconductor substrate. It becomes possible to prevent becoming. For this reason, according to the present invention, it is possible to prevent the dielectric breakdown of the gate insulating film and to improve the manufacturing yield.

[One Embodiment]
A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 11 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, as shown in FIG. 1A, a semiconductor substrate (semiconductor wafer) 10 is prepared. For example, a silicon substrate (silicon wafer) is used as the semiconductor substrate 10.

  Next, a silicon oxide film 12 having a thickness of 10 to 15 nm is formed on the entire surface by, eg, thermal oxidation. The silicon oxide film 12 is formed so as to cover the entire surface of the semiconductor substrate 10. That is, the silicon oxide film 12 is formed so as to cover the first main surface (upper surface) of the semiconductor substrate 10, the second main surface (lower surface) of the semiconductor substrate 10, and the outer periphery of the semiconductor substrate 10. The first main surface of the semiconductor substrate 10 is a surface on the side where a transistor 33 (see FIG. 4C) to be described later is formed. The second main surface of the semiconductor substrate 10 is a surface opposite to the first main surface.

  Next, as shown in FIG. 1B, a silicon nitride film 14 having a thickness of 80 to 90 nm is formed by, eg, thermal CVD. The silicon nitride film 14 is formed so as to cover the entire surface of the semiconductor substrate 10. That is, the silicon nitride film 14 is formed so as to cover the first main surface (upper surface) of the semiconductor substrate 10, the second main surface (lower surface) of the semiconductor substrate 10, and the outer periphery of the semiconductor substrate 10.

  Next, as shown in FIG. 1C, a silicon oxide film 16 having a film thickness of 300 to 400 nm is formed by, eg, thermal CVD. The silicon oxide film 16 is formed so as to cover the entire surface of the semiconductor substrate 10. That is, the silicon oxide film 16 is formed so as to cover the first main surface (upper surface) of the semiconductor substrate 10, the second main surface (lower surface) of the semiconductor substrate 10, and the outer periphery of the semiconductor substrate 10.

  Next, as shown in FIG. 2A, the silicon oxide film 16 on the first main surface (upper surface) side of the semiconductor substrate 10 is removed by etching, for example, by wet etching. When the silicon oxide film 16 on the first main surface side of the semiconductor substrate 10 is removed by etching, the silicon nitride film 14 functions as an etching stopper.

  Next, a photoresist film (not shown) is formed on the entire surface of the first main surface (upper surface) of the semiconductor substrate 10 by spin coating.

  Next, an opening (not shown) is formed in the photoresist film using a photolithography technique. Such an opening is for forming a groove 17 (see FIG. 2B) in the semiconductor substrate 10.

  Next, the silicon nitride film 14 is etched using the photoresist film as a mask. Thereby, a hard mask made of the silicon nitride film 14 is formed.

  Next, the silicon oxide film 12 and the semiconductor substrate 10 are etched using the photoresist film and the silicon nitride film 14 as a mask. Thereby, a groove 17 is formed in the semiconductor substrate 10. The groove 17 is for forming an element isolation region 18 (see FIG. 2C). The depth of the groove 17 is, for example, 300 nm.

  Next, a silicon oxide film is formed on the entire surface by plasma CVD. The film thickness of the silicon oxide film is, for example, 500 nm.

  Next, the silicon oxide film is polished by CMP (Chemical Mechanical Polishing) until the surface of the silicon nitride film 14 is exposed. As a result, an element isolation region 18 made of a silicon oxide film is formed in the trench 17 (see FIG. 2C).

  Next, the silicon nitride film 14 existing on the first main surface (upper surface) side of the semiconductor substrate 10 is removed by etching using, for example, phosphoric acid. At this time, since the silicon oxide film 16 exists on the second main surface (lower surface) side of the semiconductor substrate 10, the silicon nitride film 14 on the second main surface side of the semiconductor substrate 10 is not etched. Remains.

  Next, the silicon oxide film 12 present on the first main surface side of the semiconductor substrate 10 is removed by etching using, for example, hydrofluoric acid.

  Thus, the element isolation region 18 that defines the element region 20 is formed (see FIG. 3A).

  Next, a photoresist film (not shown) is appropriately formed on the first main surface of the semiconductor substrate 10, and dopant impurities are introduced into the semiconductor substrate 10 using the photoresist film as a mask, thereby forming a well (FIG. (Not shown).

  Next, the gate insulating film 22 is formed on the first main surface of the semiconductor substrate 10 by, eg, thermal oxidation. The film thickness of the gate insulating film 22 is 2 nm, for example.

  Next, a polysilicon film 24 is formed on the entire surface by, eg, thermal CVD. The film thickness of the polysilicon film 24 is, for example, 100 nm. The polysilicon film 24 is formed so as to cover the entire surface of the semiconductor substrate 10. That is, the polysilicon film 24 is formed so as to cover the first main surface (upper surface) of the semiconductor substrate 10, the second main surface (lower surface) of the semiconductor substrate 10, and the outer periphery of the semiconductor substrate 10.

  Next, the polysilicon film 24 present on the second main surface side of the semiconductor substrate 10 is removed by wet etching.

  Next, the silicon oxide film 16 existing on the second main surface side of the semiconductor substrate 10 is removed by wet etching.

  Next, the polysilicon film 24 existing on the first main surface side of the semiconductor substrate 10 is patterned by using a photolithography technique. Thereby, the gate electrode 24 made of polysilicon is formed (see FIG. 3B).

  Next, by introducing a dopant impurity into the semiconductor substrate 10 using the gate electrode 24 as a mask, an extension region 26 constituting a shallow region of the extension source / drain structure is formed in the semiconductor substrate 10 on both sides of the gate electrode 24. (See FIG. 3C).

  Next, as shown in FIG. 4A, a silicon oxide film 28 is formed on the entire surface by TEOS-CVD. The silicon oxide film 28 is formed so as to cover the entire surface of the semiconductor substrate 10. That is, the silicon oxide film 28 is formed so as to cover the first main surface (upper surface) of the semiconductor substrate 10, the second main surface (lower surface) of the semiconductor substrate 10, and the peripheral portion of the semiconductor substrate 10. The silicon oxide film 28 becomes a sidewall insulating film (sidewall spacer).

  Next, as shown in FIG. 4B, the silicon oxide film 28 is anisotropically etched using, for example, a single-wafer plasma etching apparatus. As a result, a sidewall insulating film 28 made of a silicon oxide film is formed on the side wall portion of the gate electrode 24. The silicon oxide film 28 on the second main surface side of the semiconductor substrate 10 remains without being etched.

  Next, a dopant impurity is introduced into the semiconductor substrate 10 using the gate electrode 24 with the sidewall insulating film 28 formed as a mask, thereby forming a deep region of the source / drain diffusion layer 32 of the extension source / drain structure. Impurity diffusion region 30 is formed. The deep impurity diffusion region 30 and the shallow impurity diffusion region 26 form a source / drain diffusion layer 32 having an extension source / drain structure.

  Thus, the transistor 33 having the gate electrode 24 and the source / drain diffusion layer 32 is formed.

  Next, using the bevel etching apparatus 100 (see FIG. 12), the silicon oxide film 28, the silicon nitride film 14, and the silicon oxide film 12 at the peripheral edge of the second main surface (lower surface) of the semiconductor substrate 10 are removed by etching.

  The bevel etching apparatus 100 is an apparatus for selectively etching an insulating film or the like on the peripheral edge of a semiconductor wafer. As the bevel etching apparatus 100, for example, a bevel etching apparatus (model number: 2300 Bevel) manufactured by Lam Research Co., Ltd. can be used.

  FIG. 12 is a schematic view showing a bevel etching apparatus.

  As shown in FIG. 12, a disc-like mounting table (electrode) 102 for mounting the semiconductor wafer 10 is provided in the chamber 101. The mounting table 102 is supplied with high frequency power (RF power).

  An insulating member 104 is provided in a ring shape on the periphery of the mounting table 102. As a material of the insulating member 104, for example, ceramic is used.

  A first ground electrode 106 is provided in a ring shape on the periphery of the mounting table 102 surrounded by the insulating member 104. The first ground electrode 106 is connected to the ground.

  A top plate 108 made of ceramic, for example, is provided above the mounting table 102. A second ground electrode 110 is provided on the top plate 108.

  A ring-shaped third ground electrode 112 is provided on the periphery of the top plate 108. The third ground electrode 112 is connected to the second ground electrode 110.

  The second ground electrode 110 and the third ground electrode 112 are connected to the ground.

  A gas inlet 114 is provided in the top plate 108 and the second ground electrode 110. A gas for generating plasma is introduced into the chamber 101 through the gas inlet 114.

  When high frequency power is applied to the mounting table 102 of such a bevel etching apparatus 100, plasma 116 is generated in a ring shape as a whole as shown in FIG. The plasma 116 includes a portion where the semiconductor substrate 10 and the first ground electrode 106 face each other, a portion where the semiconductor substrate 10 and the third ground electrode 112 face each other, and the first ground electrode 106 and the first ground electrode 106. 3 is generated at a portion facing the ground electrode 112.

The conditions for performing the bevel etching are, for example, as follows. A distance t between the first main surface (upper surface) of the semiconductor substrate 10 and the lower surface of the top plate 108 is set to 0.3 to 0.5 mm. Width D ₁ of the area and the peripheral portion overlapping the second major surface of the first ground electrode 106 and the semiconductor substrate 10 a ring-shaped surface (lower surface) is, for example, 2 mm. Depending on the width D ₁ of the region where the peripheral portion opposite the second major surface of the first ground electrode 106 and the semiconductor substrate 10 a ring-shaped surface (lower surface), the peripheral edge portion of the second major surface of the semiconductor substrate 10 Then, the silicon oxide film 12, the silicon nitride film 14, and the silicon oxide film 28 are etched. A width D2 of a region where the ring-shaped third ground electrode 112 and the peripheral portion of the first main surface (upper surface) of the semiconductor substrate 10 face _{each other} is, for example, 0.5 mm. The pressure in the chamber 101 is, for example, 0.5 Torr to 3 Torr. The high frequency power applied to the mounting table 102 is, for example, 300 to 1000 W. The flow rate of CF ₄ gas introduced into the chamber 101 is 50 to 200 sccm. The flow rate of the N ₂ gas introduced into the chamber 101 is, for example, 50 to 200 sccm. The etching time is, for example, 10 seconds. The etching time of 10 seconds is an etching time equivalent to 400 nm in terms of the etching amount of the silicon oxide film.

  Thus, the silicon oxide film 28, the silicon nitride film 14, and the silicon oxide film 12 are removed by etching at the peripheral edge portion of the second main surface of the semiconductor substrate 10. At the peripheral edge portion of the second main surface of the semiconductor substrate 10, the second main surface of the semiconductor substrate 10 is exposed.

Here, although described width D ₁ of the overlapping region and the peripheral portion of the first ground electrode 106 and the semiconductor substrate 10 a ring-shaped as an example the case of a 2 mm, ring-shaped first ground electrode 106 the width D ₁ of the region where the peripheral edge facing the second major surface of the semiconductor substrate 10 (lower surface) is not limited to 2 mm. Width D ₁ of the region where the peripheral portion of the second major surface of the first ground electrode 106 and the semiconductor substrate 10 a ring-shaped faces, for example is preferably set to 1 to 3 mm.

When the width D1 of the region where the ring-shaped first ground electrode 106 and the peripheral portion of the semiconductor substrate 10 overlap is smaller than ₁ mm, the silicon oxide film 28 and the silicon nitride film etched at the peripheral portion of the semiconductor substrate 10 14 and the silicon oxide film 12 become extremely narrow. In this case, it becomes difficult to supply charges to the semiconductor substrate 10 through the peripheral edge portion of the second main surface of the semiconductor substrate 10 when the conductive film 42 and the like are formed by a plasma CVD method in a subsequent process. . In this case, when the gate electrode 24 is charged with a large amount of charge when forming the conductive film 42 or the like by the plasma CVD method, the potential of the gate electrode 24 becomes extremely higher than the potential of the semiconductor substrate 10. while there is a possibility that dielectric breakdown of the gate insulating film 22 occurs, when the width D ₁ of the area and the peripheral portion overlapping the first ground electrode 116 and the semiconductor substrate 10 having a ring shape larger 3mm, the semiconductor The area of the semiconductor substrate 10 that can be used for manufacturing the device (semiconductor chip) is reduced, leading to an increase in the manufacturing cost of the semiconductor device.

For this reason, the width D ₁ of the area and the peripheral portion overlapping the first ground electrode 116 and the semiconductor substrate 10 a ring-shaped, for example it is preferable that the 1 to 3 mm.

When etching is performed using the bevel etching apparatus 100 in this manner, the silicon oxide film 28, the silicon nitride film 14, and the silicon oxide film 12 have a predetermined width D at the peripheral edge portion of the second main surface of the semiconductor substrate 10. ₁ is etched (see FIG. 5A). A laminated film 29 composed of the silicon oxide film 12, the silicon nitride film 14, and the silicon oxide film 28 exists in the region excluding the peripheral edge portion of the second main surface of the semiconductor substrate 10.

  Next, a refractory metal film is formed on the entire surface by, eg, sputtering. Thereby, a refractory metal film is formed on the first main surface of the semiconductor substrate 10. As a material for the refractory metal film, for example, a nickel film is used. The film thickness of the refractory metal film is, for example, 20 nm.

  Next, by performing heat treatment, Ni atoms in the refractory metal film react with Si atoms in the silicon substrate 10 to form a metal silicide film 34a made of nickel silicide. Further, Ni atoms in the refractory metal film are reacted with Si atoms in the gate electrode 24 to form a metal silicide film 34b made of nickel silicide.

  Next, the unreacted refractory metal film is removed by etching. Thus, the source / drain electrode 34 a made of the metal silicide film is formed on the source / drain diffusion layer 32. A metal silicide film 34b is also formed on the gate electrode 24 (see FIG. 5B).

  Next, as shown in FIG. 5C, a silicon nitride film 36 is formed on the entire surface by, eg, CVD. The silicon nitride film 36 functions as an etching stopper film when the contact hole 40 is formed in the interlayer insulating film 38. The film thickness of the silicon nitride film 36 is, for example, 80 nm.

  Next, an interlayer insulating film 38 made of, eg, a silicon oxide film is formed by, eg, CVD. The film thickness of the interlayer insulating film 38 is 600 nm, for example. The silicon oxide film 38 is formed not only on the first main surface (upper surface) of the semiconductor substrate 10 with a desired thickness but also on the peripheral portion of the second main surface (lower surface) of the semiconductor substrate 10. A thin film is formed. Thus, a silicon oxide film 38 having a thickness of, for example, about 100 nm is formed on the peripheral edge portion of the second main surface of the semiconductor substrate 10. The film thickness of the silicon oxide film 38 formed on the peripheral portion of the second main surface of the semiconductor substrate 10 is the film of the stacked film 29 existing in a region other than the peripheral portion of the second main surface of the semiconductor substrate 10. Thin enough for thickness. For this reason, when the conductive film 42 is formed by a plasma CVD method in a subsequent process, electric charges are transferred into the semiconductor substrate 10 via the relatively thin silicon oxide film 38 at the peripheral edge of the second main surface of the semiconductor substrate 10. Supplied. For this reason, according to the present embodiment, even when a large amount of charge is accumulated in the gate electrode 24, it is possible to prevent the potential of the gate electrode 24 from extremely rising with respect to the potential of the semiconductor substrate 10. Is possible.

  Next, the surface of the interlayer insulating film 38 is planarized by polishing the surface of the interlayer insulating film 38 by CMP. The thickness of the interlayer insulating film 38 to be polished is about 300 nm, for example. As a result, the step formed on the surface of the interlayer insulating film 38 due to the gate electrode 24 is eliminated.

  Next, a photoresist film (not shown) is formed on the first main surface (upper surface) of the semiconductor substrate 10 by, eg, spin coating.

  Next, an opening (not shown) for forming the contact hole 40 is formed in the photoresist film using a photolithography technique.

  Next, contact holes 40 are formed using the photoresist film as a mask and the silicon nitride film 36 as an etching stopper.

  Next, the silicon nitride film 36 exposed in the contact hole 40 is etched. Thus, a contact hole 40 reaching the source / drain electrode 34a and a contact hole 40 reaching the silicide film 34b on the gate electrode 24 are formed in the interlayer insulating film 38 (see FIG. 6B).

  Next, a Ti film having a thickness of 10 nm is formed on the first main surface of the semiconductor substrate 10 by plasma CVD, for example.

  Next, a 10 nm-thick TiN film is formed on the first main surface of the semiconductor substrate 10 by, for example, plasma CVD. Thus, a barrier metal film (conductive film) 42 composed of the Ti film and the TiN film is formed by the plasma CVD method (see FIG. 7A).

  The film thickness of the silicon oxide film 38 present on the peripheral portion of the second main surface of the semiconductor substrate 10 is a laminated film (insulating) existing in a region other than the peripheral portion of the second main surface of the semiconductor substrate 10. The film) is sufficiently thin with respect to the film thickness of 29. Accordingly, when the barrier metal film (conductive film) 42 is formed by the plasma CVD method, electric charges are supplied into the semiconductor substrate 10 through the silicon oxide film 38 present at the peripheral edge of the second main surface of the semiconductor substrate 10. Is done. Therefore, when the barrier metal film (conductive film) 42 is formed by the plasma CVD method, even if a large amount of charges are accumulated in the gate electrode 24, the potential of the gate electrode 24 with respect to the potential of the semiconductor substrate 10. It is possible to prevent the potential from being extremely increased, and it is possible to prevent the dielectric breakdown of the gate insulating film 22.

  Next, as shown in FIG. 7B, a tungsten film 44 is formed on the first main surface (upper surface) of the semiconductor substrate 10 by, for example, plasma CVD.

  As described above, the thickness of the silicon oxide film 38 present at the peripheral portion of the second main surface of the semiconductor substrate 10 exists in a region other than the peripheral portion of the second main surface of the semiconductor substrate 10. It is sufficiently thin with respect to the thickness of the laminated film (insulating film) 29. Therefore, even when the tungsten film (conductive film) 44 is formed by the plasma CVD method, electric charges are supplied into the semiconductor substrate 10 through the silicon oxide film 38 present at the peripheral edge of the second main surface of the semiconductor substrate 10. Is done. Therefore, when the tungsten film (conductive film) 44 is formed by the plasma CVD method, even if a large amount of charge is accumulated in the gate electrode 24, the potential of the gate electrode 24 with respect to the potential of the semiconductor substrate 10. Can be prevented from rising extremely, and the dielectric breakdown of the gate insulating film 22 can be prevented.

  Next, the tungsten film 44 is polished by CMP, for example, until the surface of the interlayer insulating film 38 is exposed. As a result, the conductor plug 44 made of tungsten is embedded in the contact hole 40 (see FIG. 8A).

  Next, as shown in FIG. 8B, an interlayer insulating film 46 is formed on the interlayer insulating film 38 in which the conductor plugs 44 are embedded. As the interlayer insulating film 46, for example, a silicon oxide film is formed.

  Next, as shown in FIG. 9A, a trench 48 for embedding the wiring 56 is formed in the interlayer insulating film 46.

  Next, as shown in FIG. 9B, a barrier metal film 50 made of Ta, for example, is formed on the entire surface by, eg, sputtering.

  Next, as shown in FIG. 10A, a seed film 52 made of Cu or a Cu alloy is formed on the entire surface by, eg, sputtering.

  Next, as shown in FIG. 10B, a conductive film 54 made of Cu or a Cu alloy is formed by, for example, electroplating. Since the 1st main surface of the semiconductor substrate 10, the 2nd main surface of the semiconductor substrate 10, and the outer periphery of the semiconductor substrate 10 are covered with the laminated film (insulating film) 29 or the insulating film 38, Cu is electroplated. Alternatively, when the conductive film 54 made of a Cu alloy is formed, Cu atoms do not diffuse into the semiconductor substrate 10 and the electrical characteristics of the characteristics of the transistor 33 and the like do not deteriorate.

  Next, as shown in FIG. 11, the conductive film 54 is polished by, for example, a CMP method until the surface of the interlayer insulating film 46 is exposed. Thereby, the wiring 56 made of Cu or Cu alloy is embedded in the groove 48.

  Thereafter, multilayer wiring, electrode pads, etc. (not shown) are further formed.

  Thus, the semiconductor device according to the present embodiment is manufactured.

(Evaluation results)
Next, the evaluation results of the semiconductor device manufacturing method according to the present embodiment will be explained with reference to FIG.

  FIG. 13 is a graph showing the measurement result of the gate leakage current density. The horizontal axis in FIG. 13 indicates the gate leakage current density. The vertical axis in FIG. 13 indicates the cumulative probability. In FIG. 13, the plots indicated by marks ● indicate the case of the comparative example, that is, the case where the laminated film 29 at the peripheral edge of the second main surface of the semiconductor substrate 10 is not etched. In FIG. 13, plots indicated by ▲ indicate the case of this embodiment, that is, the case where the laminated film 29 at the peripheral edge of the second main surface of the semiconductor substrate 10 is etched. When measuring the gate leakage current density, the gate potential of the transistor was 1.8 V, the source potential was 0 V, the drain potential was 0 V, and the substrate potential was 0 V.

As can be seen from FIG. 13, in the comparative example, only 50% of the transistors had a gate leakage current density of 2 × 10 ⁻⁷ A / cm ² or less.

On the other hand, in the case of this embodiment, the gate leakage current density is 2 × 10 ⁻⁷ A / cm ² or less in almost 100% of the transistors.

  From these facts, it can be seen that according to the present embodiment, the reliability and manufacturing yield of the transistor can be remarkably improved.

  Moreover, when the test regarding the lifetime of a transistor was done, the following results were obtained. Note that, here, the time required for 0.1% of the transistors formed to be defective is determined.

In the case of the comparative example, the time until the entire 0.1% of the transistors became defective was 5.8 × 10 ³ hours.

On the other hand, in the case of the present embodiment, the time until the entire 0.1% of the transistors are defective is 1.4 × 10 ⁴ hours.

  From these, it can be seen that according to the present embodiment, it is possible to sufficiently extend the lifetime of the transistor.

  Thus, according to the present embodiment, the laminated film (insulating film) 29 at the peripheral edge of the second main surface of the semiconductor substrate 10 is removed by etching. For this reason, when the conductive film (barrier metal film) 42 and the like are formed by a plasma CVD method in a later process, charges are supplied into the semiconductor substrate 10 via the peripheral edge portion of the second main surface of the semiconductor substrate 10. The For this reason, according to the present embodiment, even when a large amount of charge is accumulated in the gate electrode 24 when the conductive film 42 and the like are formed by the plasma CVD method, the potential of the gate electrode 24 is maintained at the level of the semiconductor substrate 10. It becomes possible to prevent the potential from becoming extremely high with respect to the potential. For this reason, according to the present embodiment, it is possible to prevent the dielectric breakdown of the gate insulating film 22 and to improve the manufacturing yield.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the above embodiment, the case where the laminated film 29 including the silicon oxide film 12, the silicon nitride film 14, and the silicon oxide film 28 is formed on the second main surface of the semiconductor substrate 10 has been described as an example. The insulating film formed on the second main surface is not limited to the laminated film 29 having such a structure. The principle of the present invention can be widely applied when an insulating film is formed on the second main surface of the semiconductor substrate 10.

  As detailed above, the features of the present invention are summarized as follows.

(Appendix 1)
Forming a transistor having a gate electrode and source / drain diffusion layers on a first main surface of a semiconductor substrate;
Forming a first insulating film on the first main surface of the semiconductor substrate and on the transistor;
Forming a contact hole reaching the gate electrode in the first insulating film;
Forming a conductive film by plasma CVD in the contact hole and on the first insulating film;
Polishing the conductive film until the surface of the first insulating film is exposed, and embedding a conductor plug containing the conductive film in the contact hole,
Before the step of forming the conductive film, of the second insulating film existing on the second main surface, which is the surface opposite to the first main surface, on the peripheral portion of the second main surface A method of manufacturing a semiconductor device, further comprising the step of etching away the second insulating film that exists.

(Appendix 2)
In the method for manufacturing a semiconductor device according to attachment 1,
After the step of forming the transistor and before the step of forming the first insulating film, the second insulating film existing at the peripheral portion of the second main surface is removed by etching. A method for manufacturing a semiconductor device.

(Appendix 3)
In the method for manufacturing a semiconductor device according to attachment 2,
In the step of forming the first insulating film, the first insulating film is formed so as to cover the peripheral portion of the second main surface, and is formed on the peripheral portion of the second main surface. The film thickness of the first insulating film is smaller than the film thickness of the first insulating film formed on the first main surface and smaller than the film thickness of the second insulating film. A method for manufacturing a semiconductor device.

(Appendix 4)
In the method for manufacturing a semiconductor device according to attachment 3,
After the step of embedding the conductor plug, a third insulating film in which a groove exposing the upper portion of the conductor plug is formed on the first insulating film on the first main surface side of the semiconductor substrate. And a step of embedding a wiring containing Cu in the groove by electroplating in a state where the second main surface of the semiconductor substrate is covered with the first insulating film and the second insulating film. A method for manufacturing a semiconductor device, further comprising: a step.

(Appendix 5)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 4,
In the step of etching and removing the second insulating film present on the peripheral edge of the second main surface, the plasma existing in a ring shape is used for the peripheral edge of the second main surface. A method for manufacturing a semiconductor device, comprising: removing the second insulating film by etching.

(Appendix 6)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 5,
The second insulating film includes a first silicon oxide film formed on the semiconductor substrate and a silicon nitride film formed on the first silicon oxide film. Production method.

(Appendix 7)
In the method for manufacturing a semiconductor device according to attachment 6,
The method for manufacturing a semiconductor device, wherein the second insulating film further includes a second silicon oxide film formed on the silicon nitride film.

(Appendix 8)
In the method for manufacturing a semiconductor device according to any one of appendices 1 to 7,
The width of the peripheral portion of the second main surface of the semiconductor substrate is 1 to 3 mm.

It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 4) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 5) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 6) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 7) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 8) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 9) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 10) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is process sectional drawing (the 11) which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is the schematic which shows a bevel etching apparatus. It is a graph which shows the measurement result of gate leak current density.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, semiconductor wafer 12 ... Silicon oxide film 14 ... Silicon nitride film 16 ... Silicon oxide film 17 ... Groove 18 ... Element isolation region 20 ... Element region 22 ... Gate insulating film 24 ... Gate electrode 26 ... Impurity diffusion region 28 ... Silicon oxide film 29 ... laminated film, insulating film 30 ... impurity diffusion region 32 ... source / drain diffusion layer 33 ... transistor 34a ... silicide film, source / drain electrode 34b ... silicide film 36 ... silicon nitride film, etching stopper film 38 ... silicon Oxide film, interlayer insulating film 40 ... contact hole 42 ... barrier metal film 44 ... tungsten film, conductor plug 46 ... interlayer insulating film 48 ... groove 50 ... barrier metal film 52 ... seed film 54 ... conductive film 56 ... wiring 100 ... bevel etching Apparatus 101 ... Chamber 102 ... Mounting table 104 ... Insulating member 106 ... First Ground electrode 108 ... top plate 110: second ground electrode 112 ... third ground electrodes 114 ... gas inlets 116 ... plasma

Claims (5)

Forming a transistor having a gate electrode and source / drain diffusion layers on a first main surface of a semiconductor substrate;
Forming a first insulating film on the first main surface of the semiconductor substrate and on the transistor;
Forming a contact hole reaching the gate electrode in the first insulating film;
Forming a conductive film by plasma CVD in the contact hole and on the first insulating film;
Polishing the conductive film until the surface of the first insulating film is exposed, and embedding a conductor plug containing the conductive film in the contact hole,
Before the step of forming the conductive film, of the second insulating film existing on the second main surface, which is the surface opposite to the first main surface, on the peripheral portion of the second main surface A method of manufacturing a semiconductor device, further comprising the step of etching away the second insulating film that exists. In the manufacturing method of the semiconductor device according to claim 1,
After the step of forming the transistor and before the step of forming the first insulating film, the second insulating film existing at the peripheral portion of the second main surface is removed by etching. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 2.
In the step of forming the first insulating film, the first insulating film is formed so as to cover the peripheral portion of the second main surface, and is formed on the peripheral portion of the second main surface. The film thickness of the first insulating film is smaller than the film thickness of the first insulating film formed on the first main surface and smaller than the film thickness of the second insulating film. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 3,
After the step of embedding the conductor plug, a third insulating film in which a groove exposing the upper portion of the conductor plug is formed on the first insulating film on the first main surface side of the semiconductor substrate. And a step of embedding a wiring containing Cu in the groove by electroplating in a state where the second main surface of the semiconductor substrate is covered with the first insulating film and the second insulating film. A method for manufacturing a semiconductor device, further comprising: a step. In the manufacturing method of the semiconductor device of any one of Claims 1 thru / or 4,
In the step of etching and removing the second insulating film present on the peripheral edge of the second main surface, the plasma existing in a ring shape is used for the peripheral edge of the second main surface. A method for manufacturing a semiconductor device, comprising: removing the second insulating film by etching.

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