JP2006351732A - Process for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor device having a stable structure in which parasitic capacitance is low between interconnect lines. <P>SOLUTION: The process for fabricating a semiconductor device comprises a step for forming a wiring structure of a conductive material being buried in a first insulator, a step for exposing the wiring structure by removing the first insulator, a step for forming a second insulator to bury the wiring structure, a step for forming a cap film on the second insulator, and a step for removing the second insulator. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure.

  In recent VLSI development, high integration is performed by miniaturizing semiconductor elements, and the operation speed is increased in accordance with the scaling law. When the semiconductor element is miniaturized in this way, the wiring pattern of the semiconductor device is miniaturized, so that it is possible to prevent wiring delay due to the miniaturization of the wiring pattern and to reduce the power consumption of the high-speed semiconductor device. Planning is an issue.

  For example, in order to solve the above-described problem, there is a method of lowering the resistance value of the wiring material. In recent years, wiring using Cu instead of Al has been increasingly used. Furthermore, in order to solve the above problem, there is a method of reducing the parasitic capacitance between the wiring patterns, and various studies have been made to reduce the parasitic capacitance by using an interlayer insulating film having a low dielectric constant. Yes.

The dielectric constant of a CVD-SiO ₂ film conventionally used as an interlayer insulating film is about 4. In order to lower the dielectric constant, even when a SiOF film in which fluorine is added to the CVD-SiO ₂ film is used, the dielectric constant is limited to about 3.3 to 3.5. In recent high-density semiconductor integrated circuits, In some cases, the effect of reducing the parasitic capacitance is not sufficient, and the required operation speed may not be obtained.

  Therefore, attention is focused on the use of a porous insulating film (bolus insulating film) as a so-called low dielectric constant interlayer insulating film having a lower dielectric constant. The porous insulating film is formed by adding a material that evaporates or decomposes by heating to the coating material, for example, by applying the spin coating method and then evaporating or decomposing the added material by heating the coating material. Is made porous. The porous insulating film can also be formed by a CVD method or the like.

  Thus, by making the insulating film porous, for example, the dielectric constant of the insulating film can be lowered to 2.5 or less, and this can be used as an interlayer insulating film of a semiconductor device as a low dielectric constant interlayer insulating film. It has been studied for use.

  1A to 1D show an example of a method for forming a wiring structure of a semiconductor device in the case where a porous insulating film is used as an interlayer insulating film. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  For example, FIG. 1A shows a state in which a wiring structure is formed on a semiconductor element formed on a semiconductor substrate such as a MOS transistor (not shown).

  Referring to FIG. 1A, an insulating layer 1 made of a porous insulating film is formed, and a trench wiring 2 made of Cu is formed in the insulating layer 1. A cap film 3 for preventing diffusion of Cu is formed on the trench wiring 2 and the insulating layer 1. In the following FIG. 1B and thereafter, a method of forming a wiring structure on the trench wiring 2 will be shown.

  In the step shown in FIG. 1B, an insulating layer 4 made of a porous insulating film is formed on the cap film 3, and an etch stopper film 5 is formed on the insulating layer 4 as necessary. Next, an insulating layer 6 made of a porous insulating film is formed on the etch stopper film 5. Further, a hard mask 7 and a resist 8 are stacked on the insulating layer 6. The hard mask 7 may be provided for the purpose of protecting the insulating layer 6 made of a porous insulating film, and the etching selectivity between the resist 8 and the insulating layer 6 is small (for example, the insulating layer 6 In some cases, a hard mask having a high etching selection ratio is used in the case where the etching mask is made of an organic material, but may be omitted.

  Next, in the step shown in FIG. 1C, the resist 8 is exposed by photolithography and then developed and patterned. Next, the hard mask 7 is etched and patterned using the patterned resist 8 as a mask.

  Next, using the patterned resist or hard mask as a mask, the trench 10 that penetrates the insulating layer 10 is formed by plasma etching, for example, and the trench 10 is formed from the insulating layer 4 to the cap film 3. Then, a via hole 9 reaching the trench wiring 2 is formed. In this case, the via hole may be formed first and then the trench may be formed, or the via hole may be formed after the trench is formed. If the etch stopper layer 5 is formed between the insulating layer 4 and the insulating layer 6, the trench 10 can be easily formed.

  Next, in the step shown in FIG. 1D, a conductive material, for example, Cu is embedded in the via hole 9 and the trench 10 by a plating method, the via plug 11 is placed in the via hole 9, and the trench wiring 12 is placed in the trench 10. Form. Furthermore, by forming the cap film 13 so as to cover the trench wiring 10, it is possible to form a further upper wiring structure.

Although not shown in FIG. 1D, a diffusion prevention film (barrier film) of a conductive material (Cu) is formed between the insulating layer 4, the insulating layer 6, and the conductive material. For example, refractory metals such as Ta, TaN, TiN, W, and WN, nitrides of refractory metals, and the like are used as the diffusion preventing film.
Japanese Patent No. 3063836

  However, the above-described method for manufacturing a semiconductor device has a problem that damage is caused particularly in an interlayer insulating film having a low dielectric constant (the insulating layer 4 and the insulating layer 6). Such damage to the interlayer insulating film has been a serious problem particularly when an insulating film made of a porous material is used. In the manufacturing process of the semiconductor device described above, the following damages may occur in the interlayer insulating films such as the insulating layer 4 and the insulating layer 6.

  For example, when the etch stopper layer 5 is formed on the insulating layer 4, or when the hard mask 7 is formed on the insulating layer 6, when the plasma CVD method or the sputtering method is used, the insulating layer In some cases, plasma damage may occur. Further, when these films are formed by a coating method (spin-on), there is a possibility that some chemical solution used for coating may penetrate into the insulating layer and cause damage.

Further, when the resist 8 is peeled off, the insulating layer 4 and the insulating layer 6 need to be subjected to chemical treatment for resist development, resist peeling, and residue treatment. The insulating layer may be damaged. Further, when the resist 8 is removed by ashing, the insulating layer 4 and the insulating layer 6 may be damaged by the plasma used in the ashing process, such as O ₂ plasma. It was.

  In addition, after embedding a conductive material such as Cu in a via hole or a trench, a process of polishing the conductive material by CMP (chemical mechanical polishing) is generally provided. In such a CMP process, there is a concern that a great stress is applied to the insulating layer 4 and the insulating layer 6 and mechanical damage is caused to the interlayer insulating film.

  When a diffusion prevention film is formed between the insulating layer 4 and the insulating layer 6 and a conductive material such as Cu, the inner wall surface of the via hole 9 or the inner wall surface of the trench 10 is formed by, for example, sputtering. Alternatively, it has been common to form a refractory metal such as Ta, TaN, TiN, W, WN or a refractory metal nitride by CVD or the like.

  In this case, when the diffusion prevention film is formed, the insulating layer may be damaged by the plasma. In addition, since the insulating layer is a porous material, the above-mentioned diffusion preventing film material may enter the inside of the porous film, or a pinhole may be formed in the diffusion preventing film, and the reliability of the diffusion preventing film may be increased. Deterioration may occur. As described above, there has been a problem that it is difficult to form a diffusion prevention film, particularly for an insulating film made of a porous material.

  When the interlayer insulating film is damaged in this way, for example, the interlayer insulating film and the wiring structure may be peeled off, and the manufacturing yield may be reduced. In addition, the characteristics of the manufactured semiconductor device may vary, and in particular, the electrical characteristics may vary.

  In view of the above, the present invention has a general object to provide a novel and useful method for manufacturing a semiconductor device that solves the above-described problems.

  A specific problem of the present invention is to provide a semiconductor device manufacturing method for manufacturing a semiconductor device having a stable structure with a small parasitic capacitance between wirings.

  In the present invention, the above-described problems are solved by a wiring structure forming step of forming a wiring structure made of a conductive material embedded in the first insulating layer, and a first step of removing the first insulating layer and exposing the wiring structure. A first insulating layer removing step, an insulating layer embedding step for forming a second insulating layer so as to fill the wiring structure, a cap film forming step for forming a cap film on the second insulating layer, And a second insulating layer removing step for removing the second insulating layer.

  According to this manufacturing method, it is possible to manufacture a semiconductor device having a stable structure with a small parasitic capacitance between wirings.

  In the first insulating layer removing step, the first insulating layer can be easily removed by removing the first insulating layer by wet etching using a chemical solution.

  In the second insulating layer removing step, the second insulating layer can be easily removed by removing the second insulating layer by wet etching using an etching medium made of a chemical solution.

  The second insulating layer removing step includes: a supply port forming step for forming a supply port for supplying the chemical solution to the second insulating layer in the cap film; and the chemical solution from the supply port. And an etching medium supply step for supplying the second insulating layer to the second insulating layer, the second insulating layer can be removed while the wiring structure is covered with the cap film.

  Also, a support structure that forms a support structure that supports the cap film and a lower insulating layer formed in a lower layer of the wiring structure at a position corresponding to the supply port after the second insulating layer removing step. If the body forming step is further included, the rigidity of the semiconductor device can be improved, which is preferable.

  Further, when the support structure is formed by a CVD method, the support structure can be easily formed at a position corresponding to the opening, which is preferable.

  In addition, it is preferable that a plurality of the support structures are formed on the lower insulating layer because the rigidity of the semiconductor device can be improved.

  Further, when the support structure is formed so as to surround the wiring structure, it is preferable that the wiring structure can be separated from the outside air by the support structure.

  Further, in the wiring structure forming step, a trench wiring and a via pug constituting the wiring structure are formed, and a region where the first insulating layer is formed is formed in the supporting structure forming step. When a separation structure that separates into a region where a body is formed and a region where the support structure is not formed is formed, it is preferable because the support structure can be easily formed.

  Further, when the separation structure has a plurality of pattern structures made of the conductive material formed on the lower insulating layer, the etching medium can pass between the plurality of pattern structures, Is preferred.

  In the etching medium supply step, when the etching medium is supplied to the second insulating layer from among the plurality of pattern structures, a region in which the support structure is formed by the pattern structure is configured. In addition, the etching medium can be supplied to the second insulating layer from the supply port, which is preferable.

  Also, in the wiring structure forming step, it is preferable that a reinforcing structure made of the conductive material that reinforces the wiring structure can be prevented from damage to the wiring structure.

  In addition, it is preferable that the conductive material is made of Cu because the resistance value of the wiring structure can be reduced.

  In addition, after the first insulating layer removing step, the conductive material has the diffusion insulating film forming step of forming a diffusion preventing film of the conductive material on the exposed surface of the wiring structure, and the conductive material becomes the second insulating layer. It is preferable that it diffuses into the surface.

  In the diffusion preventing film forming step, it is preferable that a nitriding process for nitriding the surface of the wiring structure is performed because the conductive material is suppressed from diffusing into the second insulating layer.

  In addition, if a reduction process is performed to remove the exposed oxide film on the surface of the wiring structure before the diffusion prevention film forming process, the adhesion between the diffusion prevention film and the wiring structure is improved, which is preferable. is there.

  Further, when the first insulating layer is made of a porous material, it is easy to remove the first insulating layer.

  Moreover, when the second insulating layer is made of a porous material, it is easy to remove the second insulating layer.

  Further, a porous silica material may be used as the porous material.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the manufacturing method of the semiconductor device which manufactures the semiconductor device which has the parasitic capacitance between wiring small and has a stable structure.

  First, the outline of the present invention will be described below.

  In the method for manufacturing a semiconductor device according to the present invention, a wiring structure forming step for forming a wiring structure made of a conductive material embedded in a first insulating layer, and the wiring structure is exposed by removing the first insulating layer. A first insulating layer removing step, an insulating layer embedding step of forming a second insulating layer so as to fill the wiring structure, and a cap film forming step of forming a cap film on the second insulating layer; And a second insulating layer removing step for removing the second insulating layer.

  In the case of the above manufacturing method, in the process of forming the wiring structure, the first insulating layer that is highly likely to be damaged is removed by, for example, plasma treatment or wet treatment.

  Further, the second insulating layer is separately formed so as to fill the wiring structure around the wiring structure, so that a cap film can be formed on the second insulating layer. By forming the cap film, the wiring structure is isolated from the outside air, and another wiring structure can be formed on the cap film. After the cap film is formed, the second insulating film is removed to reduce the parasitic capacitance of the wiring structure.

  In addition, by forming an insulating layer again on the cap film and repeating the above steps, it is possible to form a multilayer wiring structure in which a plurality of wiring structures separated by the cap film are stacked. . In this case, the cap film isolates the wiring structure from the outside air and becomes a part of the structure that becomes the outer wall of the wiring structure and supports the multilayer wiring structure.

  In the above structure, there is substantially a gas such as air or inert gas around the wiring structure, and the parasitic capacitance of the wiring structure is greatly reduced compared to the conventional structure using an interlayer insulating film. It becomes possible to do.

  Further, since the interlayer insulating film damaged in the manufacturing process does not remain between the wiring structures as in the prior art, for example, problems such as film peeling between the interlayer insulating film and the wiring structure do not occur. . In addition, variations in characteristics of the semiconductor device to be manufactured, for example, electrical characteristics, caused by damage to the interlayer insulating film are suppressed, and the manufacturing yield of the semiconductor device is improved.

  In this case, the first insulating layer and the second insulating layer can be easily removed by, for example, dissolving (wet etching) in a chemical solution. In particular, it is preferable to use a porous material (for example, porous silica) having a high wet etching rate with a solution for the first insulating layer or the second insulating layer.

For example, FIG. 2 is a diagram comparing the etching rates of various types of insulating films in an acid solution and an alkaline solution. In FIG. 2, an oxide film formed by a CVD method in ○ (hereinafter referred to as a CVD oxide film in the text), a porous insulating film made of a porous material in ◆, and a plasma dry etching of the porous insulating film in ● 3 shows the measurement results of the wet etching rate in the solution after being exposed to plasma. Further, the horizontal axis of the graph indicates the pH in the solution. In this experiment, an HCl solution is used as the acid solution, and an NH ₄ OH solution is used as the alkaline solution.

  Referring to FIG. 2, it can be seen that the etching rate of each insulating film increases particularly in a region where PH is high, that is, in an alkaline solution. In particular, the etching rate of the porous insulating film is higher than that of the CVD oxide film. This is presumably because the surface area of the porous insulating film is larger than that of the CVD oxide film and the area in contact with the solution is large.

  Furthermore, it can be seen that the wet etching rate of the porous insulating film exposed to plasma (after dry etching by plasma) is higher than that of the porous insulating film before being exposed to plasma. This suggests that the porous insulating film is damaged by exposure to plasma, and that the porous insulating film exposed to plasma can be easily removed by wet etching with an alkaline solution. ing.

  FIG. 3 is a diagram comparing the etching rates of various types of insulating films in a hydrofluoric acid (HF) solution. In FIG. 3, ○ indicates a CVD oxide film, ◇ indicates a thermal oxide film, ♦ indicates a porous insulating film made of a porous material, and ● indicates that the porous insulating film is subjected to plasma dry etching. 3 shows the measurement results of the wet etching rate in the hydrofluoric acid solution when exposed to water. Further, the horizontal axis of the graph indicates the pH in the solution.

  Referring to FIG. 3, when the etching rates of the respective insulating films are compared, the wet etching rate of the porous insulating film is particularly higher than that of the CVD oxide film and the thermal oxide film, and the plasma is exposed to the plasma (the dry etching by the plasma). In the porous insulating film (after etching), the wet etching rate is further increased.

  Thus, even when hydrofluoric acid is used as the wet etching solution, the wet etching rate of the porous insulating film is large, and the wet etching rate of the porous insulating film exposed to plasma is further increased. Recognize.

  In the present invention, it is preferable to use the above properties. For example, when a porous insulating film is used as the first insulating film or the second insulating film, the wet etching rate is high, and the first insulating layer or the second insulating film is used. It is easy to remove the second insulating film, which is preferable.

  In order to prevent diffusion of a conductive material constituting the wiring structure, for example, Cu into the interlayer insulating film, conventionally, a diffusion preventing film has been formed on the interlayer insulating film side. However, the following problems have arisen when a diffusion barrier film is formed in the interlayer insulating film. First, 1) When plasma is used during the formation of the diffusion barrier film (sputtering, CVD, etc.), there is a problem that the insulating layer is damaged by the plasma, and 2) a problem that the diffusion barrier film penetrates the insulating layer. ) There is a problem that pinholes are formed in the diffusion prevention film, and these problems are remarkable particularly when the insulating layer is made of a porous material. On the other hand, in the present invention, since the wiring structure is exposed, it is easy to form a diffusion prevention film (barrier film) of a conductive material (for example, Cu) constituting the wiring structure on the exposed wiring structure surface. It has become. Therefore, the above-described conventional problem in forming the diffusion prevention film can be suppressed.

  Further, when the wiring structure is formed in the above manufacturing method, various stresses are applied to the wiring structure and the cap film. In particular, in the case of the present invention, since it includes a step of removing the interlayer insulating film, it is preferable to have a structure that supports (or reinforces) the wiring structure and the cap film.

  For example, when these structures are formed, it is preferable that the structure is formed by connecting the opposing cap films with the wiring structure sandwiched by an insulator by a CVD method, because the rigidity of the entire semiconductor device is improved. It is also preferable to provide a structure that reinforces the wiring structure, for example, in the step of forming the wiring structure, for example, by a material similar to the conductive material constituting the wiring structure.

  Details of specific configuration examples of these structures will be described later in the following embodiments.

  Next, embodiments of the present invention will be specifically described with reference to the drawings.

  4A to 4L are diagrams showing an example of a method of manufacturing a semiconductor device according to the first embodiment of the present invention, following the procedure.

  First, in the semiconductor device in the process of forming a wiring structure shown in FIG. 4A, an insulating layer 201 is formed on a semiconductor element such as a MOS transistor (not shown) formed by a regular method. In the insulating layer 201, for example, a trench wiring 202 made of Cu, for example, partially connected to the MOS transistor is formed. The insulating layer 202 may have a removed structure in the same manner as shown in the following steps.

  In this step, a cap film 101 is formed on the insulating layer 201, and an insulating layer 102 made of a porous material is formed on the cap film 101. The cap film 101 is formed so as to cover the trench wiring 202. The insulating layer 102 is made of, for example, porous silica, and is formed by, for example, SOD (Spin on Dielectric) method. Moreover, such a porous material can also be formed by a CVD method.

  4B, after forming a resist on the insulating layer 102 and patterning the resist by a photolithography method, the insulating layer 102 is etched using the patterned resist as a mask. Then, a trench 104 communicating with the via hole 103 is formed on the via hole 103. In this case, the via hole 103 is formed so as to penetrate the cap layer 101 from the insulating layer 102 side, and is formed so that a part of the trench wiring 202 is exposed at the bottom of the via hole 103.

  In this case, a hard mask may be formed between the resist and the insulating layer 102. The hard mask has an effect of protecting the insulating layer 102 made of a porous material. When the etching selectivity between the resist and the insulating layer 102 is small (for example, when the insulating layer 102 is formed of an organic material), the hard mask is patterned once using the resist as a mask, The insulating layer 102 may be etched using the patterned hard mask as a substantial mask.

  An etch stopper layer may be provided in the insulating layer 102 at a height near the boundary between the via hole 103 and the trench 104. Providing an etch stopper layer provides an effect that the depth of the trench 104 can be easily controlled.

  The hard mask and the etch stopper layer are preferably materials that can be removed by wet etching in the same manner when the insulating layer 102 is removed by wet etching in a later step. A material having a small difference in speed is more preferable.

  Furthermore, in the case of the present embodiment, it is preferable to form a bridge groove 105 connecting the plurality of trenches 104 to each other in the insulating layer 102. In the bridge groove 105, a bridge structure that supports a plurality of trench wirings by connecting a plurality of trench wirings formed in the trenches 104 to each other is formed in a later step. A plurality of the bridge grooves 105 are formed so as to connect two adjacent trenches in a direction orthogonal to the trench 104, for example.

  In addition, the bridge groove 105 is preferably formed to be shallower than the trench 104. This is to make it possible to remove the bridge structure formed in the bridge groove by CMP in a later process.

  In this step, it is preferable to form a via hole 106 in addition to the via hole 103. In a later step, the via hole 103 is formed with a trench wiring formed in the trench 104 and a via plug that electrically connects the trench wiring 202. On the other hand, the via hole 106 is formed with a via plug which is a reinforcing structure for supporting the trench wiring formed in the trench 104.

  Next, in the step shown in FIG. 4C, a conductive material that forms a wiring structure, for example, Cu, is embedded in the via hole 103, the via hole 106, the trench 104, and the bridge groove 105. As a result, via plugs 103A and 106A are formed in the via holes 103 and 106, a trench wiring 104A is formed in the trench 104, and a bridge structure 105A is formed in the bridge groove 105, respectively. In this case, the via plug 103A is electrically connected to the trench wiring 202, and the trench wiring 202 and the trench wiring 104A are electrically connected.

  Further, since the via plug 106A is a reinforcing structure for supporting the trench wiring 104A, it is not connected to wiring other than the trench wiring 104A. Details of such a reinforcing structure will be described later.

  When Cu is embedded in the via hole 103, the via hole 106, the trench 104, and the bridge groove 105, for example, a plating method can be used. However, prior to plating, plating is performed by a sputtering method or a CVD method. It is preferable to form a seed layer. Further, Cu embedding is not limited to a plating method, and can be performed by a sputtering method or a CVD method.

  Conventionally, a Cu diffusion prevention film is generally formed on the insulating layer 102 prior to Cu embedding, but in this embodiment, the wiring structure side (Cu In this step, it is not necessary to form a diffusion prevention film.

  Further, Cu is formed on the trench 104 and the bridge groove 105 and so as to cover the entire insulating layer 102.

  Next, in the step shown in FIG. 4D, the conductive material formed on the trench 104 and the bridge groove 105 and so as to cover the entire insulating layer 102 is polished by CMP. In this step, the conductive material (Cu) is removed by CMP to such an extent that the insulating layer 102, the trench wiring 104A, and the bridge structure 105A are exposed.

  Thus, a wiring structure including the trench wiring 104A, the via plugs 103A and 106A, and the bridge structure 105A is formed. The wiring structure includes the trench wiring 104A and the via plug 103A used for electrical wiring of a semiconductor device, and includes the bridge structure 105A and the via plug 106A for reinforcing the mechanical strength of the wiring structure. Have.

  For example, the bridge structure 105A and the via plug 106A are structures that support (reinforce) the trench wiring 104A, and the wiring structure is damaged by the stress applied to the wiring structure in the manufacturing process of the semiconductor device. That is restrained. For example, the wiring structure is prevented from being broken or deformed by a stress caused by CMP, a stress change caused by heat treatment or plasma, or a stress applied when wet treatment is performed.

  Next, in the step shown in FIG. 4E, the insulating layer 102 is dissolved and removed by wet etching using a solution. As the solution for dissolving the insulating layer 102, for example, as shown in FIG. 2 or FIG. 3, an alkaline solution such as an ammonia solution or a hydrofluoric acid solution can be used. It is also possible to use an ammonium fluoride solution or the like. Moreover, it is also possible to mix and use these solutions. In this case, since the cap film 101 preferably remains without being dissolved in the solution, the cap film 101 preferably has resistance to the solution.

  Moreover, you may add the corrosion inhibitor which prevents the corrosion by the chemical | medical solution of conductive materials (wiring structure), such as Cu, for example, and the antioxidant which prevents the oxidation of the said conductive material to the said solution. For example, BTA (benzotriazole) can be used as the corrosion inhibitor, and ascorbic acid or aspartic acid can be used as the antioxidant.

  Further, deposits such as etching residues may remain on the surface of the wiring structure. In order to remove these deposits, the wiring structure is preferably cleaned.

  Next, a diffusion prevention film is formed on the wiring structure surface to prevent the conductive material constituting the wiring structure, for example, Cu, from diffusing into an interlayer insulating film formed in a later step. Conventionally, a diffusion preventing film having a wiring structure is formed on the interlayer insulating film side, but in this case, various problems such as damage to the interlayer insulating film have occurred. In the case of the present embodiment, by forming the diffusion prevention film on the wiring structure side, problems in forming the diffusion prevention film on the interlayer insulating film side can be avoided.

For example, the diffusion preventing film is supplied to the wiring structure by passing a gas containing a nitrogen element such as NH ₃ gas through a heating catalyst body such as W (tungsten), and thereby supplying the wiring structure surface (Cu surface). Can be formed by nitriding and passivating.

Further, before forming the diffusion preventing film, it is preferable to reduce the oxide film in order to remove the oxide film formed on the surface of the wiring structure. In this case, the reduction of the oxide film can be performed, for example, by supplying heated H ₂ gas to the wiring structure.

  The method for forming the diffusion barrier film is not limited to the above method. For example, an insulating film can be formed on the surface of the wiring structure by a CVD method or an ALD method (Atomic Layer Deposition method). There is also a method of forming a self-assembled film (SAM film) on the surface of the wiring structure. In this case, the wiring structure is immersed in a solution containing a component that forms a predetermined self-assembled film. That's fine.

  In the drawing, the diffusion preventing film is not shown.

  Next, in a step shown in FIG. 4F, an insulating layer 107 made of a porous material such as porous silica is formed on the cap film 101 so as to fill the wiring structure. In this case, the insulating layer 107 is formed by, for example, the SOD method. Moreover, such a porous material can also be formed by a CVD method.

  Next, in the step shown in FIG. 4G, the excess insulating layer 107 is removed by CMP. Further, the bridge structure 105A is polished together with the trench wiring 104A by CMP, and the bridge structure 105A is removed. Therefore, the trench wiring 104A is preferably formed thicker than the bridge structure 105A, and the thickness is suitable for use as a pattern wiring in a state where the bridge structure 105A is removed by polishing. The trench wiring 104A is preferably formed.

  Next, in the step shown in FIG. 4H, a cap film 601 is formed on the insulating layer 107 and the trench wiring 104 </ b> A exposed from the insulating layer 107. Note that in this figure (FIG. 4H) to FIG. 4L, a region wider than the region shown in FIG. 4A to FIG. 4I in the semiconductor device is shown. For example, the wiring structure such as the trench wiring 104A and the via plugs 103A and 106A shown in FIG. 4G is formed in the region A of FIG. 4H. That is, the scale of drawing differs in FIG. 4H and FIG. 4G. Further, in the drawings and subsequent figures, the lower layer structures such as the trench wiring 202 and the insulating layer 201 are not shown.

  In addition, as shown in the drawing, a plurality of via plugs 108 penetrating the insulating layer 107 are formed between the regions A on the cap film 101. For example, the via plug 108 is formed so as to penetrate the insulating layer 107 and to be in contact with the cap film 101 and the cap film 601. When the via plug 108 is formed, a via hole penetrating the insulating layer 102 is formed in the insulating layer 102 in the step shown in FIG. 4B, and in the step shown in FIG. The via plug may be formed by burying the conductive material. The via plug 108 contributes to improving the strength of the entire semiconductor device.

  Next, in a step shown in FIG. 4I, a supply port 602 for supplying a chemical for removing the insulating layer 107 is formed at a predetermined position of the cap film 601. In this case, the supply port 602 is formed by, for example, a dry etching method using a resist pattern patterned by a photolithography method as a mask. The supply port 602 is formed so as to penetrate the cap film 601 (so as to reach the insulating layer 107).

  Further, for example, at a position corresponding to the supply port 602 (illustrated by a region B in the drawing), after the insulating layer 107 is removed, the cap film 101 and the cap film 601 are supported. Preferably a support structure is formed. For this purpose, the region B is preferably provided with a predetermined structure for forming a support structure, which will be described later.

  Next, in the step shown in FIG. 4J, a chemical solution is supplied from the supply port 602 to dissolve and remove the insulating layer 107, and the insulating layer 107 is removed by wet etching. For example, as the chemical solution, a chemical solution similar to the chemical solution used in the process illustrated in FIG. 4E (an alkali solution, a hydrofluoric acid solution, an ammonium fluoride solution, or the like) can be used.

  For example, in the region A, the wiring structure such as the trench wiring 104A and the via plugs 103A and 106A is substantially exposed. However, in this case, the diffusion prevention film is formed on the wiring structure.

Next, in the step shown in FIG. 4K, for example, a columnar support structure 603 made of, for example, SiO ₂ is formed at a position corresponding to the supply port 602 by using, for example, a CVD method. In this case, a separation structure for separating a region where the support structure 603 is formed and a region where the support structure 603 is not formed is formed at a position corresponding to the supply port 602 on the cap film 101. It is preferable. The separation structure suppresses the intrusion of the film forming gas or the like so that the film forming gas for forming the support structure does not enter the space on the side where the wiring structure is formed. The structure of such a separation structure will be described with reference to FIG.

Further, for example, SiO ₂ formed by the CVD method is also formed on the cap film 601.

Therefore, in the step shown in FIG. 4L, the SiO ₂ film formed on the cap film 601 is removed by, for example, etch back or lift-off as necessary. The SiO ₂ film can also be removed by CMP. It is not always necessary to remove the SiO ₂ film.

  Thus, a semiconductor device having a wiring structure in which the upper layer and the lower layer are sandwiched between the cap films is formed. In the subsequent steps, it is obvious that a multilayer wiring structure having an arbitrary number of layers can be formed by repeating the same steps as in FIGS. 4A to 4L as necessary. For example, after the step of FIG. 4L, an insulating layer corresponding to the insulating layer 102 is formed on the cap film 601 in the same manner as the step of FIG. 4A, and the following steps corresponding to FIG. do it.

  A so-called interlayer insulating film is not formed around the wiring structure. Therefore, a gas such as air or an inert gas is substantially present around the wiring structure, and the parasitic capacitance of the wiring structure can be greatly reduced as compared with the conventional structure using an interlayer insulating film. It becomes possible.

  Further, since the interlayer insulating film damaged in the manufacturing process does not remain between the wiring structures as in the prior art, for example, problems such as film peeling between the interlayer insulating film and the wiring structure do not occur. . In addition, variations in characteristics of the semiconductor device to be manufactured, for example, electrical characteristics, caused by damage to the interlayer insulating film are suppressed, and the manufacturing yield of the semiconductor device is improved.

  Further, in the manufacturing method according to the present embodiment, the wiring structure embedded in the insulating layer is once exposed, and a diffusion preventing film of a conductive material constituting the wiring structure is formed on the wiring structure side. Thereafter, the wiring structure is buried again with an insulating layer to isolate the wiring structure and form a cap film that serves as a support structure for the semiconductor device.

  As described above, in the manufacturing method according to the present embodiment, for example, a diffusion prevention film is formed on the surface of the wiring structure by taking the step of exposing the wiring structure in a state where the wiring structure is not covered with the cap film. It is possible to perform the surface treatment of the wiring structure, for example, by performing a reduction treatment on the surface of the wiring structure and removing the oxide film.

  Further, since it is not necessary to form the diffusion preventing film on the interlayer insulating layer side, it is possible to avoid the problem that has been a problem when forming the diffusion preventing film on the interlayer insulating layer side.

  Further, in this embodiment, since the interlayer insulating film is removed and the wiring structure is substantially exposed, it is preferable to provide a structure for reinforcing the rigidity of the semiconductor device. For example, in the above example, the support structure 603 that supports the cap film 101 and the cap film 601 is provided. Such a support structure can be formed by, for example, a CVD method. Next, a preferable method and structure in the case of forming the support structure 603 will be described.

  In this case, as described above, for example, in the position corresponding to the supply port 602 of the insulating layer 107, the separation structure that suppresses the diffusion of the deposition gas is formed when the support structure 603 is formed. Preferably it is. The isolation structure substantially separates a region around the wiring structure where the insulating layer 107 is formed into a region where the support structure 603 is formed and a region where the support structure 603 is not formed. .

  FIG. 5 is a plan view of the separation structure 650, which is an example of the configuration of the separation structure. This figure is a view of the separation structure 650 formed in the insulating layer 107 in plan view from the supply port 602 side in the step shown in FIG. 4I.

  Referring to FIG. 5, the separation structure 650 is formed so that pattern structures 651, 652, 653 made of, for example, the same conductive material as the wiring structure surround a region 602 a of the insulating layer 107 corresponding to the supply port 602. Formed. In the step shown in FIG. 4J, a chemical solution for dissolving the insulating layer 107 is supplied to the insulating layer 107 side from the gap formed by these pattern structures.

In the step shown in FIG. 4K, the support structure 603 is formed in the inner region of the pattern structures 651, 652, and 653, that is, the region substantially corresponding to the region 602a by the CVD method. In this case, a film forming gas used for the CVD method, for example, a film forming gas such as TEOS or SiH ₄ hardly passes through the gaps between the pattern structures 651, 652, and 653, and the film formation mainly occurs in the region 602 a. become.

  That is, the gap between the pattern structures 651, 652, and 653 allows the solution for dissolving the insulating layer 107 to pass therethrough and substantially passes the film forming gas for forming the support structure 603. Preferably, it is formed to such an extent that it does not occur.

  For example, the pattern structure 651 has a substantially flat plate shape and is formed so as to stand on the cap film 101, and when viewed in plan, the longitudinal direction is substantially in a direction from the region 602a toward the outside of the region 602a. Formed to coincide with each other.

  The pattern structures 651 are arranged in, for example, a square so as to surround the region 602a, and the square pillar-shaped pattern structures 652 are arranged at corners of the square.

  In addition, the pattern structure 653 having a substantially flat plate shape is installed around the pattern structure 651 in a direction in which the longitudinal direction is orthogonal to the plurality of arranged pattern structures 651 so that the conductance of the gap is reduced. is set up.

  FIG. 6 is a cross-sectional view taken along the line X-X ′ of the separation structure 650 illustrated in FIG. 5. Referring to FIG. 5, the pattern structure 651 and the pattern structure 652 are formed to reach the cap film 601 from above the cap film 101 so as to penetrate the insulating layer 107, for example. . In this case, the gap d of the pattern structure is formed to such an extent that the chemical solution passes and the film forming gas does not substantially pass.

  These pattern structures 651, 652, and 653 can be formed at the same time, for example, in the step of forming the wiring structure (trench wiring 104A, via plug 103A, etc.). For example, in the step shown in FIG. 4B, when the trench 104 and the via plug 108 are formed in the insulating layer 102, a groove for forming the pattern structure is similarly formed in the insulating layer 102. In the step shown in FIG. 4C, the pattern structures 651, 652, and 653 may be formed by embedding a conductive material such as Cu in the groove.

FIG. 7 is a plan view of a state where the support structure 603 is formed inside the separation structure 650 (a state corresponding to FIG. 4L). Thus, the support structure made of, for example, SiO ₂ is formed substantially inside the pattern structures 651, 652, 653.

  Further, as described above, such a support structure is not limited to the case where the support structure is formed, for example, in a columnar shape so as to be interspersed between the trench wirings, and may be formed in various other shapes and structures. Is possible.

  FIG. 8 is a diagram showing an example of forming the support structure, and is a diagram in plan view of a wider range of the structure formed on the semiconductor substrate in the step corresponding to FIG. 4L than in FIG. 4L.

  Referring to FIG. 8, in a region C on the semiconductor substrate, a transistor, an upper layer wiring, and the like are formed and finally separated to form a semiconductor chip. That is, the via plug 108 shown in FIG. 4L, the region A including the wiring structure, and the support structure 603 are all included in the region C. In this case, illustration of these structures is omitted.

  A separation structure 700 having a structure similar to that of the separation structure 650 including the pattern structures 701 to 703 is formed so as to surround the region C, and a support D is provided in a region D outside the separation structure 700. A structure 603W is formed.

In this case, the support structure 603W is formed by the same method as the support structure 603 described above. That is, in the step shown in FIG. 4I, the portion corresponding to the region D of the cap film 601 is removed (opened) in the same manner as when the supply port 602 is formed in the cap film 601. Further, in the step shown in FIG. 4L, a support structure 603W made of, for example, SiO ₂ is formed in the region D by, eg, CVD.

  As described above, the support structure 603W is formed so as to surround the region C where the semiconductor chip is formed, whereby the wiring structure can be substantially isolated from the outside air. In this case, the upper layer and the lower layer of the wiring structure are covered with the cap film, and the side surfaces are covered with the support structure 603W.

  In addition, the support structure 603W has a substantial skeleton structure in the case where a semiconductor device is configured, and the rigidity of the semiconductor device can be improved. In addition, it is preferable to form the support structure 603W along the scrub line because dicing becomes easier when a semiconductor chip is cut out.

  Further, when such a support structure is formed, for example, if it is formed immediately below an electrode pad formed in a semiconductor device, it is possible to prevent the wiring structure from being damaged by an impact applied to the electrode pad.

  FIG. 9 is a diagram illustrating another configuration example of the support structure. Although illustration of a part of the semiconductor substrate, the semiconductor element, and the wiring structure is omitted in this drawing, the support structure shown in this drawing can be formed in the same manner as the above manufacturing method. Referring to FIG. 9, in the semiconductor device shown in this figure, cap films 401, 402, 403, 404 are laminated in order from the lower layer, and the interlayer insulating layer between the cap films is removed.

  Further, a support structure 413 that penetrates the cap films 402, 403, and 404 is formed on the cap film 401. An electrode pad 415 having a connection portion 416 is formed on the support structure 413 through a via plug 414. The electrode pad 415 is connected to a wiring structure such as a pattern wiring 411 and via plugs 410 and 412 as necessary.

  Conventionally, when wire wiring or the like is connected to the electrode pad 415, for example, by bonding, there has been a problem that the wiring structure on the semiconductor device side is disconnected due to the impact of bonding.

  Therefore, in the case of the structure shown in this figure, by providing the support structure 413 directly below the electrode pad 415, it is possible to prevent the wiring structure from being damaged by an impact during bonding.

  Further, in the method of manufacturing the semiconductor device according to the present embodiment, since there is no substantial interlayer insulating film around the wiring structure, in addition to the support structures 603 and 603W described above, the reinforcement for reinforcing the wiring structure is provided. It is preferable to provide a structure. In this embodiment, the bridge structure 105A and the via plugs 106A and 108 are provided as an example of the reinforcing structure.

  For example, the bridge structure 105A and the via plugs 106A and 108 are structures that support (reinforce) the trench wiring 104A or the entire semiconductor device, and in the manufacturing process of the semiconductor device, The wiring structure is prevented from being damaged. For example, the wiring structure is prevented from being broken or deformed by a stress caused by CMP, a stress change caused by heat treatment or plasma, or a stress applied when wet treatment is performed.

  Such a reinforcing structure can be formed in various shapes and structures.

  FIG. 10 is a partial cross-sectional view of the semiconductor device shown in FIG. 4L. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 10, for example, the via plug 106A, which is a reinforcing structure that supports the trench wiring 104A, has a structure that is not connected to wiring other than the trench wiring 104A.

  For example, the via plug 106 </ b> A may be formed so that the tip of the via plug 106 </ b> A penetrates the cap film 101, or may be formed so as to be half-immersed in the cap film 101. Further, the tip may be formed so as to touch the cap film 101.

  For example, when the cap layer 101 is formed so that the tip of the via plug 106A is partially submerged, a step is formed in the cap film 101 by an etch back method or a step is formed by a lift-off method. do it.

  Further, the reinforcing structure is not limited to the above structure. For example, FIG. 11 shows a modification of the semiconductor device shown in FIG. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 10, in the semiconductor device shown in the figure, in addition to the via plug 106A, via plugs 108, 110, 106B, 111, and a bridge structure 109 are formed as a reinforcing structure.

  For example, the via plugs 108 and 110 are formed to support the cap film 101 and the cap film 601. When forming the via plugs 108 and 110, in the step shown in FIG. 4B, a via hole penetrating the insulating layer 102 is formed in the insulating layer 102, and in the step shown in FIG. A via plug may be formed by embedding a conductive material such as Cu. The via plugs 108 and 110 contribute to improving the strength of the entire semiconductor device.

  The bridge structure 109 is a reinforcing structure formed so as to connect the via plug 108 and the trench wiring 104A. The bridge structure 109 can be formed in the same manner as the bridge structure 105A.

  For example, in the step shown in FIG. 4B, a bridge groove that connects the via hole for forming the trench 104 and the via plug 108 is formed in the insulating layer 102, and in the step shown in FIG. For example, the bridge structure 109 may be formed by embedding a conductive material such as Cu.

  It should be noted that the insulating layer 201 may be removed, and the lower layer of the trench wiring 104A may have a structure in which the interlayer insulating layer is similarly deleted.

  Further, such a reinforcing structure is not limited to the layer in which the trench wiring 104A is formed, and may be formed in an upper layer or a lower layer. For example, in the insulating layer 201, the via plug 106B connected to the via plug 106A is formed, and similarly, the via plug 201 connected to the via plug 110 is formed. As described above, the reinforcing structure can be configured by various shapes and structures.

  Further, this figure shows a configuration example of a MOS transistor which is an example of a semiconductor element formed on a semiconductor substrate connected to the wiring structure according to this embodiment. However, the structure in the middle of the connection between the MOS transistor and the wiring structure is partially omitted.

  The MOS transistor is formed on a semiconductor substrate 301 made of silicon, and is formed in an element formation region separated by an element isolation insulating film 302 formed on the semiconductor substrate. In the element isolation region, a patterned gate insulating film 303 is formed, and a gate electrode 304 is formed on the gate insulating film 303.

  In addition, a source region 306A and a drain region 306B are formed to face each other with a channel region directly below the gate insulating film 303 in which carriers move.

  In this case, an insulating film 305 is formed on the side wall surface of the gate electrode 304. In the source region 306A and the drain region 306B, the impurity diffusion region is shallow in the region covered with the insulating film 305. The impurity diffusion region is formed deeper in the portion not covered with the insulating film 305.

  Insulating layers 309 and 310 are stacked so as to cover the gate electrode 304 and the source region 306A and drain region 306B. In the insulating layer 309, a contact wiring 307 made of, for example, W (tungsten) connected to the source region 306A and the drain region 306B is formed, and the insulating layer 310 is connected to the contact wiring 307. A trench wiring 308 is formed.

  Further, the semiconductor substrate is not limited to the MOS transistor, and various elements such as a bipolar transistor, a capacitor, a photoelectric conversion element, and a light emitting element may be formed.

  Further, the configuration shown in the figure is an example, and the invention is not limited to the configuration shown in the figure, and it is obvious that various other reinforcing structures can be installed.

  In the manufacturing method shown in the first embodiment, the interlayer insulating film is repeatedly removed, reformed, and re-removed for each wiring structure, and the wiring structure is laminated to form a multilayer wiring structure. It is not limited to. For example, as shown below, interlayer insulating films respectively formed around a plurality of wiring structures can be simultaneously dissolved and re-formed and removed. Hereinafter, a method of manufacturing the semiconductor device according to the present embodiment will be described step by step based on FIGS. 12A to 12G.

  First, in the step shown in FIG. 12A, the cap film 503 and the insulating layer 504 are stacked on the insulating layer 501 in which the trench wiring 502 is formed in the same manner as the step shown in FIG. 4A of the first embodiment. The insulating layers 501 and 504, the cap film 503, and the trench wiring 502 in this example correspond to the insulating layers 201 and 102, the cap film 101, and the trench wiring 202 in Example 1, respectively, and are formed by the same method. can do.

  Next, in the step shown in FIG. 12B, via plugs 505, 506, 508 and trench wiring 507 are formed in the insulating layer 504 in the same manner as the steps shown in FIGS. 4B to 4G of the first embodiment. The via plugs 505, 506, 508 and the trench wiring 507 in this embodiment correspond to the via plugs 103A, 106A, 110 and the trench wiring 104A in the first embodiment, and can be formed by the same method. Here, a lower layer wiring structure comprising the trench wiring 507 and the via plugs 505, 506, 508 is formed.

  Next, in a step shown in FIG. 12C, an insulating layer 509 is formed on the insulating layer 504. In this case, no cap film is formed between the insulating layer 504 and the insulating layer 509. The insulating layer 504 and the insulating layer 509 are preferably made of the same material (porous material).

  Next, via plugs 510 and 511 and trench wirings 512 are formed in the insulating layer 509 in the same manner as in the step shown in FIG. 9B. In this case, the via plugs 510 and 511 can be formed in the same manner as the via plugs 506 and 505, and the trench wiring 512 can be formed in the same manner as the trench wiring 507. Here, an upper wiring structure composed of the trench wiring 512 and the via plugs 510 and 511 is formed.

  Next, in the step shown in FIG. 12E, the insulating layers 509 and 504 are removed by wet etching using a chemical solution, for example, in the same manner as in the step shown in FIG. Further, in the same manner as in Example 1, a diffusion preventing film is formed on the surfaces of the lower layer wiring structure and the upper layer wiring structure. Prior to the formation of the diffusion preventing film, it is preferable to provide a step of reducing the oxide film on the surface of the lower wiring structure and the upper wiring structure.

  Next, in the step of FIG. 12F, in the same manner as the step shown in FIG. 4F of Example 1, an insulating layer 513 made of, for example, a porous material is formed so as to fill the lower layer wiring structure and the upper layer wiring structure. Form.

  Next, in the step shown in FIG. 12G, the insulating layer 513 is polished by CMP, for example, so that the trench wiring 512 is exposed, and further, the cap film 514 is covered so as to cover the trench wiring 512 and the insulating layer 514. Form. Further, the insulating layer 514 is removed in the same manner as the steps shown in FIGS. 4I to 4L of the first embodiment.

  Thereafter, by repeating the steps shown in FIGS. 12A to 12G, a multilayer wiring can be formed in an upper layer.

  In the case of this embodiment, it is not necessary to form a cap film between the insulating layer 504 and the insulating layer 509. In addition, the insulating layers 504 and 509 are removed in the same step, and the insulating layer 513 corresponding to the insulating layers 504 and 509 is re-formed in one step and further removed. Therefore, there is an effect that the manufacturing process of the semiconductor device is simplified.

  As described above, the structure of the insulating layer to be removed and the insulating layer to be re-formed can be variously modified and changed.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the specific embodiments described above, and various modifications and changes can be made within the scope described in the claims.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the manufacturing method of a semiconductor device with which the damage given to an interlayer insulation film was suppressed.

It is FIG. (1) which shows the manufacturing method of the conventional semiconductor device. It is FIG. (2) which shows the manufacturing method of the conventional semiconductor device. It is FIG. (3) which shows the manufacturing method of the conventional semiconductor device. It is FIG. (4) which shows the manufacturing method of the conventional semiconductor device. It is the figure which compared the etching rate of the various types of insulating film in an acid solution and an alkali solution. It is the figure which compared the etching rate of various types of insulating films in a hydrofluoric acid (HF) solution. FIG. 6 is a diagram (part 1) illustrating a method for manufacturing a semiconductor device according to a first embodiment, following a procedure; FIG. 6 is a diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment with reference to a procedure. FIG. 6 is a diagram (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment, following a procedure; FIG. 9 is a diagram (No. 4) illustrating the manufacturing method of the semiconductor device according to Example 1 by following the procedure; FIG. 5 is a diagram (No. 5) illustrating the manufacturing method of the semiconductor device according to the example 1 with a step by step; FIG. 6 is a diagram (No. 6) illustrating the manufacturing method of the semiconductor device according to Example 1 by following the procedure; FIG. 7 is a diagram (No. 7) illustrating the manufacturing method of the semiconductor device according to Example 1 by following the procedure. FIG. 8 is a diagram (No. 8) illustrating the manufacturing method of the semiconductor device according to Example 1 by following the procedure; FIG. 9 is a diagram (No. 9) illustrating the manufacturing method of the semiconductor device according to Example 1 according to the procedure; FIG. 10 is a diagram (No. 10) illustrating the manufacturing method of the semiconductor device according to Example 1 according to a procedure; FIG. 11 is a diagram (No. 11) illustrating the manufacturing method of the semiconductor device according to Example 1 by following the procedure; FIG. 12 is a diagram (No. 12) illustrating the manufacturing method of the semiconductor device according to Example 1 by following a procedure; 6 is a diagram illustrating an example of a configuration of a separation structure used in the semiconductor device of Example 1. FIG. FIG. 6 is a cross-sectional view of the separation structure in FIG. 5. It is the example which formed the support structure in the isolation | separation structure of FIG. It is a figure which shows another structural example of a support structure. It is a figure which shows another example of a structure of a support structure. FIG. 4D is a cross-sectional view of the semiconductor device shown in FIG. 4L. It is a modification of the semiconductor device shown in FIG. FIG. 6 is a diagram (part 1) illustrating a method for manufacturing a semiconductor device according to a second embodiment with a step-by-step procedure; FIG. 6 is a second diagram illustrating a method for fabricating a semiconductor device according to a second embodiment, following a procedure; FIG. 10 is a diagram (No. 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment, following a procedure. FIG. 14 is a diagram (No. 4) illustrating the manufacturing method of the semiconductor device according to Example 2 by following the procedure. FIG. 9 is a diagram (No. 5) illustrating the manufacturing method of the semiconductor device according to Example 2 according to the procedure. FIG. 6 is a diagram (No. 6) illustrating the manufacturing method of the semiconductor device according to Example 2 by following the procedure. FIG. 7 is a diagram (No. 7) illustrating the manufacturing method of the semiconductor device according to Example 2 by following the procedure.

Explanation of symbols

1, 4, 6, 201, 102, 107, 309, 310, 402, 404, 406, 408, 501, 504, 513 Insulating layer 5 Etch stopper layer 3, 7, 101, 401, 403, 405, 407, 409 , 503, 514 Cap film 2, 12, 202, 104A, 411, 415, 507, 512 Trench wiring 11, 103A, 106A, 106B, 108, 110, 111, 410, 412, 413, 414, 505, 506, 508 , 510, 511 Via plug 9, 103, 106 Via hole 10, 104 Trench 650, 700 Isolation structure 651, 652, 653, 701, 702, 703 Pattern structure

Claims (20)

A method of manufacturing a semiconductor device including a multilayer wiring structure formed by a dual damascene method,
A wiring structure forming step of forming a wiring structure made of a conductive material embedded in the first insulating layer;
A first insulating layer removing step of removing the first insulating layer to expose the wiring structure;
An insulating layer burying step of forming a second insulating layer so as to fill the wiring structure;
A cap film forming step of forming a cap film on the second insulating layer;
And a second insulating layer removing step of removing the second insulating layer.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first insulating layer removing step, the first insulating layer is removed by wet etching using a chemical solution.   3. The method of manufacturing a semiconductor device according to claim 1, wherein, in the second insulating layer removing step, the second insulating layer is removed by wet etching using a chemical solution. The second insulating layer removing step includes a supply port forming step of forming a supply port for supplying the chemical solution to the second insulating layer in the cap film,
The method for manufacturing a semiconductor device according to claim 3, further comprising: an etching medium supply step of supplying the chemical solution to the second insulating layer from the supply port.   After the second insulating layer removing step, a support structure is formed that forms a support structure that supports the cap film and a lower insulating layer formed in a lower layer of the wiring structure at a position corresponding to the supply port. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the support structure is formed by a CVD method.   The semiconductor device according to claim 5, wherein a plurality of the support structures are formed on the lower insulating layer.   7. The method of forming a semiconductor device according to claim 5, wherein the support structure is formed so as to surround the periphery of the wiring structure.   In the wiring structure forming step, a trench wiring and a via pug constituting the wiring structure are formed, and the region where the first insulating layer is formed is formed in the supporting structure forming step. 9. The method of manufacturing a semiconductor device according to claim 5, wherein a separation structure is formed that separates into a region to be formed and a region in which the support structure is not formed.   8. The method of manufacturing a semiconductor device according to claim 6, wherein the isolation structure has a plurality of pattern structures made of the conductive material and formed on the lower insulating layer.   11. The method of manufacturing a semiconductor device according to claim 10, wherein in the etching medium supply step, the chemical solution is supplied to the second insulating layer from between the plurality of pattern structures.   12. The method of manufacturing a semiconductor device according to claim 1, wherein a reinforcing structure made of the conductive material that reinforces the wiring structure is formed in the wiring structure forming step.   The method of manufacturing a semiconductor device according to claim 1, wherein the conductive material is made of Cu.   14. The manufacturing method of a semiconductor device according to claim 13, further comprising a diffusion prevention film forming step of forming a diffusion prevention film of the conductive material on the exposed surface of the wiring structure after the first insulating layer removing step. Method.   15. The method of manufacturing a semiconductor device according to claim 14, wherein in the diffusion prevention film forming step, a nitriding process is performed to nitride the surface of the wiring structure.   16. The method of manufacturing a semiconductor device according to claim 14, wherein a reduction step of removing the exposed oxide film on the surface of the wiring structure is performed before the diffusion prevention film forming step.   17. The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating layer is made of a porous material.   The method for manufacturing a semiconductor device according to claim 17, wherein the porous material is made of a porous silica material.   The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating layer is made of a porous material.   The method for manufacturing a semiconductor device according to claim 19, wherein the porous material is made of a porous silica material.

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