CN102903698A - Semiconductor device and integrated circuit - Google Patents
Semiconductor device and integrated circuit Download PDFInfo
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- CN102903698A CN102903698A CN2012104139226A CN201210413922A CN102903698A CN 102903698 A CN102903698 A CN 102903698A CN 2012104139226 A CN2012104139226 A CN 2012104139226A CN 201210413922 A CN201210413922 A CN 201210413922A CN 102903698 A CN102903698 A CN 102903698A
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Abstract
The invention provides a semiconductor device and an integrated circuit. The semiconductor device comprises two parallel metal connecting wires, wherein each metal connecting wire is provided with a first metal layer provided with at least one gap, a metal plug and a second metal layer formed on the gap, each second metal layer is connected with each first metal layer through each metal plug, and at least part of gap positions of the two metal connecting wires are staggered mutually. Due to adoption of the semiconductor device, the parasitic capacitance generated by the two metal connecting wires can be greatly reduced.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly a kind of semiconductor device and integrated circuit.
Background technology
Along with the integrated circuit integrated level is more and more higher, semiconductor device quantity integrated in the integrated circuit is also more and more, integrated circuit is in order to realize certain function, relevant semiconductor device need to be connected with each other, usually, be formed with metal connecting line at semiconductor device, be connected to metal connecting line by outside interconnection line more relevant semiconductor device is connected.
As shown in Figure 1, the semiconductor device 100 in prior art comprises: a substrate 101, be formed at active area 102 in the substrate 101, be formed at grid 103 on the active area 102, be formed at the first metal connecting line 104 and the second metal connecting line 105 on the described grid 103 both sides substrates 101.
As shown in Figure 2, described the first metal connecting line 104 and the second metal connecting line 105 are arranged at described grid 103 tops and are arranged in the same aspect that is parallel to substrate 101 usually.Like this, the first metal connecting line 104 and the second metal connecting line 105 can form a parasitic capacitance as two battery lead plates (electric pole plate and lower electrode plate) respectively.Concerning this parasitic capacitance, described the first metal connecting line 104 and the second metal connecting line 105 with the parallel direction of grid 103 on overlapping area all be effective battery lead plate area.Described battery lead plate area is larger, and parasitic capacitance is also larger.
Along with the raising of integrated circuit integrated level, dimensions of semiconductor devices is more and more less, so parasitic capacitance and dead resistance will be increasing on the impact of semiconductor device characteristic.In some special application, for example some radio circuits need to reduce the parasitic capacitance between metal connecting line as far as possible, with the coupling of less radiofrequency signal between the different metal line, and can tolerate that certain metal connecting line resistance raises.
Therefore, hope can propose a kind of semiconductor device that can effectively reduce parasitic capacitance, with adapt to these especially needs reduce the parasitic capacitance between metal connecting line and can tolerate the application that certain metal connecting line resistance raises.
Summary of the invention
The invention provides a kind of semiconductor device and integrated circuit, reach the purpose that reduces parasitic capacitance, to solve above-mentioned parasitic capacitance to the distinct issues that affect of large-scale integrated circuit.
For solving the problems of the technologies described above, the invention provides a kind of semiconductor device, comprise: the two strip metal lines that are parallel to each other, described metal connecting line comprises: have the second metal level on the described gap of the first metal layer, metal plug and formation at least one gap, described the second metal level is connected with described the first metal layer by described metal plug, and the interstitial site of described two strip metal lines is at least part of to be staggered mutually.
Optionally, the interstitial site of described two strip metal lines staggers fully mutually.
Optionally, the interstitial site of described two strip metal lines part staggers mutually.
Optionally, the width range in described gap is 0.5 μ m～5 μ m.
Optionally, described second layer metal layer covers described gap fully, and stacked with the part the first metal layer.
Optionally, the area of the laminated portions of described the second metal level and described the first metal layer is greater than the cross-sectional area of described metal plug.
Optionally, described metal plug the first metal layer and and its equitant second metal level between.
Optionally, described semiconductor device also comprises:
One substrate;
Be formed at the active area in the described substrate; And
Be formed at the grid on the active area,
Wherein, described two strip metal lines are formed on the substrate of described grid both sides, and are parallel to grid.
Accordingly, also provide a kind of integrated circuit that adopts described semiconductor device.
Semiconductor device provided by the present invention comprises: the two strip metal lines that are parallel to each other, described metal connecting line comprises the second metal level on the described gap of the first metal layer, metal plug and formation with at least one gap, described the second metal level is connected with described the first metal layer by described metal plug, and the interstitial site of described two strip metal lines is at least part of to be staggered mutually.Because described the second metal level is connected with described the first metal layer by described metal plug, that is to say, the first metal layer separates the different aspect that is positioned at the second metal level by metal plug, simultaneously, the interstitial site of two strip metal lines is at least part of to be staggered mutually, so that wherein a position certainty of the second metal level of a strip metal line is corresponding with a position of the first metal layer of another strip metal line, but because first layer metal layer and second layer metal are positioned at different layers, so it is farther that the distance between first layer metal layer and the second layer metal becomes, producing parasitic capacitance can significantly descend.And in order to place metal plug, only have the position of small part the first metal layer mutually corresponding in the two strip metal lines.Therefore, for the parasitic capacitance that is produced by two strip metal lines, its effective relative area only has the mutually area of corresponding part the first metal layer of position.With respect to prior art, effective relative area of its parasitic capacitance is greatly diminished, and it is farther that the distance between first layer metal layer and the second layer metal becomes, thereby has realized reducing the purpose of parasitic capacitance.
Description of drawings
Fig. 1 is the vertical view of the semiconductor device of prior art;
Fig. 2 is the sectional drawing of the semiconductor device of prior art;
Fig. 3 is the vertical view of the semiconductor device of one embodiment of the invention;
Fig. 4 is along the cutaway view of AA ' line among Fig. 3;
Fig. 5 is along the cutaway view of BB ' line among Fig. 3.
Need to prove, accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Note, the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
Core concept of the present invention is, for the two strip metal lines that are parallel to each other in the semiconductor device, its metal connecting line is set to comprise the first metal layer, metal plug and the second metal level with at least one gap, described the second metal level is connected with described the first metal layer by described metal plug, and the interstitial site of described two strip metal lines is at least part of to be staggered mutually.Mutually stagger because the interstitial site of two strip metal lines is at least part of, so that effective relative area of the parasitic capacitance that is produced by two strip metal lines lowers greatly, thereby thereby can realize reducing the purpose of parasitic capacitance.
Implementation situation of the present invention for convenience of description, the below describes as an example of transistor example.Should be understood that, the metal connecting line of semiconductor device of the present invention can one be applied to various semiconductor device with metal connecting line, is not limited to transistor.
In order to make purpose of the present invention, technical scheme and advantage are clearer, further elaborate below in conjunction with accompanying drawing.
As shown in Figure 3, the semiconductor device of one embodiment of the invention (transistor) 200 comprises: a substrate 201, be formed at active area 202 in the described substrate 201, be formed at the grid 203 on the active area 202 and be formed at two strip metal lines 204 on the described grid 203 both sides substrates 201.Wherein, described two strip metal lines 204 are parallel to each other, and are parallel to described grid 203.
As shown in Figure 3, described metal connecting line 204 comprises: have the first metal layer 206, the metal plug 207 at least one gap 205 and form the second metal level 208 on the described gap 205.The gap 205 position parts of described two strip metal lines stagger mutually.
As shown in Figure 4, described metal plug 207 is between described the first metal layer 206 and the second metal level 208, and described the second metal level 208 is connected with described the first metal layer 206 by described metal plug 207, and other zones are filled by dielectric layer 210.That is to say, the first metal layer 206 and the second metal level 208 that metal plug 207 will be positioned at different aspects link together, thereby form metal connecting line 204.In conjunction with Fig. 3, for the first metal layer 206 shown in guaranteeing can fully be connected with the second metal level 208, described second layer metal layer 208 is wanted to cover described gap 205 fully, and stacked with described part the first metal layer 206, described metal plug 207 is located in the lamination area 209 of second layer metal layer 208 and the first metal layer 206.Because the gap of described two strip metal lines 205 position parts stagger mutually, in conjunction with Fig. 3 and Fig. 4, can find out, on the section at described lamination area 209 places, specifically, on the AA ' line such as Fig. 3, the first metal layer 206 of one strip metal line is inevitable corresponding with the first metal layer 206 of another strip metal line, and the first metal layer 206 of two strip metal lines 204 belongs to same aspect, therefore, there is effective relative area in two strip metal lines in lamination area 209 interior meetings, thereby produce parasitic capacitance.In order to reduce the parasitic capacitance of this part, described second layer metal layer 208 is the smaller the better with the lamination area area of the first metal layer 206, but in order to guarantee the connection effect of metal plug 207, the area of described lamination area should be greater than the cross-sectional area of described metal plug 207.
Because the gap of described two strip metal lines 205 position parts stagger mutually, in conjunction with Fig. 3 and Fig. 5, can find out, a position of the second metal level 206 of and another strip metal line inevitable in a position of the second metal level 208 of a strip metal line is corresponding, that is to say, the part that mutually staggers in two strip metal line gaps 205, corresponding with the first metal layer 206 is the second metal level 208.And the first metal layer 206 and the second metal level 208 are positioned at different layers, therefore in the part that mutually staggers in two strip metal line gaps 205, effective relative area of its parasitic capacitance is greatly diminished, it is farther that distance between first layer metal layer and the second layer metal becomes, so parasitic capacitance can decrease.
Need to prove for Fig. 4 and Fig. 5, other parts except grid structure 203, the first metal layer 206 and metal plug 207 under the second metal level 208 aspects, filled up by dielectric layer 210, described dielectric layer 210 can be understood for a person skilled in the art, and therefore no further details to be given herein.
This shows, the parasitic capacitance that two strip metal lines produce mainly is present in the parasitic capacitance of two strip metal lines in the lamination area 209, and the parasitic capacitance of the part that mutually staggers in two strip metal line gaps 205 can decrease.Therefore, in order to reduce parasitic capacitance, described lamination area 209 is the smaller the better, and the part that mutually staggers in two strip metal line gaps 205 then is the bigger the better, and perhaps the width L scope in gap 205 is the bigger the better.In Fig. 3, the width L in described each gap 205 is identical, but, it will be appreciated that, the width L that the present invention does not limit each gap 205 is necessary identical, staggers fully in order to make gap 205, can adjust as required the width L in each gap 205, certainly, also can adjust the quantity in gap.Along with the cross-sectional area that dwindles metal plug 207 of lamination area 209 can be along with dwindling, width L scope along with gap 205 becomes large simultaneously, the minimizing of gap 205 quantity, the quantity of metal plug 207 also can reduce, thereby after electric current arrives active areas 202 by metal plug 207, need the farther distance of drift could arrive raceway groove, can be raise to the equivalent resistance channel region by metal plug 207, this can cause that transistorized source omits living resistance rising; Therefore when reducing the area of lamination area 209, also want the source of balanced transistor to omit the negative effect that living resistance raises and causes considering to reduce parasitic capacitance.Preferably, the width L scope in described gap 205 is 0.5 μ m～5 μ m.In order to reduce parasitic capacitance as far as possible, the interstitial site 205 of described two strip metal lines can be staggered fully mutually simultaneously, the parasitic capacitance between such two strip metal connecting lines just mainly occurs between the lamination area 209 interior two strip metal lines.
Accordingly, by the integrated circuit that above-mentioned semiconductor device 200 forms, also be the protection range of technical solution of the present invention.
In the above-described embodiments, be the parasitic capacitance that how to reduce between first layer metal layer and the second layer metal layer be that example describes, should be understood that, described first layer metal and second layer metal can be any two metal layers in the semiconductor device, that is to say that inventive point of the present invention can extend to any can generation on the two metal layers of parasitic capacitance.
In sum, in semiconductor device provided by the present invention, described metal connecting line has the second metal level on the described gap of the first metal layer, metal plug and formation at least one gap, described the second metal level is connected with described the first metal layer by described metal plug, and the interstitial site of described two strip metal lines is at least part of to be staggered mutually.Therefore the first metal layer separates the different aspect that is positioned at the second metal level by metal plug, simultaneously, the interstitial site of two strip metal lines is at least part of to be staggered mutually, so that wherein the first metal layer of a strip metal line a position certainty is corresponding with a position of the second metal level of another strip metal line, but because first layer metal layer and second layer metal are positioned at different layers, so parasitic capacitance can decrease.Therefore, the parasitic capacitance that two strip metal lines produce mainly is present in the parasitic capacitance of two strip metal lines in the lamination area, and relative to existing technologies, effective relative area of two strip metal lines then is greatly diminished in the lamination area, thereby has realized reducing the purpose of parasitic capacitance.
Be understandable that, although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. semiconductor device, comprise: the two strip metal lines that are parallel to each other, it is characterized in that, described metal connecting line comprises: have the second metal level on the described gap of the first metal layer, metal plug and formation at least one gap, described the second metal level is connected with described the first metal layer by described metal plug, and the interstitial site of described two strip metal lines is at least part of to be staggered mutually.
2. semiconductor device according to claim 1 is characterized in that, the interstitial site of described two strip metal lines staggers fully mutually.
3. semiconductor device according to claim 1 is characterized in that, the interstitial site part of described two strip metal lines staggers mutually.
4. according to claim 1 to the described semiconductor device of 3 any one, it is characterized in that, the width range in described gap is 0.5 μ m～5 μ m.
5. semiconductor device according to claim 1 is characterized in that, described second layer metal layer covers described gap fully, and stacked with described part the first metal layer.
6. semiconductor device according to claim 5 is characterized in that, the area of the laminated portions of described the second metal level and described the first metal layer is greater than the cross-sectional area of described metal plug.
7. semiconductor device according to claim 5 is characterized in that, described metal plug described the first metal layer and and its equitant second metal level between.
8. semiconductor device according to claim 1 is characterized in that, described semiconductor device also comprises:
One substrate;
Be formed at the active area in the described substrate; And
Be formed at the grid on the active area,
Wherein, described two strip metal lines are formed on the substrate of described grid both sides, and are parallel to described grid.
9. integrated circuit that has adopted according to claim 1 any one described semiconductor device in 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210413922.6A CN102903698B (en) | 2012-10-25 | 2012-10-25 | Semiconductor device and integrated circuit |
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| CN201210413922.6A CN102903698B (en) | 2012-10-25 | 2012-10-25 | Semiconductor device and integrated circuit |
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| CN102903698A true CN102903698A (en) | 2013-01-30 |
| CN102903698B CN102903698B (en) | 2017-02-08 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103390609A (en) * | 2013-07-24 | 2013-11-13 | 上海宏力半导体制造有限公司 | Semiconductor device and forming method thereof |
| WO2023206712A1 (en) * | 2022-04-26 | 2023-11-02 | 长鑫存储技术有限公司 | Three-dimensional memory and forming method therefor |
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| US6239025B1 (en) * | 1996-10-08 | 2001-05-29 | Sgs-Thomson Microelectronics S.A. | High aspect ratio contact structure for use in integrated circuits |
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| CN103390609A (en) * | 2013-07-24 | 2013-11-13 | 上海宏力半导体制造有限公司 | Semiconductor device and forming method thereof |
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| WO2023206712A1 (en) * | 2022-04-26 | 2023-11-02 | 长鑫存储技术有限公司 | Three-dimensional memory and forming method therefor |
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| CN102903698B (en) | 2017-02-08 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140423 |
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Effective date of registration: 20140423 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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