CN102903698B - Semiconductor device and integrated circuit - Google Patents
Semiconductor device and integrated circuit Download PDFInfo
- Publication number
- CN102903698B CN102903698B CN201210413922.6A CN201210413922A CN102903698B CN 102903698 B CN102903698 B CN 102903698B CN 201210413922 A CN201210413922 A CN 201210413922A CN 102903698 B CN102903698 B CN 102903698B
- Authority
- CN
- China
- Prior art keywords
- metal
- metal layer
- semiconductor device
- layer
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention provides a semiconductor device and an integrated circuit. The semiconductor device comprises two parallel metal connecting wires, wherein each metal connecting wire is provided with a first metal layer provided with at least one gap, a metal plug and a second metal layer formed on the gap, each second metal layer is connected with each first metal layer through each metal plug, and at least part of gap positions of the two metal connecting wires are staggered mutually. Due to adoption of the semiconductor device, the parasitic capacitance generated by the two metal connecting wires can be greatly reduced.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly to a kind of semiconductor device and integrated circuit.
Background technology
With integrated circuit integrated level more and more higher, integrated semiconductor device quantity in integrated circuit also gets more and more,
Integrated circuit, in order to realize certain function, needs related semiconductor device to be connected with each other, generally, in semiconductor device
On be formed with metal connecting line, then metal connecting line is connected to by external interconnections line related semiconductor device is connected.
As shown in figure 1, the semiconductor device 100 in prior art includes：One substrate 101, it is formed at having in substrate 101
Source region 102, the grid 103 being formed on active area 102, the first metal being formed on described grid 103 both sides substrate 101 connect
Line 104 and the second metal connecting line 105.
As shown in Fig. 2 generally described first metal connecting line 104 and the second metal connecting line 105 are arranged on described grid 103
Just and in the same aspect parallel to substrate 101.So, the first metal connecting line 104 and the second metal connecting line 105 are made respectively
For two battery lead plates（Electric pole plate and bottom electrode plate）A parasitic capacitance can be formed.For this parasitic capacitance, described first
Metal connecting line 104 and the second metal connecting line 105 are being all effective battery lead plates with the overlapping area in the parallel direction of grid 103
Area.Described electrode plate suqare is bigger, and parasitic capacitance is also bigger.
With the raising of integrated circuit integrated level, dimensions of semiconductor devices is less and less, therefore parasitic capacitance and parasitism electricity
The impact to semiconductor device characteristic for the resistance will be increasing.In some special applications, such as some radio circuits, need
Reduce the parasitic capacitance between metal connecting line as far as possible, with coupling between different metal line for the less radiofrequency signal, and can tolerate
Certain metal connecting line resistance raises.
Accordingly, it is desirable to be able to propose a kind of semiconductor device that can effectively reduce parasitic capacitance, special to adapt to these
Need the parasitic capacitance reducing between metal connecting line can tolerate the application that certain metal connecting line resistance raises.
Content of the invention
The present invention provides a kind of semiconductor device and integrated circuit, reaches the purpose reducing parasitic capacitance, above-mentioned to solve
The impact distinct issues to large-scale integrated circuit for the parasitic capacitance.
For solving above-mentioned technical problem, the present invention provides a kind of semiconductor device, including：Two metals being parallel to each other are even
Line, described metal connecting line includes：There is the first metal layer at least one gap, metal plug and form on described gap the
Two metal levels, described second metal layer is connected with described the first metal layer by described metal plug, described two metal connecting lines
Interstitial site at least partly mutually stagger.
Optionally, the interstitial site of described two metal connecting lines mutually staggers completely.
Optionally, the interstitial site of described two metal connecting lines partly mutually staggers.
Optionally, the width range in described gap is 0.5 μm～5 μm.
Optionally, described second layer metal layer is completely covered described gap, and is laminated with part the first metal layer.
Optionally, described second metal layer and the area of the laminated portions of described the first metal layer are more than described metal plug
Cross-sectional area.
Optionally, described metal plug is located at the first metal layer and and its equitant second metal layer between.
Optionally, described semiconductor device also includes：
One substrate；
It is formed at the active area in described substrate；And
It is formed at the grid on active area,
Wherein, described two metal connecting lines are formed on the substrate of described grid both sides, and parallel to grid.
Accordingly, also provide a kind of integrated circuit using described semiconductor device.
Semiconductor device provided by the present invention includes：Two metal connecting lines being parallel to each other, described metal connecting line includes
There is the second metal layer on the first metal layer, metal plug and the described gap of formation at least one gap, described second gold medal
Belong to layer to be connected with described the first metal layer by described metal plug, at least part of phase of interstitial site of described two metal connecting lines
Mutually stagger.Because described second metal layer is connected with described the first metal layer by described metal plug that is to say, that the first gold medal
Belong to layer and second metal layer is separated positioned at different aspects by metal plug, meanwhile, the interstitial site of two metal connecting lines is extremely
Small part mutually stagger so that position of the wherein second metal layer of a metal connecting line inevitable with another metal connecting line
The first metal layer a position corresponding, but be because that first layer metal layer and second layer metal are located at different layers, so
It is farther that the distance between first layer metal layer and second layer metal become, and producing parasitic capacitance can significantly decline.And in order to put
Put metal plug, in two metal connecting lines, only have the position of small part the first metal layer mutually corresponding.Therefore, for by two gold
For belonging to the parasitic capacitance that line produces, its effective relative area only has the face of the mutually corresponding part the first metal layer in position
Long-pending.For prior art, effective relative area of its parasitic capacitance is greatly diminished, first layer metal layer and the second layer
It is farther that the distance between metal becomes, it is achieved thereby that reducing the purpose of parasitic capacitance.
Brief description
Fig. 1 is the top view of the semiconductor device of prior art；
Fig. 2 is the sectional drawing of the semiconductor device of prior art；
Fig. 3 is the top view of the semiconductor device of one embodiment of the invention；
Fig. 4 is the sectional view in Fig. 3 along AA ' line；
Fig. 5 is the sectional view in Fig. 3 along BB ' line.
It should be noted that accompanying drawing is used for the present invention is described, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.And, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
The core concept of the present invention is, for two metal connecting lines being parallel to each other in semiconductor device, by its metal
Line is set to including the first metal layer with least one gap, metal plug and second metal layer, described second metal
Layer is connected with described the first metal layer by described metal plug, and the interstitial site of described two metal connecting lines is at least partly mutual
Stagger.Because two the interstitial site of metal connecting line at least partly mutually staggers so that the parasitism that produced by two metal connecting lines
Effective relative area of electric capacity lowers significantly, such that it is able to realize it is achieved thereby that reducing the purpose of parasitic capacitance.
For convenience of explanation the present invention be embodied as situation, to illustrate below taking transistor as a example.It should be understood that
, the metal connecting line of the semiconductor device of the present invention, one can be applied to the various semiconductor device with metal connecting line, and
It is not limited to transistor.
In order that the purpose of the present invention, technical scheme and advantage are clearer, come below in conjunction with the accompanying drawings to do further in detail
Explanation.
As shown in figure 3, the semiconductor device of one embodiment of the invention（Transistor）200 include：One substrate 201, it is formed at
Active area 202 in described substrate 201, the grid 203 being formed on active area 202 and be formed at described grid 203 both sides
Two metal connecting lines 204 on substrate 201.Wherein, described two metal connecting lines 204 are parallel to each other, and parallel to described grid
203.
As shown in figure 3, described metal connecting line 204 includes：There is the first metal layer 206, the metal at least one gap 205
Second metal layer 208 on connector 207 and the described gap 205 of formation.The gap 205 position part phase of described two metal connecting lines
Mutually stagger.
As shown in figure 4, described metal plug 207 is located between described the first metal layer 206 and second metal layer 208, institute
State second metal layer 208 to be connected with described the first metal layer 206 by described metal plug 207, other regions are by dielectric layer 210
Filling.That is, metal plug 207 will be connected to one positioned at the first metal layer 206 of different aspects and second metal layer 208
Rise, thus forming metal connecting line 204.In conjunction with Fig. 3, in order to ensure that shown the first metal layer 206 can be abundant with second metal layer 208
Connect, described second layer metal layer 208 will can be completely covered described gap 205, and with 206 layers of described part the first metal layer
Folded, described metal plug 207 is located in second layer metal layer 208 and the lamination area 209 of the first metal layer 206.Because institute
Partly mutually stagger in gap 205 position stating two metal connecting lines, in conjunction with Fig. 3 and Fig. 4 it can be seen that in described lamination area
On the section at 209 places, specifically, such as on the AA ' line of Fig. 3, the first metal layer 206 of a metal connecting line is inevitable and another
Article one, the first metal layer 206 of metal connecting line is corresponding, and the first metal layer 206 of two metal connecting lines 204 belongs to same layer
Face, therefore, can there is effective relative area in two metal connecting lines in lamination area 209, thus producing parasitic capacitance.In order to
Reduce the parasitic capacitance of this part, described second layer metal layer 208 more little with the lamination area area of the first metal layer 206 more
Good, however, to ensure that the connection effect of metal plug 207, the area of described lamination area should be more than described metal plug
207 cross-sectional area.
Because a gap 205 position part for described two metal connecting lines mutually staggers, in conjunction with Fig. 3 and Fig. 5, can see
Go out, in the inevitable second metal layer 206 with another metal connecting line in a position of the second metal layer 208 of a metal connecting line
A position corresponding that is to say, that the part that mutually staggers in two metal connecting line gaps 205, with the first metal layer 206
Corresponding is second metal layer 208.And the first metal layer 206 and second metal layer 208 are located at different layers, therefore in two gold
Belong to the part that mutually staggers in line gap 205, effective relative area of its parasitic capacitance is greatly diminished, first layer metal layer and
It is farther that the distance between second layer metal becomes, and therefore parasitic capacitance can be greatly lowered.
For Fig. 4 and Fig. 5 it should be noted that under second metal layer 208 aspect except grid structure 203, the first gold medal
Other parts beyond genus layer 206 and metal plug 207, are filled up by dielectric layer 210, and described dielectric layer 210 is for this
For the technical staff in field be it will be appreciated that, therefore no further details to be given herein.
As can be seen here, parasitic capacitance produced by two metal connecting lines is primarily present in interior two metals of lamination area 209
The parasitic capacitance of line, and the parasitic capacitance of the part that mutually staggers in two metal connecting line gaps 205 can be greatly lowered.Cause
This, in order to reduce parasitic capacitance, described lamination area 209 is the smaller the better, and the portion of mutually staggering in two metal connecting line gaps 205
Divide and be then the bigger the better, or the width L scope in gap 205 is the bigger the better.In figure 3, the width L phase in each gap 205 described
With it will be understood that the width L that the present invention does not limit each gap 205 must be identical, in order that gap 205 is complete
The completely wrong width L opening, can adjusting each gap 205 as needed, it is of course also possible to be adjusted to the quantity in gap.With
The cross-sectional area of metal plug 207 of reducing lamination area 209 can be with reducing, simultaneously with the width L scope in gap 205
Become big, the minimizing of gap 205 quantity, the quantity of metal plug 207 also can reduce, thus electric current is reached by metal plug 207
After active area 202, the farther distance that needs to drift about gets to raceway groove, by metal plug 207 to the interval equivalent resistance of raceway groove
Can raise, this can cause the source and drain dead resistance of transistor to raise；Therefore reduce parasitic capacitance in consideration and reduce lamination area
While 209 area, the source and drain dead resistance of balanced transistor is also wanted to raise the negative effect causing.Preferably, between described
The width L scope of gap 205 is 0.5 μm～5 μm.Simultaneously in order to reduce parasitic capacitance as far as possible, can be by described two metal connecting lines
Interstitial site 205 mutually stagger completely, the parasitic capacitance between such two metal contact wires just occur mainly in stacking area
Between interior two metal connecting lines in domain 209.
Accordingly, the integrated circuit being made up of above-mentioned semiconductor device 200, is also the protection model of technical solution of the present invention
Enclose.
In the above-described embodiments, it is to be how to reduce the parasitic capacitance between first layer metal layer and second layer metal layer
Example illustrate it should be appreciated that described first layer metal and second layer metal can be any in semiconductor device
Two metal layers are that is to say, that the inventive point of the present invention can extend to any can generation in the two metal layers of parasitic capacitance.
In sum, in semiconductor device provided by the present invention, described metal connecting line has at least one gap
Second metal layer on the first metal layer, metal plug and the described gap of formation, described second metal layer is passed through described metal and is inserted
Plug is connected with described the first metal layer, and the interstitial site of described two metal connecting lines at least partly mutually staggers.Therefore first gold medal
Belong to layer and second metal layer is separated positioned at different aspects by metal plug, meanwhile, the interstitial site of two metal connecting lines is extremely
Small part mutually stagger so that position of the wherein the first metal layer of a metal connecting line inevitable with another metal connecting line
Second metal layer a position corresponding, but be because that first layer metal layer and second layer metal are located at different layers, so
Parasitic capacitance can be greatly lowered.Therefore, parasitic capacitance produced by two metal connecting lines is primarily present in two in lamination area
The parasitic capacitance of bar metal connecting line, and relative to existing technologies, effective relative area of two metal connecting lines in lamination area
Then it is greatly diminished, it is achieved thereby that reducing the purpose of parasitic capacitance.
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
The technology contents that the disclosure above all can be utilized are made many possible variations and modification, or are revised as to technical solution of the present invention
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
Interior.
Claims (8)
1. a kind of semiconductor device, including：Two metal connecting lines being parallel to each other are it is characterised in that also include：
One substrate；
It is formed at the active area in described substrate；And
It is formed at the grid on active area；
Wherein, described two metal connecting lines are formed on the substrate of described grid both sides, and parallel to described grid；
Described metal connecting line includes：Have on the first metal layer, metal plug and the described gap of formation at least one gap
Second metal layer, described second metal layer is connected with described the first metal layer by described metal plug, and described two metals are even
The interstitial site of line at least partly mutually staggers.
2. semiconductor device according to claim 1 is it is characterised in that the interstitial site of described two metal connecting lines is complete
Mutually stagger.
3. semiconductor device according to claim 1 is it is characterised in that the interstitial site part of described two metal connecting lines
Mutually stagger.
4. the semiconductor device according to claims 1 to 3 any one is it is characterised in that the width range in described gap
For 0.5 μm～5 μm.
5. semiconductor device according to claim 1 it is characterised in that described second metal layer be completely covered described between
Gap, and be laminated with partly described the first metal layer.
6. semiconductor device according to claim 5 is it is characterised in that described second metal layer and described the first metal layer
Laminated portions area be more than described metal plug cross-sectional area.
7. semiconductor device according to claim 5 is it is characterised in that described metal plug is located at described the first metal layer
And and its equitant second metal layer between.
8. a kind of integrated circuit employing semiconductor device as claimed in any of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210413922.6A CN102903698B (en) | 2012-10-25 | 2012-10-25 | Semiconductor device and integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210413922.6A CN102903698B (en) | 2012-10-25 | 2012-10-25 | Semiconductor device and integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102903698A CN102903698A (en) | 2013-01-30 |
| CN102903698B true CN102903698B (en) | 2017-02-08 |
Family
ID=47575871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210413922.6A Active CN102903698B (en) | 2012-10-25 | 2012-10-25 | Semiconductor device and integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102903698B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103390609B (en) * | 2013-07-24 | 2016-12-28 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and forming method thereof |
| CN117015229A (en) * | 2022-04-26 | 2023-11-07 | 长鑫存储技术有限公司 | Three-dimensional memory and forming method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239025B1 (en) * | 1996-10-08 | 2001-05-29 | Sgs-Thomson Microelectronics S.A. | High aspect ratio contact structure for use in integrated circuits |
| CN101567358A (en) * | 2009-05-27 | 2009-10-28 | 上海宏力半导体制造有限公司 | Power bus |
| JP4720414B2 (en) * | 2005-10-06 | 2011-07-13 | 日本ビクター株式会社 | Solid-state imaging device and manufacturing method thereof |
| CN102280421A (en) * | 2010-06-08 | 2011-12-14 | 三星电子株式会社 | Semiconductor devices with through-silicon vias |
| CN102629626A (en) * | 2011-02-04 | 2012-08-08 | 瑞萨电子株式会社 | Semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH021928A (en) * | 1988-06-10 | 1990-01-08 | Toshiba Corp | Semiconductor integrated circuit |
| JP2000332104A (en) * | 1999-05-17 | 2000-11-30 | Nec Corp | Semiconductor device and its manufacture |
| JP2006351732A (en) * | 2005-06-14 | 2006-12-28 | Sumitomo Heavy Ind Ltd | Process for fabricating semiconductor device |
| KR100782487B1 (en) * | 2006-08-21 | 2007-12-05 | 삼성전자주식회사 | Void-restricting structure, semiconductor devices having the void-restricting structure and methods of forming the same |
-
2012
- 2012-10-25 CN CN201210413922.6A patent/CN102903698B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239025B1 (en) * | 1996-10-08 | 2001-05-29 | Sgs-Thomson Microelectronics S.A. | High aspect ratio contact structure for use in integrated circuits |
| JP4720414B2 (en) * | 2005-10-06 | 2011-07-13 | 日本ビクター株式会社 | Solid-state imaging device and manufacturing method thereof |
| CN101567358A (en) * | 2009-05-27 | 2009-10-28 | 上海宏力半导体制造有限公司 | Power bus |
| CN102280421A (en) * | 2010-06-08 | 2011-12-14 | 三星电子株式会社 | Semiconductor devices with through-silicon vias |
| CN102629626A (en) * | 2011-02-04 | 2012-08-08 | 瑞萨电子株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102903698A (en) | 2013-01-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105575959B (en) | Integrated circuit device | |
| TW201719835A (en) | Semiconductor device having buried power rail and method of manufacturing the same | |
| CN105633137B (en) | A kind of slot gate power MOSFET device | |
| CN106252418A (en) | A kind of thin film transistor (TFT) | |
| JP2013517633A5 (en) | ||
| TW200943519A (en) | Improved methods of mid-frequency decoupling | |
| TW201901906A (en) | Semiconductor integrated circuit, and method of forming power rail for semiconductor integrated circuit | |
| CN101877315B (en) | Method for improving breakdown voltage of LDMOS devices | |
| CN104425454A (en) | Semiconductor device | |
| CN107154425A (en) | Semiconductor device | |
| CN102903698B (en) | Semiconductor device and integrated circuit | |
| CN104810349A (en) | Differential inductor | |
| CN106158804B (en) | A kind of semiconductor package and its semiconductor power device | |
| CN104425441B (en) | A kind of MOM capacitor | |
| KR20140052790A (en) | Differential moscap device | |
| CN106887410A (en) | The method for manufacturing switched capacitor dc-dc | |
| US10014214B2 (en) | Electronic device including moat power metallization in trench | |
| CN207338365U (en) | Integrated circuit | |
| CN104952853A (en) | Novel patterned-ground-shielded structure | |
| CN108091641A (en) | MIM capacitor and preparation method thereof | |
| CN203179895U (en) | IGBT with field stop structure | |
| CN102945839B (en) | A kind of high voltage interconnection structure of part field plate shielding | |
| CN201584411U (en) | Power chip with stacking package preformed vertical structure | |
| CN109994470A (en) | A kind of semiconductor power device | |
| CN104241200B (en) | A kind of power device and the integrated approach of control device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140423 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140423 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |