CN102184911A

CN102184911A - Miller parasitic capacitance shielding structure of high-power and high-frequency device

Info

Publication number: CN102184911A
Application number: CN2011100881602A
Authority: CN
Inventors: 张耀辉; 余庭; 赵一兵
Original assignee: KUNSHAN HUATAI ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: KUNSHAN HUATAI ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2011-04-08
Filing date: 2011-04-08
Publication date: 2011-09-14

Abstract

The invention discloses a Miller parasitic capacitance shielding structure of a high-power and high-frequency device. The structure is used for a high-power lateral diffused metal oxide semiconductor (LDMOS) device. The LDMOS device consists of two mutually symmetrical LDMOS structures, which are distributed on the two sides of a P-sink area. The structure is characterized in that: a metal interconnecting and shielding structure is arranged in the LDMOS device; and the metal interconnecting and shielding structure has the structure that: above heavily-doped source regions of the two LDMOS structures, the two heavily-doped source regions, a metal layer first wire and a metal layer second wire are connected through an interlayer through hole to form a metal interconnecting structure to shield a grid electrode bus. The device can achieve shielding through the metal interconnecting structure; a Miller parasitic capacitance is further reduced; and a power gain of the high-power and high-frequency device is improved.

Description

High-power high-frequency device Miller parasitic capacitance shielding construction

Technical field

The present invention relates to the semiconductor high power device, be specifically related to a kind of Miller parasitic capacitance shielding construction of high-power high-frequency device.

Background technology

The LDMOS device is the integrated high power solid state microwave power semiconductor device that microelectronic integrated circuit and microwave technology merge.LDMOS has the lateral channel structure, and drain electrode, source electrode and grid be all at chip surface, adopts double diffusion technique, carries out twice diffusion of boron phosphorus in succession at same photoetching window, can accurately determine channel length by the difference of twice horizontal junction depth of diffusion of impurities.Because its higher puncture voltage, the linearity is good, efficient is high and advantage such as cheap, its concentrated area is used in the high-power devices of high frequency such as mobile communication base station and airborne radar.

Miller capacitance (Miller Capacitance) is to be connected across the output of amplifier and the electric capacity between the input.The output capacitance of MOSFET is the covering capacitor C gd between grid and the drain electrode.In the common source configuration, Cgd just in time is connected across between input (grid) and the output (drain electrode), so Miller effect makes equivalent input capacitance increase, causes frequency characteristic to reduce.The gain of the high frequency power of LDMOS has direct relation with Miller capacitance Cgd, therefore how to reduce the Miller capacitance of device effectively and has conclusive effect for high frequency (greater than the 1GHz) gain characteristic of device.

People have adopted dummy Faraday shield grid and have reduced the Miller parasitic capacitance based on the various different structures that it develops at present, and Fig. 1 is the cross-sectional structure figure of existing LDMOS.Resistance is about on the P type substrate 11 of 0.005-0.01 Ω cm one deck high resistant epitaxial loayer 12, and the resistance of epitaxial loayer is roughly 20-30 Ω cm, and substrate 11 back sides have made one deck back of the body gold layer 16.Comprised highly doped source region 13 and highly doped drain region 14 in the epitaxial loayer 12, P-SINK zone 15 has been communicated with highly doped source region 13 and the gold of the back of the body below substrate layer 16 by through hole, makes electric current have low-resistance channel from the top device to the bottom.P-body layer 17 and drain region 18 are arranged between highly doped source region 13 in epitaxial loayer 12 and the highly doped drain region 14, and P-body layer 17 is the P type, and it has surrounded whole highly doped source region 13, and is communicated with P-sink zone 15; Drain region 18 is then near highly doped drain region 14, it has comprised slight doped n type LDD district 19 and time lightly doped n type NHV1 district 20, NHV1 district 20 is connected with the drain region, and main effect is the maximum current density that increases highly doped drain region 14, and can improve drain-source breakdown voltage.According to actual conditions, drain region 18 can comprise more NHV2 district or NHV3 district, and doping content increases successively.Above P-body layer 17 and drain region 18 underlapped parts grid 21 is arranged, the grid 21 general polysilicons that use are as material, and oxidized silicon 22 separates between it and the P-body layer.Grid 21 both sides are surrounded with oxide side wall 23 and are used to prevent that heavy dose of source from leaking to inject too leaks break-through near raceway groove so that with the generation source.Dummy Faraday shield grid 24 are arranged above grid 21, be used to reduce Miller capacitance Cgd.Be connected to grid bus (gate bus) 25, grid bus can be used for reducing the contact resistance of grid.Highly doped drain region 14 is by filling out lead 26 and the metal level 2 27 that the tungsten through hole is connected to metal level one.As a whole, the shortcoming of this structure is between grid bus 25 and the highly doped drain region 14 to produce bigger Miller capacitance Cgd, and this is not wish the phenomenon seen.

Summary of the invention

Goal of the invention of the present invention provides a kind of high-power high-frequency device Miller parasitic capacitance shielding construction, under the prerequisite that does not improve manufacturing cost, further reduce the Miller capacitance of LDMOS device effectively, to reach the purpose of the high frequency power gain that improves the LDMOS high power device.

To achieve the above object of the invention, the technical solution used in the present invention is: a kind of high-power high-frequency device Miller parasitic capacitance shielding construction, be used for the LDMOS device, described LDMOS device is made of two symmetrical mutually LDMOS structures that are distributed in both sides, P-sink zone, in the LDMOS device, be provided with metal interconnected shielding construction, described metal interconnected shielding construction is, above the highly doped source region of two LDMOS structures, two highly doped source regions, metal level one lead and metal level two leads connect and compose metal interconnect structure by the interlayer through hole grid bus are shielded.

Further technical scheme, above the highly doped source region of two LDMOS structures, the metal level three wires is connected with metal level two leads by the interlayer through hole, and both sides metal level three wires is communicated with.Realize better shield effectiveness thus.

Because the technique scheme utilization, the present invention compared with prior art has following advantage:

The present invention uses metal interconnect structure to realize shielding, has further reduced parasitic Miller capacitance, has improved the power gain of high-power high-frequency device.

Description of drawings

Fig. 1 is the sectional structure schematic diagram of LDMOS in the prior art;

Fig. 2 is the sectional structure schematic diagram of embodiment one;

Fig. 3 is the sectional structure schematic diagram of embodiment two.

Embodiment

Below in conjunction with drawings and Examples the present invention is further described:

Embodiment one: referring to the device cross-sectional structure figure that Figure 2 shows that after using metal interconnected shielding construction on existing LDMOS structure (as shown in Figure 1) basis.As can be seen from the figure two symmetrical mutually LDMOS structure distribution are on 15 both sides, P-sink zone, the highly doped source region 13 of two LDMOS respectively with the lead 28 of metal level three, the lead 29,30 of metal level two, the through hole of lead 31,32 each layers of metal level one by interlayer couples together and formed a kind of metal interconnect structure, and this metal interconnect structure is connected to back of the body gold layer 16 by P-body zone 17, P-sink zone 15 and P type substrate 11.Because back of the body gold layer 16 is a zero potential, thereby the metal interconnect structure that is similarly zero potential masks the power line between grid bus 25 and the highly doped drain region 14 and has further reduced Miller capacitance Cgd, makes power device can obtain better power gain.

Embodiment two: shown in accompanying drawing 3, on the basis of embodiment one structure, can simplify metal interconnect structure, from metal level two, no longer make lead 28 at metal level three, saved the technology of the through hole of the lead 29,30 of making the lead 28 that connects metal level three and metal level two like this, simplified metal interconnected shielding construction, also can reach simultaneously and reach the effect that reduces Miller capacitance Cgd by shadow shield.Totally-enclosed shielding construction shown in Figure 2 relatively, it is applicable to the situation that relative shielding requirements is not too high, but has technology and simplifies relatively, saves the advantage of cost.

Claims

1. high-power high-frequency device Miller parasitic capacitance shielding construction, be used for high-power LDMOS device, described LDMOS device is made of two symmetrical mutually LDMOS structures that are distributed in both sides, P-sink zone, it is characterized in that: in the LDMOS device, be provided with metal interconnected shielding construction, described metal interconnected shielding construction is, above the highly doped source region of two LDMOS structures, two highly doped source regions, metal level one lead and metal level two leads connect and compose metal interconnect structure by the interlayer through hole grid bus are shielded.

2. high-power high-frequency device Miller parasitic capacitance shielding construction according to claim 1, it is characterized in that: above the highly doped source region of two LDMOS structures, the metal level three wires is connected with metal level two leads by the interlayer through hole, and both sides metal level three wires is communicated with.