CN103515432B - P-type super-junction laterally bilateral diffusion MOS FET device - Google Patents
P-type super-junction laterally bilateral diffusion MOS FET device Download PDFInfo
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- CN103515432B CN103515432B CN201210206590.4A CN201210206590A CN103515432B CN 103515432 B CN103515432 B CN 103515432B CN 201210206590 A CN201210206590 A CN 201210206590A CN 103515432 B CN103515432 B CN 103515432B
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- 230000002146 bilateral effect Effects 0.000 title claims abstract description 14
- 238000009792 diffusion process Methods 0.000 title claims abstract description 14
- 230000001413 cellular effect Effects 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 6
- 238000010276 construction Methods 0.000 claims description 6
- 238000009826 distribution Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of p-type super-junction laterally bilateral diffusion MOS FET device, N-type substrate heavily doped region has N-type extension drift region；It is formed with cellular region and termination environment in N-type extension drift region；P-type semi-insulating post district is respectively provided with multiple p-type semi-insulating post district in cellular region and termination environment；Concentration is had to be higher than the p-type doped region in p-type semi-insulating post district respectively with top bottom described p-type semi-insulating post district；The semi-insulating post of p-type described in cellular region has gate trench between district；Flute surfaces is formed with gate oxidation films and inserts polysilicon formation grid；Well region is formed between described gate trench and p-type semi-insulating post district；Source region is formed on well region top；Source region and well region connect earth potential by contact hole.The present invention is improved by the doping content of p-type semi-insulating post district top and bottom, solves the breakdown voltage resistant value of device design, improves the overall vertical and horizontal breakdown voltage of device and reliability simultaneously.
Description
Technical field
The present invention relates to semiconductor device design field, particularly relate to a kind of p-type super-junction laterally bilateral diffusion MOS FET device.
Background technology
Fig. 1 show conventional superjunction structure and is applied to N-type longitudinal direction power MOS (Metal Oxide Semiconductor) device, i.e. N-type CooLMOS structure.It is
There are in heavily doped N-type silicon substrate 106 two doped with P type districts 102 of horizontal distribution, have between two lightly doped p type island regions 102
There is a lightly doped n type extension drift region 103, be respectively provided with heavily doped P type trap zone 104 about top and be positioned at P type trap zone 104
In heavily doped N-type district 105 (source-drain area), depositing polysilicon grid above middle channel region.In this structure turn on process only
There is majority carrier electronics, and there is no the participation of minority carrier, therefore, its switching loss and traditional power MOSFET
Identical, and the impurity doping concentration of its voltage support layer can improve nearly an order of magnitude；Additionally, due in vertical direction
Insert p type island region, the current lead-through electric charge of excess can be compensated.Add reverse bias voltage at drift layer, a horizontal electricity will be produced
, make PN junction exhaust.When voltage reaches certain value, drift layer is completely depleted, will play the effect of voltage support layer.Owing to mixing
Being greatly improved of miscellaneous concentration, under identical breakdown voltage, conducting resistance Ron can be substantially reduced, and even breaks through silicon limit, but
The planar gate structure of such devices can make both sides heavy doping p-well region 104 there is JFET pinchoff effect.
Summary of the invention
The technical problem to be solved is to provide a kind of p-type super-junction laterally bilateral diffusion MOS FET device, has horizontal stroke
To and longitudinally overall high-breakdown-voltage and high reliability.
For solving the problems referred to above, a kind of p-type super-junction laterally bilateral diffusion MOS FET device that the present invention provides, including: N-type serves as a contrast
End heavily doped region and N-type extension drift region, wherein:
N-type extension drift region is positioned on N-type substrate heavily doped region.
Having cellular region and termination environment in described N-type extension drift region, in the top plan view of device, termination environment is positioned at unit
Cellular region cincture is surrounded by outer ring, born of the same parents district.
In cross-sectional plane, described cellular region has two p-type semi-insulating post districts, termination environment has more multiple p-type half
Insulated column district, is uniformly distributed in the termination region.
Described multiple p-types semi-insulating post district, also each has the first p-type doped region bottom it, and top is respectively provided with
Two p-type doped regions.
In cellular region, between two p-type semi-insulating post districts, a groove, described trench wall surface is had to be formed with gate oxidation
Film, fills polysilicon and forms grid in groove.
Region between the both sides of described groove and p-type semi-insulating post district is respectively formed well region, forms source region on well region top,
Source region and well region connect earth potential by contact hole.
Further, described p-type semi-insulating post district is homogenous material, or semiconductor insulating material and insulant
Composite construction.
Further, when described p-type semi-insulating post district is the composite construction of semiconductor insulating material and insulant, partly lead
Body insulant is positioned against side, extension drift region.
Further, described contact hole is to penetrate source region directly to contact with well region, makes well region and source region share contact hole；Or
Person is off in source region, is injected by extra p-type hole, and formation contacts with well region.
Further, its surface, described termination environment or be formed with an oxygen, polysilicon or Metal field plate；It is away from cellular region
The outside in direction or be formed with field cut-off ring；Between its p-type semi-insulating post district or comprise the region in p-type semi-insulating post district the most not
Get rid of and be designed with p-type shallow implant.
Further, the doping content of described first p-type doped region and the second p-type doped region is the 2 of p-type semi-insulating post district
～5 times, and impurity is to be uniformly distributed or in the horizontal direction in the distribution that middle dense both sides are light.
The present invention is improved by the doping content of p-type semi-insulating post district top and bottom, solves resistance to the hitting of device design
Wear magnitude of voltage, improve the overall vertical and horizontal breakdown voltage of device and reliability simultaneously.
Accompanying drawing explanation
Fig. 1 is traditional N-type CoolMOS device.
Fig. 2 is the cross-section structure of p-type super-junction laterally bilateral diffusion MOS FET device of the present invention.
Fig. 3 is p-type semi-insulating post district top depression.
Fig. 4 is transverse electric field ionization by collision schematic diagram.
Description of reference numerals
1 be N-type substrate heavily doped region 2 be N-type extension drift region
31 is the first p-type doped region
32 is p-type semi-insulating post district
33 is the second p-type doped region
4 be gate trench 5 be gate oxidation films
6 be polysilicon gate 7 be well region
8 be source region 9 be contact hole
100 be cellular region 101 be termination environment
Detailed description of the invention
One p-type super-junction laterally bilateral diffusion MOS FET device of the present invention, is described as follows in conjunction with accompanying drawing.
As in figure 2 it is shown, have N-type extension drift region 2 on N-type substrate heavily doped region 1.
N-type extension drift region 2 has cellular region 100 and termination environment 101, in the top plan view of device, termination environment 101
Be in outer ring, cellular region 100 by cellular region 100 around encirclement, cellular region 100 is protected including.
There is in N-type extension drift region 2 multiple p-type semi-insulating post district 32, cellular region 100 has two p-types half absolutely
Yuan Zhu district 32, has more multiple p-type semi-insulating post district 32, is uniformly distributed in termination environment 101 in termination environment 101, p-type is semi-insulating
Post district 32 or single material, or by semiconductor insulating material and the composite construction of insulant, when post district 32 is
During composite construction, semiconductor insulating material is located close to the side of extension drift region.
Described multiple p-types semi-insulating post district 32, also each has the first p-type doped region 31, and top all has bottom it
Having the second p-type doped region 33, the doping content of the first p-type doped region 31 and the second p-type doped region 33 is p-type semi-insulating post district
2 to 5 times of 32, and impurity can be uniformly distributed, it is also possible to it is to present the distribution that middle dense both sides are light in the horizontal direction.
In cellular region 100, in cross-sectional plane, between two p-type semi-insulating post districts 32, there are groove 4, described groove 4 inwall
Surface is formed with gate oxidation films 5, fills polysilicon and form grid 6 in groove 4, and gate oxidation films 5 is grid 6 and groove 4 to be isolated.
Region between described gate trench 4 left and right sides and p-type semi-insulating post district 32 forms well region 7, on well region 7 top
Form source region 8, source region 8 and well region 7 and connect earth potential by contact hole 9.
More than it is the structure of p-type super-junction laterally bilateral diffusion MOS FET device of the present invention, by the semi-insulating post of p-type
Bottom district 32, the doping content of (the most described first p-type doped region 31) improves, and effectively suppresses substrate-assisted depletion effect, improves
Longitudinal voltage endurance capability of device improves.I.e. exhausting simultaneously by N-type extension drift region, both sides 2 bottom p-type semi-insulating post district 32
Weighed 1 doping by bottom N-type substrate to exhaust and affected, make the device longitudinal voltage carrying capacity theoretical value less than design.Although
The degree of depth increasing p-type semi-insulating post district 32 can simply solve this problem, but increase is process costs simultaneously, the present invention
Superiority by the scheme of the doping content raising bottom p-type semi-insulating post district 32 is self-evident.
It addition, the doping content of top, p-type semi-insulating post district 32 (i.e. forming the second described p-type doped region 33) improves,
The suction boron of effective suppression silicon face field oxygen and interlayer film tells phosphorus effect.I.e. top, p-type semi-insulating post district produces in actual process
During can cave inward, as it is shown on figure 3, cause the actual lateral breakdown voltage of device less than design theory value, make device overall
Breakdown voltage declines.Improved by the doping content at top, p-type semi-insulating post district, device under the effect of transverse electric field, surface
It is easier to exhaust, is depressed in making ionization by collision in silicon body, it is to avoid the generation of surface breakdown, as shown in Figure 4.Simultaneously for passing through
In p-type low-doped compensation art production process, p-type semi-insulating post district top indent, belongs to identical technical solution, also exists
In protection scope of the present invention.
Claims (5)
1. a p-type super-junction laterally bilateral diffusion MOS FET device, including N-type substrate heavily doped region and N-type extension drift region, it is special
Levy and be:
N-type extension drift region is positioned on N-type substrate heavily doped region；
Having cellular region and termination environment in described N-type extension drift region, in the top plan view of device, termination environment is positioned at cellular region
Cellular region cincture is surrounded by outer ring；
In cross-sectional plane, described cellular region has two p-type semi-insulating post districts, termination environment has more multiple p-type semi-insulating
Post district, is uniformly distributed in the termination region；
Described multiple p-types semi-insulating post district, also each has the first p-type doped region, and top is respectively provided with the second p-type bottom it
Doped region；The doping content of described first p-type doped region and the second p-type doped region is 2～5 times of p-type semi-insulating post district, and miscellaneous
Matter is to be uniformly distributed or in the horizontal direction in the distribution that middle dense both sides are light；
In cellular region, between two p-type semi-insulating post districts, a groove, described trench wall surface is had to be formed with gate oxidation films,
Fill polysilicon in groove and form grid；
Region between the both sides of described groove and p-type semi-insulating post district is respectively formed well region, forms source region, source region on well region top
Earth potential is connected by contact hole with well region.
2. p-type super-junction laterally bilateral diffusion MOS FET device as claimed in claim 1, it is characterised in that: the semi-insulating post of described p-type
District is homogenous material, or semiconductor insulating material and the composite construction of insulant.
3. p-type super-junction laterally bilateral diffusion MOS FET device as claimed in claim 2, it is characterised in that: the semi-insulating post of described p-type
When district is the composite construction of semiconductor insulating material and insulant, semiconductor insulating material is positioned against side, extension drift region.
4. p-type super-junction laterally bilateral diffusion MOS FET device as claimed in claim 1, it is characterised in that: described contact hole is to wear
Source region directly contacts with well region thoroughly, makes well region and source region share contact hole；Or stop at source region, by extra p-type hole
Injecting, formation contacts with well region.
5. p-type super-junction laterally bilateral diffusion MOS FET device as claimed in claim 1, it is characterised in that: its table of described termination environment
Face is formed with an oxygen, polysilicon or Metal field plate；It is formed with field cut-off ring away from the outside in direction, cellular region；Its p-type half is absolutely
There is p-type shallow implant between Yuan Zhu district or the region that comprises p-type semi-insulating post district.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210206590.4A CN103515432B (en) | 2012-06-21 | 2012-06-21 | P-type super-junction laterally bilateral diffusion MOS FET device |
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|---|---|---|---|
| CN201210206590.4A CN103515432B (en) | 2012-06-21 | 2012-06-21 | P-type super-junction laterally bilateral diffusion MOS FET device |
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| CN103515432A CN103515432A (en) | 2014-01-15 |
| CN103515432B true CN103515432B (en) | 2016-11-16 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107342325B (en) * | 2017-06-30 | 2020-03-31 | 东南大学 | Transverse double-diffusion metal oxide semiconductor device |
| CN114220847B (en) * | 2022-02-22 | 2022-05-17 | 北京芯可鉴科技有限公司 | LDMOSFET, preparation method, chip and circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868856A (en) * | 2007-09-21 | 2010-10-20 | 飞兆半导体公司 | Superjunction structures for power devices and methods of manufacture |
| CN102208447A (en) * | 2011-05-20 | 2011-10-05 | 无锡新洁能功率半导体有限公司 | Semiconductor device with super-junction structure and manufacturing method thereof |
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| JP5198030B2 (en) * | 2007-10-22 | 2013-05-15 | 株式会社東芝 | Semiconductor element |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868856A (en) * | 2007-09-21 | 2010-10-20 | 飞兆半导体公司 | Superjunction structures for power devices and methods of manufacture |
| CN102208447A (en) * | 2011-05-20 | 2011-10-05 | 无锡新洁能功率半导体有限公司 | Semiconductor device with super-junction structure and manufacturing method thereof |
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