CN103872123A - N-channel radio frequency LDMOS (Lateral Double-diffused Metal Oxide Semiconductor field effect transistor) device and manufacturing method - Google Patents
N-channel radio frequency LDMOS (Lateral Double-diffused Metal Oxide Semiconductor field effect transistor) device and manufacturing method Download PDFInfo
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- CN103872123A CN103872123A CN201210536911.7A CN201210536911A CN103872123A CN 103872123 A CN103872123 A CN 103872123A CN 201210536911 A CN201210536911 A CN 201210536911A CN 103872123 A CN103872123 A CN 103872123A
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- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
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- 239000011574 phosphorus Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
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- 229910052796 boron Inorganic materials 0.000 claims description 9
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention discloses an N-channel radio frequency LDMOS (Lateral Double-diffused Metal Oxide Semiconductor field effect transistor) device. The drain drift region of the N-channel radio frequency LDMOS device is provided with a non-uniformly doped region; a Faraday shielding structure is divided into an upper layer and a lower layer, the first layer adopts a comb-shaped or mesh-shaped structure, the region not covered by the Faraday shielding structure is coincident with the non-uniformly doped region, the second layer is located above the first layer, the two Faraday shielding layers are connected via a metal contact connection line and are connected onto a substrate via an electric sinking channel. The first Faraday shielding layer enables conduction resistance, parasitic capacitance between the gate and the drain and parasitic capacitance between the drain and the source to be well balanced. The second Faraday shielding layer further reduces parasitic capacitance between the gate and the drain, and conduction resistance of the device, breakdown voltage and frequency characteristics can be well balanced. The invention also discloses the manufacturing method of the N-channel radio frequency LDMOS device.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, refer to especially a kind of N raceway groove radio frequency LDMOS device, the invention still further relates to the manufacture method of described N raceway groove radio frequency LDMOS device.
Background technology
In high-voltage radio-frequency field, the normal radio frequency LDMOS(LDMOS:Lateral Double-diffused Metal oxideSemiconductor field effect Transistor that uses: horizontal dual pervasion field effect transistor) because such devices possesses good voltage endurance capability and frequency characteristic.For further improving the reliability of device and the parasitic capacitance of reduction device, in the device of being everlasting, adopt faraday shield layer.As shown in Figure 1, to be traditional radio frequency LDMOS device architecture profile, on substrate 1, there is epitaxial loayer 2, source region 4 and drain region 5 lay respectively in tagma 10 and drift region 11, tagma 10 and drift region 11 intersection silicon faces have grid oxygen 8 and polysilicon gate 7, faraday shield layer 6 is positioned on polysilicon gate 7, and spacer dielectric layer 14 between Faraday cup and polysilicon gate 7.Faraday shield layer 6 is connected with source region 4 and electric sinking passage 3 by Metal Contact line 9, and electric sinking passage 3 connects substrate 1.Faraday shield layer 6 can move to screen below from gate edge by the highfield position of device inside, in the time of high-voltage applications, can reduce hot carrier injector grid, thereby improves the reliability of device.Meanwhile, the parasitic capacitance (Cgd) that faraday shield layer 6 also can significantly reduce between grid and drain electrode is miller capacitance, improves the frequency characteristic of device.But faraday shield layer 6 can be in 11 generation space charge region, the top layer 12(figure of device drift region shown in dotted line), form an electric field perpendicular to current path, the area of current path can be compressed in space charge region 12, vertical electric field can reduce carrier mobility, therefore the conducting resistance of device can improve, and current driving ability will decline.Meanwhile, faraday shield layer 6 and substrate 1 short circuit, the space charge 12 that screen below produces can increase the parasitic capacitance (Cds) between drain electrode and the source electrode of devices, is unfavorable for the frequency characteristic of device.Further improve drift region doping content, can improve the current driving ability of device, but the puncture voltage of device can decline again.Therefore, how between conducting resistance, puncture voltage and the frequency characteristic of device, to obtain good balance, just seem particularly important.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of N raceway groove radio frequency LDMOS device, improves device breakdown low pressure and frequency characteristic, reduces conducting resistance.
Another technical problem to be solved by this invention is to provide the manufacture method of described N raceway groove radio frequency LDMOS device.
For addressing the above problem, N raceway groove radio frequency LDMOS device of the present invention, be arranged in the epitaxial loayer on substrate, there is tagma and the drift region, drain region against contact mutually, the source region of described radio frequency LDMOS device is arranged in tagma, drain region is arranged in drift region, drain region, and tagma one side has the electric sinking passage that connects source region and substrate, and device surface has gate oxide and grid.
In the drift region, drain region of described N raceway groove radio frequency LDMOS device, also there is non-uniform doping district; Grid top has faraday screen shield structure, and faraday screen shield structure is divided into two-layer up and down, and ground floor faraday shield layer is positioned at polysilicon gate top, and spacer dielectric layer between polysilicon gate; Second layer faraday shield layer is positioned at the top of ground floor faraday shield layer, covers ground floor faraday shield layer, between blank medium; Ground floor faraday shield layer is connected by metal connecting line with ground floor faraday shield layer, and is connected on the electric sinking passage between source electrode and the substrate of N raceway groove radio frequency LDMOS device.
Further, the Shi Kao drain region, non-uniform doping district in described drift region, drain region is rectangle injection region, and the region between rectangle injection region and grid is horizontal or longitudinal multiple strips to be injected, or the injection zone of square matrix.
Further, described ground floor faraday shield layer is to adopt longitudinally, or horizontal comb teeth-shaped structure, or mesh-like structure; The region that does not cover faraday shield layer need overlap with the non-uniform doping district of drift region, drain region, it is the faraday shield layer of ground floor comb teeth-shaped or mesh-like, the non-uniform doping district that its below is multiple strips distributions or square matrix is just in time exposed in space between broach or mesh-like space, comb structure and strip are intermeshing, or the square matrix non-uniform doping district of mesh-like structure and below is complementary identical.
For addressing the above problem, the invention provides the manufacture method of described N raceway groove radio frequency LDMOS device, comprise following processing step:
The 1st step, Yanzhong completes tagma and injects outside, and the complete grid of N raceway groove radio frequency LDMOS device of epitaxial surface, carries out the injection of drift region, drain region;
The 2nd step, carries out the contact in source region and drain region and injects, and deposit insulating medium layer, makes ground floor faraday shield layer;
The 3rd step, deposit insulating medium layer, makes second layer faraday shield layer;
The 4th step, makes Metal Contact and connects, by ground floor and second layer faraday shield layer and source region, tagma and substrate short circuit.
Preferably, in described the 1st step, the extension adopting when N raceway groove radio frequency LDMOS device is time delay outside N-type, and epitaxy layer thickness is 1～10 micron, and doped chemical is phosphorus or arsenic, and foreign body concentration is 1.0x10
15～1.0x10
17atom/cubic centimetre; In the time that device adopts P type epitaxial loayer, epitaxy layer thickness is 1～10 micron, and doped chemical is boron, and foreign body concentration is 1.0x10
15～1.0x10
17atom/cubic centimetre; Inject in drain terminal one side, injection zone covers the whole drift region from grid to drain electrode again, and as main confined area, doped chemical is phosphorus or arsenic, and implantation dosage is 1.0x10
12～1.0x10
14atom/square centimeter, Implantation Energy is 100～500KeV; On main confined area basis, then carry out the injection of non-uniform doping drift region, implanted dopant is phosphorus or arsenic, and implantation dosage is 1.0x10
13～1.0x10
14atom/square centimeter, Implantation Energy is 30～300KeV, and injection zone, for being that rectangle injects by drain region, is horizontal or longitudinal strip or square matrix distribution by gate regions, and injection region width is 0.5～2 micron, and injection region spacing is 0.5～2 micron; After injection completes, through thermal process activator impurity, adopt short annealing, temperature is 900～1200 degrees Celsius, and the time is 10～30 seconds, or adopts diffusion annealing, and temperature is 900～1000 degrees Celsius, and the time is 30～60 minutes, completes the drift region of non-uniform doping.
Preferably, in described the 2nd step, insulating medium layer is that thickness is 0.5～2 micron by being combined to form of silica, silicon nitride, silicon oxynitride or three; Described faraday shield layer is to be formed by heavily doped polysilicon or metal, and thickness is 0.1～1 micron; The distance that faraday shield layer leaks side extending end and drain terminal contact hole interval is 1～10 micron; Ground floor faraday shield layer adopts horizontal or longitudinal comb teeth-shaped or mesh-like structure, the area coincidence that in the region that ensures not cover screen and drift region, adulterate in non-homogeneous drift region.
Preferably, the impurity of described polysilicon doping is phosphorus, or arsenic, or boron, and foreign body concentration is 1.0x10
18～5.0x10
20atom/cubic centimetre, the composite bed that the material that metal level adopts comprises any one or a few formation in aluminium, copper, tungsten, titanium, tantalum, molybdenum, platinum.
Preferably, in described the 3rd step, insulating medium layer is that thickness is 0.5～2 micron by being combined to form of silica, silicon nitride, silicon oxynitride or three; Described faraday shield layer is to be formed by heavily doped polysilicon or metal, and thickness is 0.1～1 micron; The distance that faraday shield layer leaks side extending end and drain terminal contact hole interval is 1～10 micron.
Preferably, the impurity of described polysilicon doping is phosphorus, or arsenic, or boron, and foreign body concentration is 1.0x10
18～5.0x10
20atom/cubic centimetre, the composite bed that the material that metal level adopts comprises any one or a few formation in aluminium, copper, tungsten, titanium, tantalum, molybdenum, platinum.
Preferably, described the 1st to the 4th step process method is for silicon-based devices, or compound semiconductor device.
N raceway groove radio frequency LDMOS device of the present invention, the drift region of device adopts non-uniform doping, can between puncture voltage and conducting resistance, obtain good balance; Ground floor faraday shield layer adopts comb teeth-shaped or mesh-like structure, the area coincidence that does not cover non-uniform doping in the region of screen and drift region, can reach well balanced between parasitic capacitance between parasitic capacitance and drain electrode and source electrode between conducting resistance, grid and drain electrode; Cover second layer screen, can further reduce parasitic capacitance between grid and drain electrode, between conducting resistance, puncture voltage and the frequency characteristic of device, can obtain good balance.
Brief description of the drawings
Fig. 1 is the structural representation of traditional RFLDMOS;
Fig. 2～11st, the each processing step schematic diagram of the present invention;
Figure 12 is process flow diagram of the present invention.
Description of reference numerals
The 1st, substrate, the 2nd, extension, the 3rd, electric sinking passage, the 4th, source region, the 5th, drain region, the 6th, faraday shield layer, the 7th, polysilicon gate, the 8th, gate oxide, the 9th, Metal Contact line, the 10th, tagma, the 11st, drift region, drain region or main confined area, the 12nd, space charge region, the 13rd, back metal, the 14th, insulating medium layer, the 15th, non-uniform doping district.
Embodiment
The structure of N raceway groove radio frequency LDMOS device of the present invention as shown in figure 11, be arranged in the epitaxial loayer 2 on substrate 1, there is tagma 10 and drift region, drain region (the main confined area) 11 against contact mutually, the source region 4 of described radio frequency LDMOS device is arranged in tagma 10, drain region 5 is arranged in drift region, drain region 11, tagma 10 1 sides have the electric sinking passage 3 that connects source region 4 and substrate 1, and device surface has gate oxide 8 and grid 7.
In the drift region, drain region 11 of described N raceway groove radio frequency LDMOS device, also there is non-uniform doping district 15; Grid 7 tops have faraday screen shield structure 6, and faraday screen shield structure is divided into two-layer up and down, and ground floor faraday shield layer 6 is positioned at polysilicon gate 7 tops, and spacer dielectric layer 14 between polysilicon gate 7; Second layer faraday shield layer is positioned at the top of ground floor faraday shield layer, covers ground floor faraday shield layer, between blank medium 14; Ground floor faraday shield layer is connected by metal connecting line 9 with second layer faraday shield layer, and is connected on the electric sinking passage 3 between source electrode 4 and the substrate 1 of N raceway groove radio frequency LDMOS device.
The manufacture method of N raceway groove radio frequency LDMOS device of the present invention, mainly comprises following several step:
The 1st step, as shown in Figure 2, adopts traditional handicraft to complete the grid 7 of device and the making in tagma 10, carries out drift region 11 and injects, and forms non-uniform doping.If what device adopted is N-type epitaxial loayer, epitaxial loayer 2 thickness are 1 to 10 micron, and doped chemical is phosphorus or arsenic, foreign body concentration 1.0x10
15～1.0x10
17atom/cubic centimetre, as main confined area (drift region, drain region) 11.If device adopts P type epitaxial loayer, epitaxy layer thickness is 1 to 10 micron, and doped chemical is boron, and foreign body concentration is 1.0x10
15～1.0x10
17atom/cubic centimetre, injects in drain terminal 5 one sides again, and injection zone covers the whole drift region from grid 7 to drain electrode 5, and as main confined area, doped chemical is phosphorus or arsenic, and implantation dosage is 1.0x10
12～1.0x10
14atom/square centimeter, Implantation Energy is 100～500KeV.On main confined area 11 bases, then carry out 15 doping of non-homogeneous drift region and inject, implanted dopant is phosphorus or arsenic, and implantation dosage is 1.0x10
13～1.0x10
14atom/square centimeter, Implantation Energy is 30～300KeV, injection zone is horizontal or longitudinal multiple strips or square matrix distribution, Fig. 3, Fig. 4, Fig. 5 are respectively the device vertical views after described the 1st step completes, 3 kinds of embodiment that inject form are shown, wherein Fig. 3 and Fig. 4 form doping to inject the form that multiple strips distribute, and be to form rectangle to inject away from the region of grid, be to adopt multiple horizontal strips or longitudinal strip near the region of grid, Fig. 5 has adopted a kind of distribution of square matrix.Injection region width is 0.5～2 micron, and injection region spacing is 0.5～2 micron.After injection completes, through thermal process activator impurity, can adopt short annealing, temperature is 900～1200 degrees Celsius, and the time is 10～30 seconds, and also can adopt diffusion annealing, temperature is 900～1000 degrees Celsius, and the time is 30～60 minutes, completes non-uniform doping district 15.
The 2nd step, as shown in Figure 6, completes source drain contact and injects, and deposit insulating medium layer 14, forms ground floor faraday shield layer 6.Insulating medium layer can being combined to form by silica, silicon nitride, silicon oxynitride or three, thickness is 0.5～2 micron, and faraday shield layer 6 can be formed by heavily doped polysilicon or metal, and thickness is 0.1～1 micron, polysilicon can mix phosphorus, arsenic or boron, and foreign body concentration is 1.0x10
18～5.0x10
20atom/cubic centimetre, metal level can adopt the complex metal layer of any one or a few formation in the metals such as aluminium, copper, tungsten, titanium, tantalum, molybdenum, platinum.Faraday shield layer 6 adopts horizontal or longitudinal comb teeth-shaped or mesh-like structure, not covering the region of screen overlaps with the region 15 of non-homogeneous drift region doping in drift region, it is the faraday shield layer 6 of ground floor comb teeth-shaped or mesh-like, the non-uniform doping district that its below is multiple strips distributions or square matrix is just in time exposed in space between broach or mesh-like space, broach and strip are intermeshing, or complementary the coincideing in square matrix non-uniform doping district 15 of mesh-like and below.As shown in Fig. 7, Fig. 8, Fig. 9, Fig. 7 and Fig. 8 are corresponding with above-mentioned Fig. 3 and Fig. 4 respectively, and Fig. 9 is corresponding with above-mentioned Fig. 5, represent respectively the faraday shield layer of horizontal comb teeth-shaped, longitudinal faraday shield layer and the faraday shield layer of mesh-like structure.
The 3rd step, as shown in figure 10, deposit insulating medium layer 14, forms second layer faraday shield layer 6.Insulating medium layer 14 can being combined to form by silica, silicon nitride, silicon oxynitride or three, thickness is 0.5～2 micron, and faraday shield layer 6 can be formed by heavily doped polysilicon or metal, and thickness is 0.1～1 micron, polysilicon can mix phosphorus, arsenic or boron, and foreign body concentration is 1.0x10
18～5.0x10
20atom/cubic centimetre, metal level can adopt the complex metal layer of any one or a few formation in the metals such as aluminium, copper, tungsten, titanium, tantalum, molybdenum, platinum.
The 4th step, as shown in figure 11, by two-layer faraday shield layer 6 and source electrode 4, tagma 10 and substrate 1 short circuit, completes element manufacturing by Metal Contact 9.Ground floor faraday shield layer 6 is 1～10 micron near the distance A of leaking side extending end and drain terminal contact hole 9 intervals, and second layer faraday shield layer 6 is 1～10 micron near the extending end of drain terminal 5 one sides and the distance B at drain terminal contact hole 9 intervals.Two spacing A, B need to ensure that the insulating barrier between faraday shield layer 6 and Metal Contact 9 has enough voltage endurance capabilities.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a N raceway groove radio frequency LDMOS device, be arranged in the epitaxial loayer on substrate, there is tagma and the drift region, drain region against contact mutually, the source region of described radio frequency LDMOS device is arranged in tagma, drain region is arranged in drift region, drain region, tagma one side has the electric sinking passage that connects source region and substrate, and device surface has gate oxide and grid, it is characterized in that:
In the drift region, drain region of described N raceway groove radio frequency LDMOS device, also there is non-uniform doping district; Grid top has faraday screen shield structure, and faraday screen shield structure is divided into two-layer up and down, and ground floor faraday shield layer is positioned at polysilicon gate top, and spacer dielectric layer between polysilicon gate; Second layer faraday shield layer is positioned at the top of ground floor faraday shield layer, covers ground floor faraday shield layer, between blank medium; Ground floor faraday shield layer is connected by metal connecting line with ground floor faraday shield layer, and is connected on the electric sinking passage between source electrode and the substrate of N raceway groove radio frequency LDMOS device.
2. N raceway groove radio frequency LDMOS device as claimed in claim 1, it is characterized in that: the Shi Kao drain region, non-uniform doping district in described drift region, drain region is rectangle injection region, region between rectangle injection region and grid is horizontal or longitudinal multiple strips to be injected, or the injection zone of square matrix.
3. the N raceway groove radio frequency LDMOS device as described in claim 1 and 2, is characterized in that: described ground floor faraday shield layer is to adopt longitudinally, or horizontal comb teeth-shaped structure, or mesh-like structure; The region that does not cover faraday shield layer need overlap with the non-uniform doping district of drift region, drain region, it is the faraday shield layer of ground floor comb teeth-shaped or mesh-like, the non-uniform doping district that its below is multiple strips distributions or square matrix is just in time exposed in space between broach or mesh-like space, comb structure and strip are intermeshing, or the square matrix non-uniform doping district of mesh-like structure and below is complementary identical.
4. the manufacture method of N raceway groove radio frequency LDMOS device as claimed in claim 1, is characterized in that: comprise following processing step:
The 1st step, Yanzhong completes tagma and injects outside, and the complete grid of N raceway groove radio frequency LDMOS device of epitaxial surface, carries out the injection of drift region, drain region;
The 2nd step, carries out the contact in source region and drain region and injects, and deposit insulating medium layer, makes ground floor faraday shield layer;
The 3rd step, deposit insulating medium layer, makes second layer faraday shield layer;
The 4th step, makes Metal Contact and connects, by ground floor and second layer faraday shield layer and source region, tagma and substrate short circuit.
5. the manufacture method of N raceway groove radio frequency LDMOS device as claimed in claim 4, it is characterized in that: in described the 1st step, the extension adopting when N raceway groove radio frequency LDMOS device is time delay outside N-type, and epitaxy layer thickness is 1～10 micron, doped chemical is phosphorus or arsenic, and foreign body concentration is 1.0x10
15～1.0x10
17atom/cubic centimetre; In the time that device adopts P type epitaxial loayer, epitaxy layer thickness is 1～10 micron, and doped chemical is boron, and foreign body concentration is 1.0x10
15～1.0x10
17atom/cubic centimetre; Inject in drain terminal one side, injection zone covers the whole drift region from grid to drain electrode again, and as main confined area, doped chemical is phosphorus or arsenic, and implantation dosage is 1.0x10
12～1.0x10
14atom/square centimeter, Implantation Energy is 100～500KeV; On main confined area basis, then carry out the injection of non-uniform doping drift region, implanted dopant is phosphorus or arsenic, and implantation dosage is 1.0x10
13～1.0x10
14atom/square centimeter, Implantation Energy is 30～300KeV, and injection zone, for being that rectangle injects by drain region, is horizontal or longitudinal strip or square matrix distribution by gate regions, and injection region width is 0.5～2 micron, and injection region spacing is 0.5～2 micron; After injection completes, through thermal process activator impurity, adopt short annealing, temperature is 900～1200 degrees Celsius, and the time is 10～30 seconds, or adopts diffusion annealing, and temperature is 900～1000 degrees Celsius, and the time is 30～60 minutes, completes the drift region of non-uniform doping.
6. the manufacture method of N raceway groove radio frequency LDMOS device as claimed in claim 4, is characterized in that: in described the 2nd step, insulating medium layer is that thickness is 0.5～2 micron by being combined to form of silica, silicon nitride, silicon oxynitride or three; Described faraday shield layer is to be formed by heavily doped polysilicon or metal, and thickness is 0.1～1 micron; The distance that faraday shield layer leaks side extending end and drain terminal contact hole interval is 1～10 micron; Ground floor faraday shield layer adopts horizontal or longitudinal comb teeth-shaped or mesh-like structure, the area coincidence that in the region that ensures not cover screen and drift region, adulterate in non-homogeneous drift region.
7. the manufacture method of N raceway groove radio frequency LDMOS device as claimed in claim 4, is characterized in that: the impurity of described polysilicon doping is phosphorus, or arsenic, or boron, and foreign body concentration is 1.0x10
18～5.0x10
20atom/cubic centimetre, the composite bed that the material that metal level adopts comprises any one or a few formation in aluminium, copper, tungsten, titanium, tantalum, molybdenum, platinum.
8. the manufacture method of N raceway groove radio frequency LDMOS device as claimed in claim 4, is characterized in that: in described the 3rd step, insulating medium layer is that thickness is 0.5～2 micron by being combined to form of silica, silicon nitride, silicon oxynitride or three; Described faraday shield layer is to be formed by heavily doped polysilicon or metal, and thickness is 0.1～1 micron; The distance that faraday shield layer leaks side extending end and drain terminal contact hole interval is 1～10 micron.
9. the manufacture method of N raceway groove radio frequency LDMOS device as claimed in claim 8, is characterized in that: the impurity of described polysilicon doping is phosphorus, or arsenic, or boron, and foreign body concentration is 1.0x10
18～5.0x10
20atom/cubic centimetre, the composite bed that the material that metal level adopts comprises any one or a few formation in aluminium, copper, tungsten, titanium, tantalum, molybdenum, platinum.
10. the manufacture method of N raceway groove radio frequency LDMOS device as claimed in claim 4, is characterized in that: described the 1st to the 4th step process method is for silicon-based devices, or compound semiconductor device.
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| CN113410300A (en) * | 2020-03-16 | 2021-09-17 | 电子科技大学 | High-voltage-resistance p-channel LDMOS device and preparation method thereof |
| CN113675262A (en) * | 2020-05-14 | 2021-11-19 | 苏州华太电子技术有限公司 | Field plate structure applied to semiconductor device and manufacturing method and application thereof |
| US11923453B2 (en) | 2019-10-08 | 2024-03-05 | Csmc Technologies Fab2 Co., Ltd. | LDMOS device and method for preparing same |
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| CN113410300B (en) * | 2020-03-16 | 2023-04-25 | 电子科技大学 | High-voltage-resistant p-channel LDMOS device and preparation method thereof |
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